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//////////////////////////////////////////////////////////////////////

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////  OR1200's register file read operands mux                    ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Mux for two register file read operands.                    ////

////                                                              ////

////  To Do:                                                      ////

////   - make it smaller and faster                               ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.7  2001/10/14 13:12:09  lampret

// MP3 version.

//

// Revision 1.1.1.1  2001/10/06 10:18:36  igorm

// no message

//

// Revision 1.2  2001/08/09 13:39:33  lampret

// Major clean-up.

//

// Revision 1.1  2001/07/20 00:46:05  lampret

// Development version of RTL. Libraries are missing.

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "defines.v"

module operandmuxes(

        // Clock and reset

        clk, rst,

        // Internal i/f

        ex_freeze, rf_dataa, rf_datab, ex_forw, wb_forw,

        simm, sel_a, sel_b, operand_a, operand_b, muxed_b

);

parameter width = `OPERAND_WIDTH;

//

// I/O

//

input                           clk;

input                           rst;

input                           ex_freeze;

input   [width-1:0]              rf_dataa;

input   [width-1:0]              rf_datab;

input   [width-1:0]              ex_forw;

input   [width-1:0]              wb_forw;

input   [width-1:0]              simm;

input   [`SEL_WIDTH-1:0] sel_a;

input   [`SEL_WIDTH-1:0] sel_b;

output  [width-1:0]              operand_a;

output  [width-1:0]              operand_b;

output  [width-1:0]              muxed_b;

//

// Internal wires and regs

//

reg     [width-1:0]              operand_a;

reg     [width-1:0]              operand_b;

reg     [width-1:0]              muxed_a;

reg     [width-1:0]              muxed_b;

//

// Operand A register

//

always @(posedge clk or posedge rst) begin

        if (rst)

                operand_a <= #1 32'd0;

        else if (!ex_freeze)

                operand_a <= #1 muxed_a;

end

//

// Operand B register

//

always @(posedge clk or posedge rst) begin

        if (rst)

                operand_b <= #1 32'd0;

        else if (!ex_freeze)

                operand_b <= #1 muxed_b;

end

//

// Forwarding logic for operand A register

//

always @(ex_forw or wb_forw or rf_dataa or sel_a) begin

        casex (sel_a)   // synopsys full_case parallel_case infer_mux

                `SEL_EX_FORW:

                        muxed_a = ex_forw;

                `SEL_WB_FORW:

                        muxed_a = wb_forw;

                default:

                        muxed_a = rf_dataa;

        endcase

end

//

// Forwarding logic for operand B register

//

always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin

        casex (sel_b)   // synopsys full_case parallel_case infer_mux

                `SEL_IMM:

                        muxed_b = simm;

                `SEL_EX_FORW:

                        muxed_b = ex_forw;

                `SEL_WB_FORW:

                        muxed_b = wb_forw;

                default:

                        muxed_b = rf_datab;

        endcase

end

endmodule