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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "general.h"
 
module or1200(
        clk, rst, pic_ints, clkdiv_by_2,
 
        // Instruction WISHBONE INTERFACE
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
 
        // Data WISHBONE INTERFACE
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
 
        // Trace
        tp_dir_in, tp_sel, tp_in, tp_out,
 
        // Power Management
        pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
        pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
 
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
parameter ppic_ints = `PIC_INTS;
 
//
// Instruction WISHBONE interface
//
input                   iwb_clk_i;      // clock input
input                   iwb_rst_i;      // reset input
input                   iwb_ack_i;      // normal termination
input                   iwb_err_i;      // termination w/ error
input                   iwb_rty_i;      // termination w/ retry
input [dw-1:0]           iwb_dat_i;      // input data bus
output                  iwb_cyc_o;      // cycle valid output
output [aw-1:0]          iwb_adr_o;      // address bus outputs
output                  iwb_stb_o;      // strobe output
output                  iwb_we_o;       // indicates write transfer
output [3:0]             iwb_sel_o;      // byte select outputs
output [dw-1:0]          iwb_dat_o;      // output data bus
 
//
// Data WISHBONE interface
//
input                   dwb_clk_i;      // clock input
input                   dwb_rst_i;      // reset input
input                   dwb_ack_i;      // normal termination
input                   dwb_err_i;      // termination w/ error
input                   dwb_rty_i;      // termination w/ retry
input [dw-1:0]           dwb_dat_i;      // input data bus
output                  dwb_cyc_o;      // cycle valid output
output [aw-1:0]          dwb_adr_o;      // address bus outputs
output                  dwb_stb_o;      // strobe output
output                  dwb_we_o;       // indicates write transfer
output [3:0]             dwb_sel_o;      // byte select outputs
output [dw-1:0]          dwb_dat_o;      // output data bus
 
//
// System
//
input                   clk;
input                   rst;
input                   clkdiv_by_2;
input [ppic_ints-1:0]    pic_ints;
 
// CPU and PM
input                   pm_cpustall;
output                  pm_clksd;
output                  pm_dc_gate;
output                  pm_ic_gate;
output                  pm_dmmu_gate;
output                  pm_immu_gate;
output                  pm_tt_gate;
output                  pm_cpu_gate;
output                  pm_wakeup;
output                  pm_lvolt;
 
// DC to BIU
wire                    dcbiu_rdy;
wire [dw-1:0]            dcbiu_from_biu;
wire [dw-1:0]            dcbiu_to_biu;
wire [aw-1:0]            dcbiu_addr;
wire                    dcbiu_read;
wire                    dcbiu_write;
 
// IC to BIU
wire                    icbiu_rdy;
wire [dw-1:0]            icbiu_from_biu;
wire [aw-1:0]            icbiu_addr;
wire                    icbiu_read;
 
// CPU's SPR access to various RISC units (shared wires)
wire [aw-1:0]            spr_addr;
wire [dw-1:0]            spr_dat_cpu;
wire [31:0]              spr_cs;
wire                    spr_we;
 
// DC and CPU's LSU
wire                    dclsu_stall;
wire [aw-1:0]            dclsu_addr;
wire [aw-1:0]            dclsu_from_dc;
wire [aw-1:0]            dclsu_to_dc;
wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
 
// IC and CPU's ifetch
wire                    icfetch_stall;
wire [aw-1:0]            icfetch_addr;
wire [dw-1:0]            icfetch_dataout;
 
// Connection between CPU and PIC
wire [dw-1:0]            spr_dat_pic;
wire                    pic_wakeup;
wire                    int_low;
wire                    int_high;
wire                    int_high_tt;
 
// Connection between CPU and PM
wire [dw-1:0]            spr_dat_pm;
 
// CPU and TT
wire [dw-1:0]            spr_dat_tt;
wire                    tt_int;
 
// CPU and external Trace port
input                   tp_dir_in;
input [1:0]              tp_sel;
input [dw-1:0]           tp_in;
output [dw-1:0]          tp_out;
 
// Trace port and caches/MMUs
wire [`TP2W_WIDTH-1:0]   tp2w;
wire [`TP3W_WIDTH-1:0]   tp3w;
wire [`TP4W_WIDTH-1:0]   tp4w;
wire [dw-1:0]            tpdw;
 
//
// Assignments
//
assign int_high_tt = int_high | tt_int;
 
//
// Instantiation of Instruction WISHBONE BIU
//
wb_biu iwb_biu(
        // WISHBONE interface
        .wb_clk_i(iwb_clk_i),
        .wb_rst_i(iwb_rst_i),
        .wb_ack_i(iwb_ack_i),
        .wb_err_i(iwb_err_i),
        .wb_rty_i(iwb_rty_i),
        .wb_dat_i(iwb_dat_i),
        .wb_cyc_o(iwb_cyc_o),
        .wb_adr_o(iwb_adr_o),
        .wb_stb_o(iwb_stb_o),
        .wb_we_o(iwb_we_o),
        .wb_sel_o(iwb_sel_o),
        .wb_dat_o(iwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(32'b0),
        .biu_addr(icbiu_addr),
        .biu_read(icbiu_read),
        .biu_write(1'b0),
        .biu_rdy(icbiu_rdy),
        .biu_from_biu(icbiu_from_biu)
);
 
//
// Instantiation of Data WISHBONE BIU
//
wb_biu dwb_biu(
        // WISHBONE interface
        .wb_clk_i(dwb_clk_i),
        .wb_rst_i(dwb_rst_i),
        .wb_ack_i(dwb_ack_i),
        .wb_err_i(dwb_err_i),
        .wb_rty_i(dwb_rty_i),
        .wb_dat_i(dwb_dat_i),
        .wb_cyc_o(dwb_cyc_o),
        .wb_adr_o(dwb_adr_o),
        .wb_stb_o(dwb_stb_o),
        .wb_we_o(dwb_we_o),
        .wb_sel_o(dwb_sel_o),
        .wb_dat_o(dwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(dcbiu_to_biu),
        .biu_addr(dcbiu_addr),
        .biu_read(dcbiu_read),
        .biu_write(dcbiu_write),
        .biu_rdy(dcbiu_rdy),
        .biu_from_biu(dcbiu_from_biu)
);
 
//
// Instantiation of Instruction Cache
//
ic ic(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect IC to CPU's ifetch
        .icfetch_addr(icfetch_addr),
        .icfetch_op(`FETCHOP_LW),
        .icfetch_dataout(icfetch_dataout),
        .icfetch_stall(icfetch_stall),
 
        // These connect IC to BIU
        .icbiu_rdy(icbiu_rdy),
        .icbiu_datain(icbiu_from_biu),
        .icbiu_addr(icbiu_addr),
        .icbiu_read(icbiu_read),
 
        // These connect IC to SPRS
        .spr_dat_i(spr_dat_cpu),
 
        // Trace port
        .tp4w(tp4w),
        .tpdw(tpdw)
);
 
//
// Instantiation of Instruction Cache
//
cpu cpu(
        .clk(clk),
        .rst(rst),
 
        // These connect IC and IFETCHER inside CPU
        .ic_insn(icfetch_dataout),
        .ic_pcaddr(icfetch_addr),
        .ic_stall(icfetch_stall),
 
        // These connect CPU to external Trace port
        .tp_dir_in(tp_dir_in),
        .tp_sel(tp_sel),
        .tp_in(tp_in),
        .tp_out(tp_out),
 
        // These connect DC and CPU's LSU
        .dclsu_stall(dclsu_stall),
        .dclsu_addr(dclsu_addr),
        .dclsu_datain(dclsu_from_dc),
        .dclsu_dataout(dclsu_to_dc),
        .dclsu_lsuop(dclsu_lsuop),
 
        // These connect PIC and CPU's EXCEPT
        .int_high(int_high_tt),
        .int_low(int_low),
 
        // SPRs
        .spr_addr(spr_addr),
        .spr_dataout(spr_dat_cpu),
        .spr_dat_pic(spr_dat_pic),
        .spr_dat_tt(spr_dat_tt),
        .spr_dat_pm(spr_dat_pm),
        .spr_cs(spr_cs),
        .spr_we(spr_we),
 
        // These connect trace port to caches and MMUs
        .tp2w(tp2w),
        .tp3w(tp3w),
        .tp4w(tp4w),
        .tpdw(tpdw)
);
 
//
// Instantiation of Data Cache
//
dc dc(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect DC to CPU's LSU
        .dclsu_addr(dclsu_addr),
        .dclsu_lsuop(dclsu_lsuop),
        .dclsu_datain(dclsu_to_dc),
        .dclsu_dataout(dclsu_from_dc),
        .dclsu_stall(dclsu_stall),
 
        // These connect DC to BIU
        .dcbiu_rdy(dcbiu_rdy),
        .dcbiu_datain(dcbiu_from_biu),
        .dcbiu_dataout(dcbiu_to_biu),
        .dcbiu_addr(dcbiu_addr),
        .dcbiu_read(dcbiu_read),
        .dcbiu_write(dcbiu_write),
 
        // Trace port
        .tp2w(tp2w),
        .tp3w(tp3w),
        .tpdw(tpdw)
);
 
//
// Programmable interrupt controller
//
pic pic(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_PIC]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pic),
        .pic_wakeup(pic_wakeup),
        .int_low(int_low),
        .int_high(int_high),
 
        // PIC Interface
        .pic_int(pic_ints)
);
 
//
// Instantiation of Tick timer
//
tt tt(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_TT]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_tt),
        .int(tt_int)
);
 
//
// Instantiation of Power Management
//
pm pm(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .pic_wakeup(pic_wakeup),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pm),
 
        // Power Management Interface
        .pm_clksd(pm_clksd),
        .pm_cpustall(pm_cpustall),
        .pm_dc_gate(pm_dc_gate),
        .pm_ic_gate(pm_ic_gate),
        .pm_dmmu_gate(pm_dmmu_gate),
        .pm_immu_gate(pm_immu_gate),
        .pm_tt_gate(pm_tt_gate),
        .pm_cpu_gate(pm_cpu_gate),
        .pm_wakeup(pm_wakeup),
        .pm_lvolt(pm_lvolt)
);
 
 
endmodule
 
 
 
 
 
 
 

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [or1200.v] - Blame information for rev 161

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200 Top Level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OR1200 Top Level ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48
49			`include "general.h"
50
51			`module or1200(`
52			`clk, rst, pic_ints, clkdiv_by_2,`
53
54			`// Instruction WISHBONE INTERFACE`
55			`iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,`
56			`iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,`
57
58			`// Data WISHBONE INTERFACE`
59			`dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,`
60			`dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,`
61
62			`// Trace`
63			`tp_dir_in, tp_sel, tp_in, tp_out,`
64
65			`// Power Management`
66			`pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,`
67			`pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt`
68
69			`);`
70
71			parameter dw = `OPERAND_WIDTH;
72			parameter aw = `OPERAND_WIDTH;
73			parameter ppic_ints = `PIC_INTS;
74
75			`//`
76			`// Instruction WISHBONE interface`
77			`//`
78			`input iwb_clk_i; // clock input`
79			`input iwb_rst_i; // reset input`
80			`input iwb_ack_i; // normal termination`
81			`input iwb_err_i; // termination w/ error`
82			`input iwb_rty_i; // termination w/ retry`
83			`input [dw-1:0] iwb_dat_i; // input data bus`
84			`output iwb_cyc_o; // cycle valid output`
85			`output [aw-1:0] iwb_adr_o; // address bus outputs`
86			`output iwb_stb_o; // strobe output`
87			`output iwb_we_o; // indicates write transfer`
88			`output [3:0] iwb_sel_o; // byte select outputs`
89			`output [dw-1:0] iwb_dat_o; // output data bus`
90
91			`//`
92			`// Data WISHBONE interface`
93			`//`
94			`input dwb_clk_i; // clock input`
95			`input dwb_rst_i; // reset input`
96			`input dwb_ack_i; // normal termination`
97			`input dwb_err_i; // termination w/ error`
98			`input dwb_rty_i; // termination w/ retry`
99			`input [dw-1:0] dwb_dat_i; // input data bus`
100			`output dwb_cyc_o; // cycle valid output`
101			`output [aw-1:0] dwb_adr_o; // address bus outputs`
102			`output dwb_stb_o; // strobe output`
103			`output dwb_we_o; // indicates write transfer`
104			`output [3:0] dwb_sel_o; // byte select outputs`
105			`output [dw-1:0] dwb_dat_o; // output data bus`
106
107			`//`
108			`// System`
109			`//`
110			`input clk;`
111			`input rst;`
112			`input clkdiv_by_2;`
113			`input [ppic_ints-1:0] pic_ints;`
114
115			`// CPU and PM`
116			`input pm_cpustall;`
117			`output pm_clksd;`
118			`output pm_dc_gate;`
119			`output pm_ic_gate;`
120			`output pm_dmmu_gate;`
121			`output pm_immu_gate;`
122			`output pm_tt_gate;`
123			`output pm_cpu_gate;`
124			`output pm_wakeup;`
125			`output pm_lvolt;`
126
127			`// DC to BIU`
128			`wire dcbiu_rdy;`
129			`wire [dw-1:0] dcbiu_from_biu;`
130			`wire [dw-1:0] dcbiu_to_biu;`
131			`wire [aw-1:0] dcbiu_addr;`
132			`wire dcbiu_read;`
133			`wire dcbiu_write;`
134
135			`// IC to BIU`
136			`wire icbiu_rdy;`
137			`wire [dw-1:0] icbiu_from_biu;`
138			`wire [aw-1:0] icbiu_addr;`
139			`wire icbiu_read;`
140
141			`// CPU's SPR access to various RISC units (shared wires)`
142			`wire [aw-1:0] spr_addr;`
143			`wire [dw-1:0] spr_dat_cpu;`
144			`wire [31:0] spr_cs;`
145			`wire spr_we;`
146
147			`// DC and CPU's LSU`
148			`wire dclsu_stall;`
149			`wire [aw-1:0] dclsu_addr;`
150			`wire [aw-1:0] dclsu_from_dc;`
151			`wire [aw-1:0] dclsu_to_dc;`
152			wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
153
154			`// IC and CPU's ifetch`
155			`wire icfetch_stall;`
156			`wire [aw-1:0] icfetch_addr;`
157			`wire [dw-1:0] icfetch_dataout;`
158
159			`// Connection between CPU and PIC`
160			`wire [dw-1:0] spr_dat_pic;`
161			`wire pic_wakeup;`
162			`wire int_low;`
163			`wire int_high;`
164			`wire int_high_tt;`
165
166			`// Connection between CPU and PM`
167			`wire [dw-1:0] spr_dat_pm;`
168
169			`// CPU and TT`
170			`wire [dw-1:0] spr_dat_tt;`
171			`wire tt_int;`
172
173			`// CPU and external Trace port`
174			`input tp_dir_in;`
175			`input [1:0] tp_sel;`
176			`input [dw-1:0] tp_in;`
177			`output [dw-1:0] tp_out;`
178
179			`// Trace port and caches/MMUs`
180			wire [`TP2W_WIDTH-1:0] tp2w;
181			wire [`TP3W_WIDTH-1:0] tp3w;
182			wire [`TP4W_WIDTH-1:0] tp4w;
183			`wire [dw-1:0] tpdw;`
184
185			`//`
186			`// Assignments`
187			`//`
188			`assign int_high_tt = int_high \| tt_int;`
189
190			`//`
191			`// Instantiation of Instruction WISHBONE BIU`
192			`//`
193			`wb_biu iwb_biu(`
194			`// WISHBONE interface`
195			`.wb_clk_i(iwb_clk_i),`
196			`.wb_rst_i(iwb_rst_i),`
197			`.wb_ack_i(iwb_ack_i),`
198			`.wb_err_i(iwb_err_i),`
199			`.wb_rty_i(iwb_rty_i),`
200			`.wb_dat_i(iwb_dat_i),`
201			`.wb_cyc_o(iwb_cyc_o),`
202			`.wb_adr_o(iwb_adr_o),`
203			`.wb_stb_o(iwb_stb_o),`
204			`.wb_we_o(iwb_we_o),`
205			`.wb_sel_o(iwb_sel_o),`
206			`.wb_dat_o(iwb_dat_o),`
207
208			`// Internal RISC bus`
209			`.biu_to_biu(32'b0),`
210			`.biu_addr(icbiu_addr),`
211			`.biu_read(icbiu_read),`
212			`.biu_write(1'b0),`
213			`.biu_rdy(icbiu_rdy),`
214			`.biu_from_biu(icbiu_from_biu)`
215			`);`
216
217			`//`
218			`// Instantiation of Data WISHBONE BIU`
219			`//`
220			`wb_biu dwb_biu(`
221			`// WISHBONE interface`
222			`.wb_clk_i(dwb_clk_i),`
223			`.wb_rst_i(dwb_rst_i),`
224			`.wb_ack_i(dwb_ack_i),`
225			`.wb_err_i(dwb_err_i),`
226			`.wb_rty_i(dwb_rty_i),`
227			`.wb_dat_i(dwb_dat_i),`
228			`.wb_cyc_o(dwb_cyc_o),`
229			`.wb_adr_o(dwb_adr_o),`
230			`.wb_stb_o(dwb_stb_o),`
231			`.wb_we_o(dwb_we_o),`
232			`.wb_sel_o(dwb_sel_o),`
233			`.wb_dat_o(dwb_dat_o),`
234
235			`// Internal RISC bus`
236			`.biu_to_biu(dcbiu_to_biu),`
237			`.biu_addr(dcbiu_addr),`
238			`.biu_read(dcbiu_read),`
239			`.biu_write(dcbiu_write),`
240			`.biu_rdy(dcbiu_rdy),`
241			`.biu_from_biu(dcbiu_from_biu)`
242			`);`
243
244			`//`
245			`// Instantiation of Instruction Cache`
246			`//`
247			`ic ic(`
248			`.clk(clk),`
249			`.rst(rst),`
250			`.clkdiv_by_2(clkdiv_by_2),`
251
252			`// These connect IC to CPU's ifetch`
253			`.icfetch_addr(icfetch_addr),`
254			.icfetch_op(`FETCHOP_LW),
255			`.icfetch_dataout(icfetch_dataout),`
256			`.icfetch_stall(icfetch_stall),`
257
258			`// These connect IC to BIU`
259			`.icbiu_rdy(icbiu_rdy),`
260			`.icbiu_datain(icbiu_from_biu),`
261			`.icbiu_addr(icbiu_addr),`
262			`.icbiu_read(icbiu_read),`
263
264			`// These connect IC to SPRS`
265			`.spr_dat_i(spr_dat_cpu),`
266
267			`// Trace port`
268			`.tp4w(tp4w),`
269			`.tpdw(tpdw)`
270			`);`
271
272			`//`
273			`// Instantiation of Instruction Cache`
274			`//`
275			`cpu cpu(`
276			`.clk(clk),`
277			`.rst(rst),`
278
279			`// These connect IC and IFETCHER inside CPU`
280			`.ic_insn(icfetch_dataout),`
281			`.ic_pcaddr(icfetch_addr),`
282			`.ic_stall(icfetch_stall),`
283
284			`// These connect CPU to external Trace port`
285			`.tp_dir_in(tp_dir_in),`
286			`.tp_sel(tp_sel),`
287			`.tp_in(tp_in),`
288			`.tp_out(tp_out),`
289
290			`// These connect DC and CPU's LSU`
291			`.dclsu_stall(dclsu_stall),`
292			`.dclsu_addr(dclsu_addr),`
293			`.dclsu_datain(dclsu_from_dc),`
294			`.dclsu_dataout(dclsu_to_dc),`
295			`.dclsu_lsuop(dclsu_lsuop),`
296
297			`// These connect PIC and CPU's EXCEPT`
298			`.int_high(int_high_tt),`
299			`.int_low(int_low),`
300
301			`// SPRs`
302			`.spr_addr(spr_addr),`
303			`.spr_dataout(spr_dat_cpu),`
304			`.spr_dat_pic(spr_dat_pic),`
305			`.spr_dat_tt(spr_dat_tt),`
306			`.spr_dat_pm(spr_dat_pm),`
307			`.spr_cs(spr_cs),`
308			`.spr_we(spr_we),`
309
310			`// These connect trace port to caches and MMUs`
311			`.tp2w(tp2w),`
312			`.tp3w(tp3w),`
313			`.tp4w(tp4w),`
314			`.tpdw(tpdw)`
315			`);`
316
317			`//`
318			`// Instantiation of Data Cache`
319			`//`
320			`dc dc(`
321			`.clk(clk),`
322			`.rst(rst),`
323			`.clkdiv_by_2(clkdiv_by_2),`
324
325			`// These connect DC to CPU's LSU`
326			`.dclsu_addr(dclsu_addr),`
327			`.dclsu_lsuop(dclsu_lsuop),`
328			`.dclsu_datain(dclsu_to_dc),`
329			`.dclsu_dataout(dclsu_from_dc),`
330			`.dclsu_stall(dclsu_stall),`
331
332			`// These connect DC to BIU`
333			`.dcbiu_rdy(dcbiu_rdy),`
334			`.dcbiu_datain(dcbiu_from_biu),`
335			`.dcbiu_dataout(dcbiu_to_biu),`
336			`.dcbiu_addr(dcbiu_addr),`
337			`.dcbiu_read(dcbiu_read),`
338			`.dcbiu_write(dcbiu_write),`
339
340			`// Trace port`
341			`.tp2w(tp2w),`
342			`.tp3w(tp3w),`
343			`.tpdw(tpdw)`
344			`);`
345
346			`//`
347			`// Programmable interrupt controller`
348			`//`
349			`pic pic(`
350			`// RISC Internal Interface`
351			`.clk(clk),`
352			`.rst(rst),`
353			.spr_cs(spr_cs[`SPR_GROUP_PIC]),
354			`.spr_write(spr_we),`
355			`.spr_addr(spr_addr),`
356			`.spr_dat_i(spr_dat_cpu),`
357			`.spr_dat_o(spr_dat_pic),`
358			`.pic_wakeup(pic_wakeup),`
359			`.int_low(int_low),`
360			`.int_high(int_high),`
361
362			`// PIC Interface`
363			`.pic_int(pic_ints)`
364			`);`
365
366			`//`
367			`// Instantiation of Tick timer`
368			`//`
369			`tt tt(`
370			`// RISC Internal Interface`
371			`.clk(clk),`
372			`.rst(rst),`
373			.spr_cs(spr_cs[`SPR_GROUP_TT]),
374			`.spr_write(spr_we),`
375			`.spr_addr(spr_addr),`
376			`.spr_dat_i(spr_dat_cpu),`
377			`.spr_dat_o(spr_dat_tt),`
378			`.int(tt_int)`
379			`);`
380
381			`//`
382			`// Instantiation of Power Management`
383			`//`
384			`pm pm(`
385			`// RISC Internal Interface`
386			`.clk(clk),`
387			`.rst(rst),`
388			`.pic_wakeup(pic_wakeup),`
389			`.spr_write(spr_we),`
390			`.spr_addr(spr_addr),`
391			`.spr_dat_i(spr_dat_cpu),`
392			`.spr_dat_o(spr_dat_pm),`
393
394			`// Power Management Interface`
395			`.pm_clksd(pm_clksd),`
396			`.pm_cpustall(pm_cpustall),`
397			`.pm_dc_gate(pm_dc_gate),`
398			`.pm_ic_gate(pm_ic_gate),`
399			`.pm_dmmu_gate(pm_dmmu_gate),`
400			`.pm_immu_gate(pm_immu_gate),`
401			`.pm_tt_gate(pm_tt_gate),`
402			`.pm_cpu_gate(pm_cpu_gate),`
403			`.pm_wakeup(pm_wakeup),`
404			`.pm_lvolt(pm_lvolt)`
405			`);`
406
407
408			`endmodule`
409
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415