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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "general.h"
 
module or1200(
        clk, rst, pic_ints, clkdiv_by_2,
 
        // Instruction WISHBONE INTERFACE
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
 
        // Data WISHBONE INTERFACE
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
 
        // Trace
        tp_dir_in, tp_sel, tp_in, tp_out,
 
        // Power Management
        pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
        pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
 
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
parameter ppic_ints = `PIC_INTS;
 
//
// Instruction WISHBONE interface
//
input                   iwb_clk_i;      // clock input
input                   iwb_rst_i;      // reset input
input                   iwb_ack_i;      // normal termination
input                   iwb_err_i;      // termination w/ error
input                   iwb_rty_i;      // termination w/ retry
input [dw-1:0]           iwb_dat_i;      // input data bus
output                  iwb_cyc_o;      // cycle valid output
output [aw-1:0]          iwb_adr_o;      // address bus outputs
output                  iwb_stb_o;      // strobe output
output                  iwb_we_o;       // indicates write transfer
output [3:0]             iwb_sel_o;      // byte select outputs
output [dw-1:0]          iwb_dat_o;      // output data bus
 
//
// Data WISHBONE interface
//
input                   dwb_clk_i;      // clock input
input                   dwb_rst_i;      // reset input
input                   dwb_ack_i;      // normal termination
input                   dwb_err_i;      // termination w/ error
input                   dwb_rty_i;      // termination w/ retry
input [dw-1:0]           dwb_dat_i;      // input data bus
output                  dwb_cyc_o;      // cycle valid output
output [aw-1:0]          dwb_adr_o;      // address bus outputs
output                  dwb_stb_o;      // strobe output
output                  dwb_we_o;       // indicates write transfer
output [3:0]             dwb_sel_o;      // byte select outputs
output [dw-1:0]          dwb_dat_o;      // output data bus
 
//
// System
//
input                   clk;
input                   rst;
input                   clkdiv_by_2;
input [ppic_ints-1:0]    pic_ints;
 
// CPU and PM
input                   pm_cpustall;
output                  pm_clksd;
output                  pm_dc_gate;
output                  pm_ic_gate;
output                  pm_dmmu_gate;
output                  pm_immu_gate;
output                  pm_tt_gate;
output                  pm_cpu_gate;
output                  pm_wakeup;
output                  pm_lvolt;
 
// DC to BIU
wire                    dcbiu_rdy;
wire [dw-1:0]            dcbiu_from_biu;
wire [dw-1:0]            dcbiu_to_biu;
wire [aw-1:0]            dcbiu_addr;
wire                    dcbiu_read;
wire                    dcbiu_write;
wire [3:0]               dcbiu_sel;
 
// IC to BIU
wire                    icbiu_rdy;
wire [dw-1:0]            icbiu_from_biu;
wire [aw-1:0]            icbiu_addr;
wire                    icbiu_read;
 
// CPU's SPR access to various RISC units (shared wires)
wire [aw-1:0]            spr_addr;
wire [dw-1:0]            spr_dat_cpu;
wire [31:0]              spr_cs;
wire                    spr_we;
 
// DC and CPU's LSU
wire                    dclsu_stall;
wire [aw-1:0]            dclsu_addr;
wire [aw-1:0]            dclsu_from_dc;
wire [aw-1:0]            dclsu_to_dc;
wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
 
// IC and CPU's ifetch
wire                    icfetch_stall;
wire [aw-1:0]            icfetch_addr;
wire [dw-1:0]            icfetch_dataout;
 
// Connection between CPU and PIC
wire [dw-1:0]            spr_dat_pic;
wire                    pic_wakeup;
wire                    int_low;
wire                    int_high;
wire                    int_high_tt;
 
// Connection between CPU and PM
wire [dw-1:0]            spr_dat_pm;
 
// CPU and TT
wire [dw-1:0]            spr_dat_tt;
wire                    tt_int;
 
// CPU and external Trace port
input                   tp_dir_in;
input [1:0]              tp_sel;
input [dw-1:0]           tp_in;
output [dw-1:0]          tp_out;
 
// Trace port and caches/MMUs
wire [`TP2W_WIDTH-1:0]   tp2w;
wire [`TP3W_WIDTH-1:0]   tp3w;
wire [`TP4W_WIDTH-1:0]   tp4w;
wire [dw-1:0]            tpdw;
 
//
// Assignments
//
assign int_high_tt = int_high | tt_int;
 
//
// Instantiation of Instruction WISHBONE BIU
//
wb_biu iwb_biu(
        // WISHBONE interface
        .wb_clk_i(iwb_clk_i),
        .wb_rst_i(iwb_rst_i),
        .wb_ack_i(iwb_ack_i),
        .wb_err_i(iwb_err_i),
        .wb_rty_i(iwb_rty_i),
        .wb_dat_i(iwb_dat_i),
        .wb_cyc_o(iwb_cyc_o),
        .wb_adr_o(iwb_adr_o),
        .wb_stb_o(iwb_stb_o),
        .wb_we_o(iwb_we_o),
        .wb_sel_o(iwb_sel_o),
        .wb_dat_o(iwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(32'b0),
        .biu_addr(icbiu_addr),
        .biu_read(icbiu_read),
        .biu_write(1'b0),
        .biu_rdy(icbiu_rdy),
        .biu_from_biu(icbiu_from_biu),
        .biu_sel(4'b1111)
);
 
//
// Instantiation of Data WISHBONE BIU
//
wb_biu dwb_biu(
        // WISHBONE interface
        .wb_clk_i(dwb_clk_i),
        .wb_rst_i(dwb_rst_i),
        .wb_ack_i(dwb_ack_i),
        .wb_err_i(dwb_err_i),
        .wb_rty_i(dwb_rty_i),
        .wb_dat_i(dwb_dat_i),
        .wb_cyc_o(dwb_cyc_o),
        .wb_adr_o(dwb_adr_o),
        .wb_stb_o(dwb_stb_o),
        .wb_we_o(dwb_we_o),
        .wb_sel_o(dwb_sel_o),
        .wb_dat_o(dwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(dcbiu_to_biu),
        .biu_addr(dcbiu_addr),
        .biu_read(dcbiu_read),
        .biu_write(dcbiu_write),
        .biu_rdy(dcbiu_rdy),
        .biu_from_biu(dcbiu_from_biu),
        .biu_sel(dcbiu_sel)
);
 
//
// Instantiation of Instruction Cache
//
ic ic(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect IC to CPU's ifetch
        .icfetch_addr(icfetch_addr),
        .icfetch_op(`FETCHOP_LW),
        .icfetch_dataout(icfetch_dataout),
        .icfetch_stall(icfetch_stall),
 
        // These connect IC to BIU
        .icbiu_rdy(icbiu_rdy),
        .icbiu_datain(icbiu_from_biu),
        .icbiu_addr(icbiu_addr),
        .icbiu_read(icbiu_read),
 
        // These connect IC to SPRS
        .spr_dat_i(spr_dat_cpu),
 
        // Trace port
        .tp4w(tp4w),
        .tpdw(tpdw)
);
 
//
// Instantiation of Instruction Cache
//
cpu cpu(
        .clk(clk),
        .rst(rst),
 
        // These connect IC and IFETCHER inside CPU
        .ic_insn(icfetch_dataout),
        .ic_pcaddr(icfetch_addr),
        .ic_stall(icfetch_stall),
 
        // These connect CPU to external Trace port
        .tp_dir_in(tp_dir_in),
        .tp_sel(tp_sel),
        .tp_in(tp_in),
        .tp_out(tp_out),
 
        // These connect DC and CPU's LSU
        .dclsu_stall(dclsu_stall),
        .dclsu_addr(dclsu_addr),
        .dclsu_datain(dclsu_from_dc),
        .dclsu_dataout(dclsu_to_dc),
        .dclsu_lsuop(dclsu_lsuop),
 
        // These connect PIC and CPU's EXCEPT
        .int_high(int_high_tt),
        .int_low(int_low),
 
        // SPRs
        .spr_addr(spr_addr),
        .spr_dataout(spr_dat_cpu),
        .spr_dat_pic(spr_dat_pic),
        .spr_dat_tt(spr_dat_tt),
        .spr_dat_pm(spr_dat_pm),
        .spr_cs(spr_cs),
        .spr_we(spr_we),
 
        // These connect trace port to caches and MMUs
        .tp2w(tp2w),
        .tp3w(tp3w),
        .tp4w(tp4w),
        .tpdw(tpdw)
);
 
//
// Instantiation of Data Cache
//
dc dc(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect DC to CPU's LSU
        .dclsu_addr(dclsu_addr),
        .dclsu_lsuop(dclsu_lsuop),
        .dclsu_datain(dclsu_to_dc),
        .dclsu_dataout(dclsu_from_dc),
        .dclsu_stall(dclsu_stall),
 
        // These connect DC to BIU
        .dcbiu_rdy(dcbiu_rdy),
        .dcbiu_datain(dcbiu_from_biu),
        .dcbiu_dataout(dcbiu_to_biu),
        .dcbiu_addr(dcbiu_addr),
        .dcbiu_read(dcbiu_read),
        .dcbiu_write(dcbiu_write),
        .dcbiu_sel(dcbiu_sel),
 
        // Trace port
        .tp2w(tp2w),
        .tp3w(tp3w),
        .tpdw(tpdw)
);
 
//
// Programmable interrupt controller
//
pic pic(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_PIC]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pic),
        .pic_wakeup(pic_wakeup),
        .int_low(int_low),
        .int_high(int_high),
 
        // PIC Interface
        .pic_int(pic_ints)
);
 
//
// Instantiation of Tick timer
//
tt tt(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_TT]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_tt),
        .int(tt_int)
);
 
//
// Instantiation of Power Management
//
pm pm(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .pic_wakeup(pic_wakeup),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pm),
 
        // Power Management Interface
        .pm_clksd(pm_clksd),
        .pm_cpustall(pm_cpustall),
        .pm_dc_gate(pm_dc_gate),
        .pm_ic_gate(pm_ic_gate),
        .pm_dmmu_gate(pm_dmmu_gate),
        .pm_immu_gate(pm_immu_gate),
        .pm_tt_gate(pm_tt_gate),
        .pm_cpu_gate(pm_cpu_gate),
        .pm_wakeup(pm_wakeup),
        .pm_lvolt(pm_lvolt)
);
 
 
endmodule
 
 
 
 
 
 
 

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [or1200.v] - Blame information for rev 166

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200 Top Level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OR1200 Top Level ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	166	lampret	`// Revision 1.1 2001/07/20 00:46:21 lampret`
48			`// Development version of RTL. Libraries are missing.`
49	161	lampret	`//`
50	166	lampret	`//`
51	161	lampret
52			`include "general.h"
53
54			`module or1200(`
55			`clk, rst, pic_ints, clkdiv_by_2,`
56
57			`// Instruction WISHBONE INTERFACE`
58			`iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,`
59			`iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,`
60
61			`// Data WISHBONE INTERFACE`
62			`dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,`
63			`dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,`
64
65			`// Trace`
66			`tp_dir_in, tp_sel, tp_in, tp_out,`
67
68			`// Power Management`
69			`pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,`
70			`pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt`
71
72			`);`
73
74			parameter dw = `OPERAND_WIDTH;
75			parameter aw = `OPERAND_WIDTH;
76			parameter ppic_ints = `PIC_INTS;
77
78			`//`
79			`// Instruction WISHBONE interface`
80			`//`
81			`input iwb_clk_i; // clock input`
82			`input iwb_rst_i; // reset input`
83			`input iwb_ack_i; // normal termination`
84			`input iwb_err_i; // termination w/ error`
85			`input iwb_rty_i; // termination w/ retry`
86			`input [dw-1:0] iwb_dat_i; // input data bus`
87			`output iwb_cyc_o; // cycle valid output`
88			`output [aw-1:0] iwb_adr_o; // address bus outputs`
89			`output iwb_stb_o; // strobe output`
90			`output iwb_we_o; // indicates write transfer`
91			`output [3:0] iwb_sel_o; // byte select outputs`
92			`output [dw-1:0] iwb_dat_o; // output data bus`
93
94			`//`
95			`// Data WISHBONE interface`
96			`//`
97			`input dwb_clk_i; // clock input`
98			`input dwb_rst_i; // reset input`
99			`input dwb_ack_i; // normal termination`
100			`input dwb_err_i; // termination w/ error`
101			`input dwb_rty_i; // termination w/ retry`
102			`input [dw-1:0] dwb_dat_i; // input data bus`
103			`output dwb_cyc_o; // cycle valid output`
104			`output [aw-1:0] dwb_adr_o; // address bus outputs`
105			`output dwb_stb_o; // strobe output`
106			`output dwb_we_o; // indicates write transfer`
107			`output [3:0] dwb_sel_o; // byte select outputs`
108			`output [dw-1:0] dwb_dat_o; // output data bus`
109
110			`//`
111			`// System`
112			`//`
113			`input clk;`
114			`input rst;`
115			`input clkdiv_by_2;`
116			`input [ppic_ints-1:0] pic_ints;`
117
118			`// CPU and PM`
119			`input pm_cpustall;`
120			`output pm_clksd;`
121			`output pm_dc_gate;`
122			`output pm_ic_gate;`
123			`output pm_dmmu_gate;`
124			`output pm_immu_gate;`
125			`output pm_tt_gate;`
126			`output pm_cpu_gate;`
127			`output pm_wakeup;`
128			`output pm_lvolt;`
129
130			`// DC to BIU`
131			`wire dcbiu_rdy;`
132			`wire [dw-1:0] dcbiu_from_biu;`
133			`wire [dw-1:0] dcbiu_to_biu;`
134			`wire [aw-1:0] dcbiu_addr;`
135			`wire dcbiu_read;`
136			`wire dcbiu_write;`
137	166	lampret	`wire [3:0] dcbiu_sel;`
138	161	lampret
139			`// IC to BIU`
140			`wire icbiu_rdy;`
141			`wire [dw-1:0] icbiu_from_biu;`
142			`wire [aw-1:0] icbiu_addr;`
143			`wire icbiu_read;`
144
145			`// CPU's SPR access to various RISC units (shared wires)`
146			`wire [aw-1:0] spr_addr;`
147			`wire [dw-1:0] spr_dat_cpu;`
148			`wire [31:0] spr_cs;`
149			`wire spr_we;`
150
151			`// DC and CPU's LSU`
152			`wire dclsu_stall;`
153			`wire [aw-1:0] dclsu_addr;`
154			`wire [aw-1:0] dclsu_from_dc;`
155			`wire [aw-1:0] dclsu_to_dc;`
156			wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
157
158			`// IC and CPU's ifetch`
159			`wire icfetch_stall;`
160			`wire [aw-1:0] icfetch_addr;`
161			`wire [dw-1:0] icfetch_dataout;`
162
163			`// Connection between CPU and PIC`
164			`wire [dw-1:0] spr_dat_pic;`
165			`wire pic_wakeup;`
166			`wire int_low;`
167			`wire int_high;`
168			`wire int_high_tt;`
169
170			`// Connection between CPU and PM`
171			`wire [dw-1:0] spr_dat_pm;`
172
173			`// CPU and TT`
174			`wire [dw-1:0] spr_dat_tt;`
175			`wire tt_int;`
176
177			`// CPU and external Trace port`
178			`input tp_dir_in;`
179			`input [1:0] tp_sel;`
180			`input [dw-1:0] tp_in;`
181			`output [dw-1:0] tp_out;`
182
183			`// Trace port and caches/MMUs`
184			wire [`TP2W_WIDTH-1:0] tp2w;
185			wire [`TP3W_WIDTH-1:0] tp3w;
186			wire [`TP4W_WIDTH-1:0] tp4w;
187			`wire [dw-1:0] tpdw;`
188
189			`//`
190			`// Assignments`
191			`//`
192			`assign int_high_tt = int_high \| tt_int;`
193
194			`//`
195			`// Instantiation of Instruction WISHBONE BIU`
196			`//`
197			`wb_biu iwb_biu(`
198			`// WISHBONE interface`
199			`.wb_clk_i(iwb_clk_i),`
200			`.wb_rst_i(iwb_rst_i),`
201			`.wb_ack_i(iwb_ack_i),`
202			`.wb_err_i(iwb_err_i),`
203			`.wb_rty_i(iwb_rty_i),`
204			`.wb_dat_i(iwb_dat_i),`
205			`.wb_cyc_o(iwb_cyc_o),`
206			`.wb_adr_o(iwb_adr_o),`
207			`.wb_stb_o(iwb_stb_o),`
208			`.wb_we_o(iwb_we_o),`
209			`.wb_sel_o(iwb_sel_o),`
210			`.wb_dat_o(iwb_dat_o),`
211
212			`// Internal RISC bus`
213			`.biu_to_biu(32'b0),`
214			`.biu_addr(icbiu_addr),`
215			`.biu_read(icbiu_read),`
216			`.biu_write(1'b0),`
217			`.biu_rdy(icbiu_rdy),`
218	166	lampret	`.biu_from_biu(icbiu_from_biu),`
219			`.biu_sel(4'b1111)`
220	161	lampret	`);`
221
222			`//`
223			`// Instantiation of Data WISHBONE BIU`
224			`//`
225			`wb_biu dwb_biu(`
226			`// WISHBONE interface`
227			`.wb_clk_i(dwb_clk_i),`
228			`.wb_rst_i(dwb_rst_i),`
229			`.wb_ack_i(dwb_ack_i),`
230			`.wb_err_i(dwb_err_i),`
231			`.wb_rty_i(dwb_rty_i),`
232			`.wb_dat_i(dwb_dat_i),`
233			`.wb_cyc_o(dwb_cyc_o),`
234			`.wb_adr_o(dwb_adr_o),`
235			`.wb_stb_o(dwb_stb_o),`
236			`.wb_we_o(dwb_we_o),`
237			`.wb_sel_o(dwb_sel_o),`
238			`.wb_dat_o(dwb_dat_o),`
239
240			`// Internal RISC bus`
241			`.biu_to_biu(dcbiu_to_biu),`
242			`.biu_addr(dcbiu_addr),`
243			`.biu_read(dcbiu_read),`
244			`.biu_write(dcbiu_write),`
245			`.biu_rdy(dcbiu_rdy),`
246	166	lampret	`.biu_from_biu(dcbiu_from_biu),`
247			`.biu_sel(dcbiu_sel)`
248	161	lampret	`);`
249
250			`//`
251			`// Instantiation of Instruction Cache`
252			`//`
253			`ic ic(`
254			`.clk(clk),`
255			`.rst(rst),`
256			`.clkdiv_by_2(clkdiv_by_2),`
257
258			`// These connect IC to CPU's ifetch`
259			`.icfetch_addr(icfetch_addr),`
260			.icfetch_op(`FETCHOP_LW),
261			`.icfetch_dataout(icfetch_dataout),`
262			`.icfetch_stall(icfetch_stall),`
263
264			`// These connect IC to BIU`
265			`.icbiu_rdy(icbiu_rdy),`
266			`.icbiu_datain(icbiu_from_biu),`
267			`.icbiu_addr(icbiu_addr),`
268			`.icbiu_read(icbiu_read),`
269
270			`// These connect IC to SPRS`
271			`.spr_dat_i(spr_dat_cpu),`
272
273			`// Trace port`
274			`.tp4w(tp4w),`
275			`.tpdw(tpdw)`
276			`);`
277
278			`//`
279			`// Instantiation of Instruction Cache`
280			`//`
281			`cpu cpu(`
282			`.clk(clk),`
283			`.rst(rst),`
284
285			`// These connect IC and IFETCHER inside CPU`
286			`.ic_insn(icfetch_dataout),`
287			`.ic_pcaddr(icfetch_addr),`
288			`.ic_stall(icfetch_stall),`
289
290			`// These connect CPU to external Trace port`
291			`.tp_dir_in(tp_dir_in),`
292			`.tp_sel(tp_sel),`
293			`.tp_in(tp_in),`
294			`.tp_out(tp_out),`
295
296			`// These connect DC and CPU's LSU`
297			`.dclsu_stall(dclsu_stall),`
298			`.dclsu_addr(dclsu_addr),`
299			`.dclsu_datain(dclsu_from_dc),`
300			`.dclsu_dataout(dclsu_to_dc),`
301			`.dclsu_lsuop(dclsu_lsuop),`
302
303			`// These connect PIC and CPU's EXCEPT`
304			`.int_high(int_high_tt),`
305			`.int_low(int_low),`
306
307			`// SPRs`
308			`.spr_addr(spr_addr),`
309			`.spr_dataout(spr_dat_cpu),`
310			`.spr_dat_pic(spr_dat_pic),`
311			`.spr_dat_tt(spr_dat_tt),`
312			`.spr_dat_pm(spr_dat_pm),`
313			`.spr_cs(spr_cs),`
314			`.spr_we(spr_we),`
315
316			`// These connect trace port to caches and MMUs`
317			`.tp2w(tp2w),`
318			`.tp3w(tp3w),`
319			`.tp4w(tp4w),`
320			`.tpdw(tpdw)`
321			`);`
322
323			`//`
324			`// Instantiation of Data Cache`
325			`//`
326			`dc dc(`
327			`.clk(clk),`
328			`.rst(rst),`
329			`.clkdiv_by_2(clkdiv_by_2),`
330
331			`// These connect DC to CPU's LSU`
332			`.dclsu_addr(dclsu_addr),`
333			`.dclsu_lsuop(dclsu_lsuop),`
334			`.dclsu_datain(dclsu_to_dc),`
335			`.dclsu_dataout(dclsu_from_dc),`
336			`.dclsu_stall(dclsu_stall),`
337
338			`// These connect DC to BIU`
339			`.dcbiu_rdy(dcbiu_rdy),`
340			`.dcbiu_datain(dcbiu_from_biu),`
341			`.dcbiu_dataout(dcbiu_to_biu),`
342			`.dcbiu_addr(dcbiu_addr),`
343			`.dcbiu_read(dcbiu_read),`
344			`.dcbiu_write(dcbiu_write),`
345	166	lampret	`.dcbiu_sel(dcbiu_sel),`
346	161	lampret
347			`// Trace port`
348			`.tp2w(tp2w),`
349			`.tp3w(tp3w),`
350			`.tpdw(tpdw)`
351			`);`
352
353			`//`
354			`// Programmable interrupt controller`
355			`//`
356			`pic pic(`
357			`// RISC Internal Interface`
358			`.clk(clk),`
359			`.rst(rst),`
360			.spr_cs(spr_cs[`SPR_GROUP_PIC]),
361			`.spr_write(spr_we),`
362			`.spr_addr(spr_addr),`
363			`.spr_dat_i(spr_dat_cpu),`
364			`.spr_dat_o(spr_dat_pic),`
365			`.pic_wakeup(pic_wakeup),`
366			`.int_low(int_low),`
367			`.int_high(int_high),`
368
369			`// PIC Interface`
370			`.pic_int(pic_ints)`
371			`);`
372
373			`//`
374			`// Instantiation of Tick timer`
375			`//`
376			`tt tt(`
377			`// RISC Internal Interface`
378			`.clk(clk),`
379			`.rst(rst),`
380			.spr_cs(spr_cs[`SPR_GROUP_TT]),
381			`.spr_write(spr_we),`
382			`.spr_addr(spr_addr),`
383			`.spr_dat_i(spr_dat_cpu),`
384			`.spr_dat_o(spr_dat_tt),`
385			`.int(tt_int)`
386			`);`
387
388			`//`
389			`// Instantiation of Power Management`
390			`//`
391			`pm pm(`
392			`// RISC Internal Interface`
393			`.clk(clk),`
394			`.rst(rst),`
395			`.pic_wakeup(pic_wakeup),`
396			`.spr_write(spr_we),`
397			`.spr_addr(spr_addr),`
398			`.spr_dat_i(spr_dat_cpu),`
399			`.spr_dat_o(spr_dat_pm),`
400
401			`// Power Management Interface`
402			`.pm_clksd(pm_clksd),`
403			`.pm_cpustall(pm_cpustall),`
404			`.pm_dc_gate(pm_dc_gate),`
405			`.pm_ic_gate(pm_ic_gate),`
406			`.pm_dmmu_gate(pm_dmmu_gate),`
407			`.pm_immu_gate(pm_immu_gate),`
408			`.pm_tt_gate(pm_tt_gate),`
409			`.pm_cpu_gate(pm_cpu_gate),`
410			`.pm_wakeup(pm_wakeup),`
411			`.pm_lvolt(pm_lvolt)`
412			`);`
413
414
415			`endmodule`
416
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