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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module or1200(
        // System
        clk, rst, pic_ints, clkdiv_by_2,
 
        // Instruction WISHBONE INTERFACE
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
 
        // Data WISHBONE INTERFACE
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
 
        // Trace
        tp_dir_in, tp_sel, tp_in, tp_out,
 
        // Power Management
        pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
        pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
 
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
parameter ppic_ints = `PIC_INTS;
 
//
// I/O
//
 
//
// System
//
input                   clk;
input                   rst;
input                   clkdiv_by_2;
input   [ppic_ints-1:0]  pic_ints;
 
//
// Instruction WISHBONE interface
//
input                   iwb_clk_i;      // clock input
input                   iwb_rst_i;      // reset input
input                   iwb_ack_i;      // normal termination
input                   iwb_err_i;      // termination w/ error
input                   iwb_rty_i;      // termination w/ retry
input   [dw-1:0] iwb_dat_i;      // input data bus
output                  iwb_cyc_o;      // cycle valid output
output  [aw-1:0] iwb_adr_o;      // address bus outputs
output                  iwb_stb_o;      // strobe output
output                  iwb_we_o;       // indicates write transfer
output  [3:0]            iwb_sel_o;      // byte select outputs
output  [dw-1:0] iwb_dat_o;      // output data bus
 
//
// Data WISHBONE interface
//
input                   dwb_clk_i;      // clock input
input                   dwb_rst_i;      // reset input
input                   dwb_ack_i;      // normal termination
input                   dwb_err_i;      // termination w/ error
input                   dwb_rty_i;      // termination w/ retry
input   [dw-1:0] dwb_dat_i;      // input data bus
output                  dwb_cyc_o;      // cycle valid output
output  [aw-1:0] dwb_adr_o;      // address bus outputs
output                  dwb_stb_o;      // strobe output
output                  dwb_we_o;       // indicates write transfer
output  [3:0]            dwb_sel_o;      // byte select outputs
output  [dw-1:0] dwb_dat_o;      // output data bus
 
//
// Power Management
//
input                   pm_cpustall;
output                  pm_clksd;
output                  pm_dc_gate;
output                  pm_ic_gate;
output                  pm_dmmu_gate;
output                  pm_immu_gate;
output                  pm_tt_gate;
output                  pm_cpu_gate;
output                  pm_wakeup;
output                  pm_lvolt;
 
//
// Internal wires and regs
//
 
//
// DC to BIU
//
wire                    dcbiu_rdy;
wire [dw-1:0]            dcbiu_from_biu;
wire [dw-1:0]            dcbiu_to_biu;
wire [aw-1:0]            dcbiu_addr;
wire                    dcbiu_read;
wire                    dcbiu_write;
wire [3:0]               dcbiu_sel;
 
//
// IC to BIU
//
wire                    icbiu_rdy;
wire [dw-1:0]            icbiu_from_biu;
wire [aw-1:0]            icbiu_addr;
wire                    icbiu_read;
 
//
// CPU's SPR access to various RISC units (shared wires)
//
wire [aw-1:0]            spr_addr;
wire [dw-1:0]            spr_dat_cpu;
wire [31:0]              spr_cs;
wire                    spr_we;
 
//
// DC and CPU's LSU
//
wire                    dclsu_stall;
wire [aw-1:0]            dclsu_addr;
wire [aw-1:0]            dclsu_from_dc;
wire [aw-1:0]            dclsu_to_dc;
wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
wire                    dc_en;
 
//
// IC and CPU's ifetch
//
wire                    icfetch_stall;
wire [aw-1:0]            icfetch_addr;
wire [dw-1:0]            icfetch_dataout;
 
//
// Connection between CPU and PIC
//
wire [dw-1:0]            spr_dat_pic;
wire                    pic_wakeup;
wire                    int_low;
wire                    int_high;
wire                    int_high_tt;
 
//
// Connection between CPU and PM
//
wire [dw-1:0]            spr_dat_pm;
 
//
// CPU and TT
//
wire [dw-1:0]            spr_dat_tt;
wire                    tt_int;
 
//
// CPU and external Trace port
//
input                   tp_dir_in;
input [1:0]              tp_sel;
input [dw-1:0]           tp_in;
output [dw-1:0]          tp_out;
 
//
// Trace port and caches/MMUs
//
wire [`TP2W_WIDTH-1:0]   tp2w;
wire [`TP3W_WIDTH-1:0]   tp3w;
 
//
// Assignments
//
assign int_high_tt = int_high | tt_int;
 
//
// Instantiation of Instruction WISHBONE BIU
//
wb_biu iwb_biu(
        // WISHBONE interface
        .wb_clk_i(iwb_clk_i),
        .wb_rst_i(iwb_rst_i),
        .wb_ack_i(iwb_ack_i),
        .wb_err_i(iwb_err_i),
        .wb_rty_i(iwb_rty_i),
        .wb_dat_i(iwb_dat_i),
        .wb_cyc_o(iwb_cyc_o),
        .wb_adr_o(iwb_adr_o),
        .wb_stb_o(iwb_stb_o),
        .wb_we_o(iwb_we_o),
        .wb_sel_o(iwb_sel_o),
        .wb_dat_o(iwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(32'b0),
        .biu_addr(icbiu_addr),
        .biu_read(icbiu_read),
        .biu_write(1'b0),
        .biu_rdy(icbiu_rdy),
        .biu_from_biu(icbiu_from_biu),
        .biu_sel(4'b1111)
);
 
//
// Instantiation of Data WISHBONE BIU
//
wb_biu dwb_biu(
        // WISHBONE interface
        .wb_clk_i(dwb_clk_i),
        .wb_rst_i(dwb_rst_i),
        .wb_ack_i(dwb_ack_i),
        .wb_err_i(dwb_err_i),
        .wb_rty_i(dwb_rty_i),
        .wb_dat_i(dwb_dat_i),
        .wb_cyc_o(dwb_cyc_o),
        .wb_adr_o(dwb_adr_o),
        .wb_stb_o(dwb_stb_o),
        .wb_we_o(dwb_we_o),
        .wb_sel_o(dwb_sel_o),
        .wb_dat_o(dwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(dcbiu_to_biu),
        .biu_addr(dcbiu_addr),
        .biu_read(dcbiu_read),
        .biu_write(dcbiu_write),
        .biu_rdy(dcbiu_rdy),
        .biu_from_biu(dcbiu_from_biu),
        .biu_sel(dcbiu_sel)
);
 
//
// Instantiation of Instruction Cache
//
ic ic(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect IC to CPU's ifetch
        .icfetch_addr(icfetch_addr),
        .icfetch_op(`FETCHOP_LW),
        .icfetch_dataout(icfetch_dataout),
        .icfetch_stall(icfetch_stall),
 
        // These connect IC to BIU
        .icbiu_rdy(icbiu_rdy),
        .icbiu_datain(icbiu_from_biu),
        .icbiu_addr(icbiu_addr),
        .icbiu_read(icbiu_read),
 
        // These connect IC to SPRS
        .spr_dat_i(spr_dat_cpu)
);
 
//
// Instantiation of Instruction Cache
//
cpu cpu(
        .clk(clk),
        .rst(rst),
 
        // These connect IC and IFETCHER inside CPU
        .ic_insn(icfetch_dataout),
        .ic_pcaddr(icfetch_addr),
        .ic_stall(icfetch_stall),
 
        // These connect CPU to external Trace port
        .tp_dir_in(tp_dir_in),
        .tp_sel(tp_sel),
        .tp_in(tp_in),
        .tp_out(tp_out),
 
        // These connect DC and CPU's LSU
        .dclsu_stall(dclsu_stall),
        .dclsu_addr(dclsu_addr),
        .dclsu_datain(dclsu_from_dc),
        .dclsu_dataout(dclsu_to_dc),
        .dclsu_lsuop(dclsu_lsuop),
        .dc_en(dc_en),
 
        // These connect PIC and CPU's EXCEPT
        .int_high(int_high_tt),
        .int_low(int_low),
 
        // SPRs
        .spr_addr(spr_addr),
        .spr_dataout(spr_dat_cpu),
        .spr_dat_pic(spr_dat_pic),
        .spr_dat_tt(spr_dat_tt),
        .spr_dat_pm(spr_dat_pm),
        .spr_cs(spr_cs),
        .spr_we(spr_we),
 
        // These connect trace port to caches and MMUs
        .tp2w(tp2w),
        .tp3w(tp3w)
);
 
//
// Instantiation of Data Cache
//
dc dc(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect DC to CPU's LSU
        .dclsu_addr(dclsu_addr),
        .dclsu_lsuop(dclsu_lsuop),
        .dclsu_datain(dclsu_to_dc),
        .dclsu_dataout(dclsu_from_dc),
        .dclsu_stall(dclsu_stall),
        .dc_en(dc_en),
 
        // These connect DC to BIU
        .dcbiu_rdy(dcbiu_rdy),
        .dcbiu_datain(dcbiu_from_biu),
        .dcbiu_dataout(dcbiu_to_biu),
        .dcbiu_addr(dcbiu_addr),
        .dcbiu_read(dcbiu_read),
        .dcbiu_write(dcbiu_write),
        .dcbiu_sel(dcbiu_sel),
 
        // Trace port
        .tp2w(tp2w)
);
 
//
// Programmable interrupt controller
//
pic pic(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_PIC]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pic),
        .pic_wakeup(pic_wakeup),
        .int_low(int_low),
        .int_high(int_high),
 
        // PIC Interface
        .pic_int(pic_ints)
);
 
//
// Instantiation of Tick timer
//
tt tt(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_TT]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_tt),
        .int(tt_int)
);
 
//
// Instantiation of Power Management
//
pm pm(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .pic_wakeup(pic_wakeup),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pm),
 
        // Power Management Interface
        .pm_clksd(pm_clksd),
        .pm_cpustall(pm_cpustall),
        .pm_dc_gate(pm_dc_gate),
        .pm_ic_gate(pm_ic_gate),
        .pm_dmmu_gate(pm_dmmu_gate),
        .pm_immu_gate(pm_immu_gate),
        .pm_tt_gate(pm_tt_gate),
        .pm_cpu_gate(pm_cpu_gate),
        .pm_wakeup(pm_wakeup),
        .pm_lvolt(pm_lvolt)
);
 
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200 Top Level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OR1200 Top Level ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	168	lampret	`// Revision 1.2 2001/07/22 03:31:54 lampret`
48			`// Fixed RAM's oen bug. Cache bypass under development.`
49			`//`
50	166	lampret	`// Revision 1.1 2001/07/20 00:46:21 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	166	lampret	`//`
54	161	lampret
55	168	lampret	`include "timescale.v"
56			`include "defines.v"
57	161	lampret
58			`module or1200(`
59	168	lampret	`// System`
60	161	lampret	`clk, rst, pic_ints, clkdiv_by_2,`
61
62			`// Instruction WISHBONE INTERFACE`
63			`iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,`
64			`iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,`
65
66			`// Data WISHBONE INTERFACE`
67			`dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,`
68			`dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,`
69
70			`// Trace`
71			`tp_dir_in, tp_sel, tp_in, tp_out,`
72
73			`// Power Management`
74			`pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,`
75			`pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt`
76
77			`);`
78
79			parameter dw = `OPERAND_WIDTH;
80			parameter aw = `OPERAND_WIDTH;
81			parameter ppic_ints = `PIC_INTS;
82
83			`//`
84	168	lampret	`// I/O`
85			`//`
86
87			`//`
88			`// System`
89			`//`
90			`input clk;`
91			`input rst;`
92			`input clkdiv_by_2;`
93			`input [ppic_ints-1:0] pic_ints;`
94
95			`//`
96	161	lampret	`// Instruction WISHBONE interface`
97			`//`
98			`input iwb_clk_i; // clock input`
99			`input iwb_rst_i; // reset input`
100			`input iwb_ack_i; // normal termination`
101			`input iwb_err_i; // termination w/ error`
102			`input iwb_rty_i; // termination w/ retry`
103	168	lampret	`input [dw-1:0] iwb_dat_i; // input data bus`
104	161	lampret	`output iwb_cyc_o; // cycle valid output`
105	168	lampret	`output [aw-1:0] iwb_adr_o; // address bus outputs`
106	161	lampret	`output iwb_stb_o; // strobe output`
107			`output iwb_we_o; // indicates write transfer`
108	168	lampret	`output [3:0] iwb_sel_o; // byte select outputs`
109			`output [dw-1:0] iwb_dat_o; // output data bus`
110	161	lampret
111			`//`
112			`// Data WISHBONE interface`
113			`//`
114			`input dwb_clk_i; // clock input`
115			`input dwb_rst_i; // reset input`
116			`input dwb_ack_i; // normal termination`
117			`input dwb_err_i; // termination w/ error`
118			`input dwb_rty_i; // termination w/ retry`
119	168	lampret	`input [dw-1:0] dwb_dat_i; // input data bus`
120	161	lampret	`output dwb_cyc_o; // cycle valid output`
121	168	lampret	`output [aw-1:0] dwb_adr_o; // address bus outputs`
122	161	lampret	`output dwb_stb_o; // strobe output`
123			`output dwb_we_o; // indicates write transfer`
124	168	lampret	`output [3:0] dwb_sel_o; // byte select outputs`
125			`output [dw-1:0] dwb_dat_o; // output data bus`
126	161	lampret
127			`//`
128	168	lampret	`// Power Management`
129	161	lampret	`//`
130			`input pm_cpustall;`
131	168	lampret	`output pm_clksd;`
132			`output pm_dc_gate;`
133			`output pm_ic_gate;`
134			`output pm_dmmu_gate;`
135			`output pm_immu_gate;`
136			`output pm_tt_gate;`
137			`output pm_cpu_gate;`
138			`output pm_wakeup;`
139			`output pm_lvolt;`
140	161	lampret
141	168	lampret	`//`
142			`// Internal wires and regs`
143			`//`
144
145			`//`
146	161	lampret	`// DC to BIU`
147	168	lampret	`//`
148	161	lampret	`wire dcbiu_rdy;`
149			`wire [dw-1:0] dcbiu_from_biu;`
150			`wire [dw-1:0] dcbiu_to_biu;`
151			`wire [aw-1:0] dcbiu_addr;`
152			`wire dcbiu_read;`
153			`wire dcbiu_write;`
154	166	lampret	`wire [3:0] dcbiu_sel;`
155	161	lampret
156	168	lampret	`//`
157	161	lampret	`// IC to BIU`
158	168	lampret	`//`
159	161	lampret	`wire icbiu_rdy;`
160			`wire [dw-1:0] icbiu_from_biu;`
161			`wire [aw-1:0] icbiu_addr;`
162			`wire icbiu_read;`
163
164	168	lampret	`//`
165	161	lampret	`// CPU's SPR access to various RISC units (shared wires)`
166	168	lampret	`//`
167	161	lampret	`wire [aw-1:0] spr_addr;`
168			`wire [dw-1:0] spr_dat_cpu;`
169			`wire [31:0] spr_cs;`
170			`wire spr_we;`
171
172	168	lampret	`//`
173	161	lampret	`// DC and CPU's LSU`
174	168	lampret	`//`
175	161	lampret	`wire dclsu_stall;`
176			`wire [aw-1:0] dclsu_addr;`
177			`wire [aw-1:0] dclsu_from_dc;`
178			`wire [aw-1:0] dclsu_to_dc;`
179			wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
180	168	lampret	`wire dc_en;`
181	161	lampret
182	168	lampret	`//`
183	161	lampret	`// IC and CPU's ifetch`
184	168	lampret	`//`
185	161	lampret	`wire icfetch_stall;`
186			`wire [aw-1:0] icfetch_addr;`
187			`wire [dw-1:0] icfetch_dataout;`
188
189	168	lampret	`//`
190	161	lampret	`// Connection between CPU and PIC`
191	168	lampret	`//`
192	161	lampret	`wire [dw-1:0] spr_dat_pic;`
193			`wire pic_wakeup;`
194			`wire int_low;`
195			`wire int_high;`
196			`wire int_high_tt;`
197
198	168	lampret	`//`
199	161	lampret	`// Connection between CPU and PM`
200	168	lampret	`//`
201	161	lampret	`wire [dw-1:0] spr_dat_pm;`
202
203	168	lampret	`//`
204	161	lampret	`// CPU and TT`
205	168	lampret	`//`
206	161	lampret	`wire [dw-1:0] spr_dat_tt;`
207			`wire tt_int;`
208
209	168	lampret	`//`
210	161	lampret	`// CPU and external Trace port`
211	168	lampret	`//`
212	161	lampret	`input tp_dir_in;`
213			`input [1:0] tp_sel;`
214			`input [dw-1:0] tp_in;`
215			`output [dw-1:0] tp_out;`
216
217	168	lampret	`//`
218	161	lampret	`// Trace port and caches/MMUs`
219	168	lampret	`//`
220	161	lampret	wire [`TP2W_WIDTH-1:0] tp2w;
221			wire [`TP3W_WIDTH-1:0] tp3w;
222
223			`//`
224			`// Assignments`
225			`//`
226			`assign int_high_tt = int_high \| tt_int;`
227
228			`//`
229			`// Instantiation of Instruction WISHBONE BIU`
230			`//`
231			`wb_biu iwb_biu(`
232			`// WISHBONE interface`
233			`.wb_clk_i(iwb_clk_i),`
234			`.wb_rst_i(iwb_rst_i),`
235			`.wb_ack_i(iwb_ack_i),`
236			`.wb_err_i(iwb_err_i),`
237			`.wb_rty_i(iwb_rty_i),`
238			`.wb_dat_i(iwb_dat_i),`
239			`.wb_cyc_o(iwb_cyc_o),`
240			`.wb_adr_o(iwb_adr_o),`
241			`.wb_stb_o(iwb_stb_o),`
242			`.wb_we_o(iwb_we_o),`
243			`.wb_sel_o(iwb_sel_o),`
244			`.wb_dat_o(iwb_dat_o),`
245
246			`// Internal RISC bus`
247			`.biu_to_biu(32'b0),`
248			`.biu_addr(icbiu_addr),`
249			`.biu_read(icbiu_read),`
250			`.biu_write(1'b0),`
251			`.biu_rdy(icbiu_rdy),`
252	166	lampret	`.biu_from_biu(icbiu_from_biu),`
253			`.biu_sel(4'b1111)`
254	161	lampret	`);`
255
256			`//`
257			`// Instantiation of Data WISHBONE BIU`
258			`//`
259			`wb_biu dwb_biu(`
260			`// WISHBONE interface`
261			`.wb_clk_i(dwb_clk_i),`
262			`.wb_rst_i(dwb_rst_i),`
263			`.wb_ack_i(dwb_ack_i),`
264			`.wb_err_i(dwb_err_i),`
265			`.wb_rty_i(dwb_rty_i),`
266			`.wb_dat_i(dwb_dat_i),`
267			`.wb_cyc_o(dwb_cyc_o),`
268			`.wb_adr_o(dwb_adr_o),`
269			`.wb_stb_o(dwb_stb_o),`
270			`.wb_we_o(dwb_we_o),`
271			`.wb_sel_o(dwb_sel_o),`
272			`.wb_dat_o(dwb_dat_o),`
273
274			`// Internal RISC bus`
275			`.biu_to_biu(dcbiu_to_biu),`
276			`.biu_addr(dcbiu_addr),`
277			`.biu_read(dcbiu_read),`
278			`.biu_write(dcbiu_write),`
279			`.biu_rdy(dcbiu_rdy),`
280	166	lampret	`.biu_from_biu(dcbiu_from_biu),`
281			`.biu_sel(dcbiu_sel)`
282	161	lampret	`);`
283
284			`//`
285			`// Instantiation of Instruction Cache`
286			`//`
287			`ic ic(`
288			`.clk(clk),`
289			`.rst(rst),`
290			`.clkdiv_by_2(clkdiv_by_2),`
291
292			`// These connect IC to CPU's ifetch`
293			`.icfetch_addr(icfetch_addr),`
294			.icfetch_op(`FETCHOP_LW),
295			`.icfetch_dataout(icfetch_dataout),`
296			`.icfetch_stall(icfetch_stall),`
297
298			`// These connect IC to BIU`
299			`.icbiu_rdy(icbiu_rdy),`
300			`.icbiu_datain(icbiu_from_biu),`
301			`.icbiu_addr(icbiu_addr),`
302			`.icbiu_read(icbiu_read),`
303
304			`// These connect IC to SPRS`
305	168	lampret	`.spr_dat_i(spr_dat_cpu)`
306	161	lampret	`);`
307
308			`//`
309			`// Instantiation of Instruction Cache`
310			`//`
311			`cpu cpu(`
312			`.clk(clk),`
313			`.rst(rst),`
314
315			`// These connect IC and IFETCHER inside CPU`
316			`.ic_insn(icfetch_dataout),`
317			`.ic_pcaddr(icfetch_addr),`
318			`.ic_stall(icfetch_stall),`
319
320			`// These connect CPU to external Trace port`
321			`.tp_dir_in(tp_dir_in),`
322			`.tp_sel(tp_sel),`
323			`.tp_in(tp_in),`
324			`.tp_out(tp_out),`
325
326			`// These connect DC and CPU's LSU`
327			`.dclsu_stall(dclsu_stall),`
328			`.dclsu_addr(dclsu_addr),`
329			`.dclsu_datain(dclsu_from_dc),`
330			`.dclsu_dataout(dclsu_to_dc),`
331			`.dclsu_lsuop(dclsu_lsuop),`
332	168	lampret	`.dc_en(dc_en),`
333	161	lampret
334			`// These connect PIC and CPU's EXCEPT`
335			`.int_high(int_high_tt),`
336			`.int_low(int_low),`
337
338			`// SPRs`
339			`.spr_addr(spr_addr),`
340			`.spr_dataout(spr_dat_cpu),`
341			`.spr_dat_pic(spr_dat_pic),`
342			`.spr_dat_tt(spr_dat_tt),`
343			`.spr_dat_pm(spr_dat_pm),`
344			`.spr_cs(spr_cs),`
345			`.spr_we(spr_we),`
346
347			`// These connect trace port to caches and MMUs`
348			`.tp2w(tp2w),`
349	168	lampret	`.tp3w(tp3w)`
350	161	lampret	`);`
351
352			`//`
353			`// Instantiation of Data Cache`
354			`//`
355			`dc dc(`
356			`.clk(clk),`
357			`.rst(rst),`
358			`.clkdiv_by_2(clkdiv_by_2),`
359
360			`// These connect DC to CPU's LSU`
361			`.dclsu_addr(dclsu_addr),`
362			`.dclsu_lsuop(dclsu_lsuop),`
363			`.dclsu_datain(dclsu_to_dc),`
364			`.dclsu_dataout(dclsu_from_dc),`
365			`.dclsu_stall(dclsu_stall),`
366	168	lampret	`.dc_en(dc_en),`
367	161	lampret
368			`// These connect DC to BIU`
369			`.dcbiu_rdy(dcbiu_rdy),`
370			`.dcbiu_datain(dcbiu_from_biu),`
371			`.dcbiu_dataout(dcbiu_to_biu),`
372			`.dcbiu_addr(dcbiu_addr),`
373			`.dcbiu_read(dcbiu_read),`
374			`.dcbiu_write(dcbiu_write),`
375	166	lampret	`.dcbiu_sel(dcbiu_sel),`
376	161	lampret
377			`// Trace port`
378	168	lampret	`.tp2w(tp2w)`
379	161	lampret	`);`
380
381			`//`
382			`// Programmable interrupt controller`
383			`//`
384			`pic pic(`
385			`// RISC Internal Interface`
386			`.clk(clk),`
387			`.rst(rst),`
388			.spr_cs(spr_cs[`SPR_GROUP_PIC]),
389			`.spr_write(spr_we),`
390			`.spr_addr(spr_addr),`
391			`.spr_dat_i(spr_dat_cpu),`
392			`.spr_dat_o(spr_dat_pic),`
393			`.pic_wakeup(pic_wakeup),`
394			`.int_low(int_low),`
395			`.int_high(int_high),`
396
397			`// PIC Interface`
398			`.pic_int(pic_ints)`
399			`);`
400
401			`//`
402			`// Instantiation of Tick timer`
403			`//`
404			`tt tt(`
405			`// RISC Internal Interface`
406			`.clk(clk),`
407			`.rst(rst),`
408			.spr_cs(spr_cs[`SPR_GROUP_TT]),
409			`.spr_write(spr_we),`
410			`.spr_addr(spr_addr),`
411			`.spr_dat_i(spr_dat_cpu),`
412			`.spr_dat_o(spr_dat_tt),`
413			`.int(tt_int)`
414			`);`
415
416			`//`
417			`// Instantiation of Power Management`
418			`//`
419			`pm pm(`
420			`// RISC Internal Interface`
421			`.clk(clk),`
422			`.rst(rst),`
423			`.pic_wakeup(pic_wakeup),`
424			`.spr_write(spr_we),`
425			`.spr_addr(spr_addr),`
426			`.spr_dat_i(spr_dat_cpu),`
427			`.spr_dat_o(spr_dat_pm),`
428
429			`// Power Management Interface`
430			`.pm_clksd(pm_clksd),`
431			`.pm_cpustall(pm_cpustall),`
432			`.pm_dc_gate(pm_dc_gate),`
433			`.pm_ic_gate(pm_ic_gate),`
434			`.pm_dmmu_gate(pm_dmmu_gate),`
435			`.pm_immu_gate(pm_immu_gate),`
436			`.pm_tt_gate(pm_tt_gate),`
437			`.pm_cpu_gate(pm_cpu_gate),`
438			`.pm_wakeup(pm_wakeup),`
439			`.pm_lvolt(pm_lvolt)`
440			`);`
441
442
443			`endmodule`

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