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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module or1200(
        // System
        clk, rst, pic_ints, clkdiv_by_2,
 
        // Instruction WISHBONE INTERFACE
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
 
        // Data WISHBONE INTERFACE
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
 
        // Trace
        tp_dir_in, tp_sel, tp_in, tp_out,
 
        // Power Management
        pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
        pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
 
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
parameter ppic_ints = `PIC_INTS;
 
//
// I/O
//
 
//
// System
//
input                   clk;
input                   rst;
input                   clkdiv_by_2;
input   [ppic_ints-1:0]  pic_ints;
 
//
// Instruction WISHBONE interface
//
input                   iwb_clk_i;      // clock input
input                   iwb_rst_i;      // reset input
input                   iwb_ack_i;      // normal termination
input                   iwb_err_i;      // termination w/ error
input                   iwb_rty_i;      // termination w/ retry
input   [dw-1:0] iwb_dat_i;      // input data bus
output                  iwb_cyc_o;      // cycle valid output
output  [aw-1:0] iwb_adr_o;      // address bus outputs
output                  iwb_stb_o;      // strobe output
output                  iwb_we_o;       // indicates write transfer
output  [3:0]            iwb_sel_o;      // byte select outputs
output  [dw-1:0] iwb_dat_o;      // output data bus
 
//
// Data WISHBONE interface
//
input                   dwb_clk_i;      // clock input
input                   dwb_rst_i;      // reset input
input                   dwb_ack_i;      // normal termination
input                   dwb_err_i;      // termination w/ error
input                   dwb_rty_i;      // termination w/ retry
input   [dw-1:0] dwb_dat_i;      // input data bus
output                  dwb_cyc_o;      // cycle valid output
output  [aw-1:0] dwb_adr_o;      // address bus outputs
output                  dwb_stb_o;      // strobe output
output                  dwb_we_o;       // indicates write transfer
output  [3:0]            dwb_sel_o;      // byte select outputs
output  [dw-1:0] dwb_dat_o;      // output data bus
 
//
// Power Management
//
input                   pm_cpustall;
output                  pm_clksd;
output                  pm_dc_gate;
output                  pm_ic_gate;
output                  pm_dmmu_gate;
output                  pm_immu_gate;
output                  pm_tt_gate;
output                  pm_cpu_gate;
output                  pm_wakeup;
output                  pm_lvolt;
 
//
// Internal wires and regs
//
 
//
// DC to BIU
//
wire                    dcbiu_rdy;
wire    [dw-1:0]         dcbiu_from_biu;
wire    [dw-1:0]         dcbiu_to_biu;
wire    [aw-1:0]         dcbiu_addr;
wire                    dcbiu_read;
wire                    dcbiu_write;
wire    [3:0]            dcbiu_sel;
 
//
// IC to BIU
//
wire                    icbiu_rdy;
wire    [dw-1:0] icbiu_from_biu;
wire    [aw-1:0] icbiu_addr;
wire                    icbiu_read;
wire    [3:0]            icbiu_sel;
 
//
// CPU's SPR access to various RISC units (shared wires)
//
wire    [aw-1:0] spr_addr;
wire    [dw-1:0] spr_dat_cpu;
wire    [31:0]           spr_cs;
wire                    spr_we;
 
//
// DC and CPU's LSU
//
wire                    dclsu_stall;
wire    [aw-1:0] dclsu_addr;
wire    [aw-1:0] dclsu_from_dc;
wire    [aw-1:0] dclsu_to_dc;
wire    [`LSUOP_WIDTH-1:0] dclsu_lsuop;
wire                    dc_en;
 
//
// IC and CPU's ifetch
//
wire                    icfetch_stall;
wire    [aw-1:0] icfetch_addr;
wire    [dw-1:0] icfetch_dataout;
wire                    ic_en;
 
//
// Connection between CPU and PIC
//
wire    [dw-1:0] spr_dat_pic;
wire                    pic_wakeup;
wire                    int_low;
wire                    int_high;
wire                    int_high_tt;
 
//
// Connection between CPU and PM
//
wire    [dw-1:0] spr_dat_pm;
 
//
// CPU and TT
//
wire    [dw-1:0] spr_dat_tt;
wire                    tt_int;
 
//
// CPU and external Trace port
//
input                   tp_dir_in;
input   [1:0]            tp_sel;
input   [dw-1:0]         tp_in;
output  [dw-1:0] tp_out;
 
//
// Trace port and caches/MMUs
//
wire    [`TP2W_WIDTH-1:0] tp2w;
wire    [`TP3W_WIDTH-1:0] tp3w;
 
//
// Assignments
//
assign int_high_tt = int_high | tt_int;
 
//
// Instantiation of Instruction WISHBONE BIU
//
wb_biu iwb_biu(
        // WISHBONE interface
        .wb_clk_i(iwb_clk_i),
        .wb_rst_i(iwb_rst_i),
        .wb_ack_i(iwb_ack_i),
        .wb_err_i(iwb_err_i),
        .wb_rty_i(iwb_rty_i),
        .wb_dat_i(iwb_dat_i),
        .wb_cyc_o(iwb_cyc_o),
        .wb_adr_o(iwb_adr_o),
        .wb_stb_o(iwb_stb_o),
        .wb_we_o(iwb_we_o),
        .wb_sel_o(iwb_sel_o),
        .wb_dat_o(iwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(32'b0),
        .biu_addr(icbiu_addr),
        .biu_read(icbiu_read),
        .biu_write(1'b0),
        .biu_rdy(icbiu_rdy),
        .biu_from_biu(icbiu_from_biu),
        .biu_sel(icbiu_sel)
);
 
//
// Instantiation of Data WISHBONE BIU
//
wb_biu dwb_biu(
        // WISHBONE interface
        .wb_clk_i(dwb_clk_i),
        .wb_rst_i(dwb_rst_i),
        .wb_ack_i(dwb_ack_i),
        .wb_err_i(dwb_err_i),
        .wb_rty_i(dwb_rty_i),
        .wb_dat_i(dwb_dat_i),
        .wb_cyc_o(dwb_cyc_o),
        .wb_adr_o(dwb_adr_o),
        .wb_stb_o(dwb_stb_o),
        .wb_we_o(dwb_we_o),
        .wb_sel_o(dwb_sel_o),
        .wb_dat_o(dwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(dcbiu_to_biu),
        .biu_addr(dcbiu_addr),
        .biu_read(dcbiu_read),
        .biu_write(dcbiu_write),
        .biu_rdy(dcbiu_rdy),
        .biu_from_biu(dcbiu_from_biu),
        .biu_sel(dcbiu_sel)
);
 
//
// Instantiation of Instruction Cache
//
ic ic(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect IC to CPU's ifetch
        .icfetch_addr(icfetch_addr),
        .icfetch_op(`FETCHOP_LW),
        .icfetch_dataout(icfetch_dataout),
        .icfetch_stall(icfetch_stall),
        .ic_en(ic_en),
 
        // These connect IC to BIU
        .icbiu_rdy(icbiu_rdy),
        .icbiu_datain(icbiu_from_biu),
        .icbiu_addr(icbiu_addr),
        .icbiu_read(icbiu_read),
        .icbiu_sel(icbiu_sel),
 
        // These connect IC to SPRS
        .spr_dat_i(spr_dat_cpu)
);
 
//
// Instantiation of Instruction Cache
//
cpu cpu(
        .clk(clk),
        .rst(rst),
 
        // These connect IC and IFETCHER inside CPU
        .ic_insn(icfetch_dataout),
        .ic_pcaddr(icfetch_addr),
        .ic_stall(icfetch_stall),
        .ic_en(ic_en),
 
        // These connect CPU to external Trace port
        .tp_dir_in(tp_dir_in),
        .tp_sel(tp_sel),
        .tp_in(tp_in),
        .tp_out(tp_out),
 
        // These connect DC and CPU's LSU
        .dclsu_stall(dclsu_stall),
        .dclsu_addr(dclsu_addr),
        .dclsu_datain(dclsu_from_dc),
        .dclsu_dataout(dclsu_to_dc),
        .dclsu_lsuop(dclsu_lsuop),
        .dc_en(dc_en),
 
        // These connect PIC and CPU's EXCEPT
        .int_high(int_high_tt),
        .int_low(int_low),
 
        // SPRs
        .spr_addr(spr_addr),
        .spr_dataout(spr_dat_cpu),
        .spr_dat_pic(spr_dat_pic),
        .spr_dat_tt(spr_dat_tt),
        .spr_dat_pm(spr_dat_pm),
        .spr_cs(spr_cs),
        .spr_we(spr_we),
 
        // These connect trace port to caches and MMUs
        .tp2w(tp2w),
        .tp3w(tp3w)
);
 
//
// Instantiation of Data Cache
//
dc dc(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect DC to CPU's LSU
        .dclsu_addr(dclsu_addr),
        .dclsu_lsuop(dclsu_lsuop),
        .dclsu_datain(dclsu_to_dc),
        .dclsu_dataout(dclsu_from_dc),
        .dclsu_stall(dclsu_stall),
        .dc_en(dc_en),
 
        // These connect DC to BIU
        .dcbiu_rdy(dcbiu_rdy),
        .dcbiu_datain(dcbiu_from_biu),
        .dcbiu_dataout(dcbiu_to_biu),
        .dcbiu_addr(dcbiu_addr),
        .dcbiu_read(dcbiu_read),
        .dcbiu_write(dcbiu_write),
        .dcbiu_sel(dcbiu_sel),
 
        // Trace port
        .tp2w(tp2w)
);
 
//
// Programmable interrupt controller
//
pic pic(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_PIC]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pic),
        .pic_wakeup(pic_wakeup),
        .int_low(int_low),
        .int_high(int_high),
 
        // PIC Interface
        .pic_int(pic_ints)
);
 
//
// Instantiation of Tick timer
//
tt tt(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_TT]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_tt),
        .int(tt_int)
);
 
//
// Instantiation of Power Management
//
pm pm(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .pic_wakeup(pic_wakeup),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pm),
 
        // Power Management Interface
        .pm_clksd(pm_clksd),
        .pm_cpustall(pm_cpustall),
        .pm_dc_gate(pm_dc_gate),
        .pm_ic_gate(pm_ic_gate),
        .pm_dmmu_gate(pm_dmmu_gate),
        .pm_immu_gate(pm_immu_gate),
        .pm_tt_gate(pm_tt_gate),
        .pm_cpu_gate(pm_cpu_gate),
        .pm_wakeup(pm_wakeup),
        .pm_lvolt(pm_lvolt)
);
 
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200 Top Level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OR1200 Top Level ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	170	lampret	`// Revision 1.3 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49			`//`
50	168	lampret	`// Revision 1.2 2001/07/22 03:31:54 lampret`
51			`// Fixed RAM's oen bug. Cache bypass under development.`
52			`//`
53	166	lampret	`// Revision 1.1 2001/07/20 00:46:21 lampret`
54			`// Development version of RTL. Libraries are missing.`
55	161	lampret	`//`
56	166	lampret	`//`
57	161	lampret
58	168	lampret	`include "timescale.v"
59			`include "defines.v"
60	161	lampret
61			`module or1200(`
62	168	lampret	`// System`
63	161	lampret	`clk, rst, pic_ints, clkdiv_by_2,`
64
65			`// Instruction WISHBONE INTERFACE`
66			`iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,`
67			`iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,`
68
69			`// Data WISHBONE INTERFACE`
70			`dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,`
71			`dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,`
72
73			`// Trace`
74			`tp_dir_in, tp_sel, tp_in, tp_out,`
75
76			`// Power Management`
77			`pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,`
78			`pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt`
79
80			`);`
81
82			parameter dw = `OPERAND_WIDTH;
83			parameter aw = `OPERAND_WIDTH;
84			parameter ppic_ints = `PIC_INTS;
85
86			`//`
87	168	lampret	`// I/O`
88			`//`
89
90			`//`
91			`// System`
92			`//`
93			`input clk;`
94			`input rst;`
95			`input clkdiv_by_2;`
96			`input [ppic_ints-1:0] pic_ints;`
97
98			`//`
99	161	lampret	`// Instruction WISHBONE interface`
100			`//`
101			`input iwb_clk_i; // clock input`
102			`input iwb_rst_i; // reset input`
103			`input iwb_ack_i; // normal termination`
104			`input iwb_err_i; // termination w/ error`
105			`input iwb_rty_i; // termination w/ retry`
106	168	lampret	`input [dw-1:0] iwb_dat_i; // input data bus`
107	161	lampret	`output iwb_cyc_o; // cycle valid output`
108	168	lampret	`output [aw-1:0] iwb_adr_o; // address bus outputs`
109	161	lampret	`output iwb_stb_o; // strobe output`
110			`output iwb_we_o; // indicates write transfer`
111	168	lampret	`output [3:0] iwb_sel_o; // byte select outputs`
112			`output [dw-1:0] iwb_dat_o; // output data bus`
113	161	lampret
114			`//`
115			`// Data WISHBONE interface`
116			`//`
117			`input dwb_clk_i; // clock input`
118			`input dwb_rst_i; // reset input`
119			`input dwb_ack_i; // normal termination`
120			`input dwb_err_i; // termination w/ error`
121			`input dwb_rty_i; // termination w/ retry`
122	168	lampret	`input [dw-1:0] dwb_dat_i; // input data bus`
123	161	lampret	`output dwb_cyc_o; // cycle valid output`
124	168	lampret	`output [aw-1:0] dwb_adr_o; // address bus outputs`
125	161	lampret	`output dwb_stb_o; // strobe output`
126			`output dwb_we_o; // indicates write transfer`
127	168	lampret	`output [3:0] dwb_sel_o; // byte select outputs`
128			`output [dw-1:0] dwb_dat_o; // output data bus`
129	161	lampret
130			`//`
131	168	lampret	`// Power Management`
132	161	lampret	`//`
133			`input pm_cpustall;`
134	168	lampret	`output pm_clksd;`
135			`output pm_dc_gate;`
136			`output pm_ic_gate;`
137			`output pm_dmmu_gate;`
138			`output pm_immu_gate;`
139			`output pm_tt_gate;`
140			`output pm_cpu_gate;`
141			`output pm_wakeup;`
142			`output pm_lvolt;`
143	161	lampret
144	168	lampret	`//`
145			`// Internal wires and regs`
146			`//`
147
148			`//`
149	161	lampret	`// DC to BIU`
150	168	lampret	`//`
151	170	lampret	`wire dcbiu_rdy;`
152			`wire [dw-1:0] dcbiu_from_biu;`
153			`wire [dw-1:0] dcbiu_to_biu;`
154			`wire [aw-1:0] dcbiu_addr;`
155			`wire dcbiu_read;`
156			`wire dcbiu_write;`
157			`wire [3:0] dcbiu_sel;`
158	161	lampret
159	168	lampret	`//`
160	161	lampret	`// IC to BIU`
161	168	lampret	`//`
162	170	lampret	`wire icbiu_rdy;`
163			`wire [dw-1:0] icbiu_from_biu;`
164			`wire [aw-1:0] icbiu_addr;`
165			`wire icbiu_read;`
166			`wire [3:0] icbiu_sel;`
167	161	lampret
168	168	lampret	`//`
169	161	lampret	`// CPU's SPR access to various RISC units (shared wires)`
170	168	lampret	`//`
171	170	lampret	`wire [aw-1:0] spr_addr;`
172			`wire [dw-1:0] spr_dat_cpu;`
173			`wire [31:0] spr_cs;`
174	161	lampret	`wire spr_we;`
175
176	168	lampret	`//`
177	161	lampret	`// DC and CPU's LSU`
178	168	lampret	`//`
179	170	lampret	`wire dclsu_stall;`
180			`wire [aw-1:0] dclsu_addr;`
181			`wire [aw-1:0] dclsu_from_dc;`
182			`wire [aw-1:0] dclsu_to_dc;`
183			wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
184	168	lampret	`wire dc_en;`
185	161	lampret
186	168	lampret	`//`
187	161	lampret	`// IC and CPU's ifetch`
188	168	lampret	`//`
189	170	lampret	`wire icfetch_stall;`
190			`wire [aw-1:0] icfetch_addr;`
191			`wire [dw-1:0] icfetch_dataout;`
192			`wire ic_en;`
193	161	lampret
194	168	lampret	`//`
195	161	lampret	`// Connection between CPU and PIC`
196	168	lampret	`//`
197	170	lampret	`wire [dw-1:0] spr_dat_pic;`
198			`wire pic_wakeup;`
199			`wire int_low;`
200			`wire int_high;`
201	161	lampret	`wire int_high_tt;`
202
203	168	lampret	`//`
204	161	lampret	`// Connection between CPU and PM`
205	168	lampret	`//`
206	170	lampret	`wire [dw-1:0] spr_dat_pm;`
207	161	lampret
208	168	lampret	`//`
209	161	lampret	`// CPU and TT`
210	168	lampret	`//`
211	170	lampret	`wire [dw-1:0] spr_dat_tt;`
212	161	lampret	`wire tt_int;`
213
214	168	lampret	`//`
215	161	lampret	`// CPU and external Trace port`
216	168	lampret	`//`
217	170	lampret	`input tp_dir_in;`
218			`input [1:0] tp_sel;`
219			`input [dw-1:0] tp_in;`
220			`output [dw-1:0] tp_out;`
221	161	lampret
222	168	lampret	`//`
223	161	lampret	`// Trace port and caches/MMUs`
224	168	lampret	`//`
225	170	lampret	wire [`TP2W_WIDTH-1:0] tp2w;
226			wire [`TP3W_WIDTH-1:0] tp3w;
227	161	lampret
228			`//`
229			`// Assignments`
230			`//`
231			`assign int_high_tt = int_high \| tt_int;`
232
233			`//`
234			`// Instantiation of Instruction WISHBONE BIU`
235			`//`
236			`wb_biu iwb_biu(`
237			`// WISHBONE interface`
238			`.wb_clk_i(iwb_clk_i),`
239			`.wb_rst_i(iwb_rst_i),`
240			`.wb_ack_i(iwb_ack_i),`
241			`.wb_err_i(iwb_err_i),`
242			`.wb_rty_i(iwb_rty_i),`
243			`.wb_dat_i(iwb_dat_i),`
244			`.wb_cyc_o(iwb_cyc_o),`
245			`.wb_adr_o(iwb_adr_o),`
246			`.wb_stb_o(iwb_stb_o),`
247			`.wb_we_o(iwb_we_o),`
248			`.wb_sel_o(iwb_sel_o),`
249			`.wb_dat_o(iwb_dat_o),`
250
251			`// Internal RISC bus`
252			`.biu_to_biu(32'b0),`
253			`.biu_addr(icbiu_addr),`
254			`.biu_read(icbiu_read),`
255			`.biu_write(1'b0),`
256			`.biu_rdy(icbiu_rdy),`
257	166	lampret	`.biu_from_biu(icbiu_from_biu),`
258	170	lampret	`.biu_sel(icbiu_sel)`
259	161	lampret	`);`
260
261			`//`
262			`// Instantiation of Data WISHBONE BIU`
263			`//`
264			`wb_biu dwb_biu(`
265			`// WISHBONE interface`
266			`.wb_clk_i(dwb_clk_i),`
267			`.wb_rst_i(dwb_rst_i),`
268			`.wb_ack_i(dwb_ack_i),`
269			`.wb_err_i(dwb_err_i),`
270			`.wb_rty_i(dwb_rty_i),`
271			`.wb_dat_i(dwb_dat_i),`
272			`.wb_cyc_o(dwb_cyc_o),`
273			`.wb_adr_o(dwb_adr_o),`
274			`.wb_stb_o(dwb_stb_o),`
275			`.wb_we_o(dwb_we_o),`
276			`.wb_sel_o(dwb_sel_o),`
277			`.wb_dat_o(dwb_dat_o),`
278
279			`// Internal RISC bus`
280			`.biu_to_biu(dcbiu_to_biu),`
281			`.biu_addr(dcbiu_addr),`
282			`.biu_read(dcbiu_read),`
283			`.biu_write(dcbiu_write),`
284			`.biu_rdy(dcbiu_rdy),`
285	166	lampret	`.biu_from_biu(dcbiu_from_biu),`
286			`.biu_sel(dcbiu_sel)`
287	161	lampret	`);`
288
289			`//`
290			`// Instantiation of Instruction Cache`
291			`//`
292			`ic ic(`
293			`.clk(clk),`
294			`.rst(rst),`
295			`.clkdiv_by_2(clkdiv_by_2),`
296
297			`// These connect IC to CPU's ifetch`
298			`.icfetch_addr(icfetch_addr),`
299			.icfetch_op(`FETCHOP_LW),
300			`.icfetch_dataout(icfetch_dataout),`
301			`.icfetch_stall(icfetch_stall),`
302	170	lampret	`.ic_en(ic_en),`
303	161	lampret
304			`// These connect IC to BIU`
305			`.icbiu_rdy(icbiu_rdy),`
306			`.icbiu_datain(icbiu_from_biu),`
307			`.icbiu_addr(icbiu_addr),`
308			`.icbiu_read(icbiu_read),`
309	170	lampret	`.icbiu_sel(icbiu_sel),`
310	161	lampret
311			`// These connect IC to SPRS`
312	168	lampret	`.spr_dat_i(spr_dat_cpu)`
313	161	lampret	`);`
314
315			`//`
316			`// Instantiation of Instruction Cache`
317			`//`
318			`cpu cpu(`
319			`.clk(clk),`
320			`.rst(rst),`
321
322			`// These connect IC and IFETCHER inside CPU`
323			`.ic_insn(icfetch_dataout),`
324			`.ic_pcaddr(icfetch_addr),`
325			`.ic_stall(icfetch_stall),`
326	170	lampret	`.ic_en(ic_en),`
327	161	lampret
328			`// These connect CPU to external Trace port`
329			`.tp_dir_in(tp_dir_in),`
330			`.tp_sel(tp_sel),`
331			`.tp_in(tp_in),`
332			`.tp_out(tp_out),`
333
334			`// These connect DC and CPU's LSU`
335			`.dclsu_stall(dclsu_stall),`
336			`.dclsu_addr(dclsu_addr),`
337			`.dclsu_datain(dclsu_from_dc),`
338			`.dclsu_dataout(dclsu_to_dc),`
339			`.dclsu_lsuop(dclsu_lsuop),`
340	168	lampret	`.dc_en(dc_en),`
341	161	lampret
342			`// These connect PIC and CPU's EXCEPT`
343			`.int_high(int_high_tt),`
344			`.int_low(int_low),`
345
346			`// SPRs`
347			`.spr_addr(spr_addr),`
348			`.spr_dataout(spr_dat_cpu),`
349			`.spr_dat_pic(spr_dat_pic),`
350			`.spr_dat_tt(spr_dat_tt),`
351			`.spr_dat_pm(spr_dat_pm),`
352			`.spr_cs(spr_cs),`
353			`.spr_we(spr_we),`
354
355			`// These connect trace port to caches and MMUs`
356			`.tp2w(tp2w),`
357	168	lampret	`.tp3w(tp3w)`
358	161	lampret	`);`
359
360			`//`
361			`// Instantiation of Data Cache`
362			`//`
363			`dc dc(`
364			`.clk(clk),`
365			`.rst(rst),`
366			`.clkdiv_by_2(clkdiv_by_2),`
367
368			`// These connect DC to CPU's LSU`
369			`.dclsu_addr(dclsu_addr),`
370			`.dclsu_lsuop(dclsu_lsuop),`
371			`.dclsu_datain(dclsu_to_dc),`
372			`.dclsu_dataout(dclsu_from_dc),`
373			`.dclsu_stall(dclsu_stall),`
374	168	lampret	`.dc_en(dc_en),`
375	161	lampret
376			`// These connect DC to BIU`
377			`.dcbiu_rdy(dcbiu_rdy),`
378			`.dcbiu_datain(dcbiu_from_biu),`
379			`.dcbiu_dataout(dcbiu_to_biu),`
380			`.dcbiu_addr(dcbiu_addr),`
381			`.dcbiu_read(dcbiu_read),`
382			`.dcbiu_write(dcbiu_write),`
383	166	lampret	`.dcbiu_sel(dcbiu_sel),`
384	161	lampret
385			`// Trace port`
386	168	lampret	`.tp2w(tp2w)`
387	161	lampret	`);`
388
389			`//`
390			`// Programmable interrupt controller`
391			`//`
392			`pic pic(`
393			`// RISC Internal Interface`
394			`.clk(clk),`
395			`.rst(rst),`
396			.spr_cs(spr_cs[`SPR_GROUP_PIC]),
397			`.spr_write(spr_we),`
398			`.spr_addr(spr_addr),`
399			`.spr_dat_i(spr_dat_cpu),`
400			`.spr_dat_o(spr_dat_pic),`
401			`.pic_wakeup(pic_wakeup),`
402			`.int_low(int_low),`
403			`.int_high(int_high),`
404
405			`// PIC Interface`
406			`.pic_int(pic_ints)`
407			`);`
408
409			`//`
410			`// Instantiation of Tick timer`
411			`//`
412			`tt tt(`
413			`// RISC Internal Interface`
414			`.clk(clk),`
415			`.rst(rst),`
416			.spr_cs(spr_cs[`SPR_GROUP_TT]),
417			`.spr_write(spr_we),`
418			`.spr_addr(spr_addr),`
419			`.spr_dat_i(spr_dat_cpu),`
420			`.spr_dat_o(spr_dat_tt),`
421			`.int(tt_int)`
422			`);`
423
424			`//`
425			`// Instantiation of Power Management`
426			`//`
427			`pm pm(`
428			`// RISC Internal Interface`
429			`.clk(clk),`
430			`.rst(rst),`
431			`.pic_wakeup(pic_wakeup),`
432			`.spr_write(spr_we),`
433			`.spr_addr(spr_addr),`
434			`.spr_dat_i(spr_dat_cpu),`
435			`.spr_dat_o(spr_dat_pm),`
436
437			`// Power Management Interface`
438			`.pm_clksd(pm_clksd),`
439			`.pm_cpustall(pm_cpustall),`
440			`.pm_dc_gate(pm_dc_gate),`
441			`.pm_ic_gate(pm_ic_gate),`
442			`.pm_dmmu_gate(pm_dmmu_gate),`
443			`.pm_immu_gate(pm_immu_gate),`
444			`.pm_tt_gate(pm_tt_gate),`
445			`.pm_cpu_gate(pm_cpu_gate),`
446			`.pm_wakeup(pm_wakeup),`
447			`.pm_lvolt(pm_lvolt)`
448			`);`
449
450
451			`endmodule`

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