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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  OR1200 Top Level                                            ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.4  2001/08/13 03:36:20  lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module or1200(
        // System
        clk, rst, pic_ints, clkdiv_by_2,
 
        // Instruction WISHBONE INTERFACE
        iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
        iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
 
        // Data WISHBONE INTERFACE
        dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
        dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
 
        // External Debug Interface
        dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
        dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
 
        // Power Management
        pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,
        pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt
 
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `OPERAND_WIDTH;
parameter ppic_ints = `PIC_INTS;
 
//
// I/O
//
 
//
// System
//
input                   clk;
input                   rst;
input                   clkdiv_by_2;
input   [ppic_ints-1:0]  pic_ints;
 
//
// Instruction WISHBONE interface
//
input                   iwb_clk_i;      // clock input
input                   iwb_rst_i;      // reset input
input                   iwb_ack_i;      // normal termination
input                   iwb_err_i;      // termination w/ error
input                   iwb_rty_i;      // termination w/ retry
input   [dw-1:0] iwb_dat_i;      // input data bus
output                  iwb_cyc_o;      // cycle valid output
output  [aw-1:0] iwb_adr_o;      // address bus outputs
output                  iwb_stb_o;      // strobe output
output                  iwb_we_o;       // indicates write transfer
output  [3:0]            iwb_sel_o;      // byte select outputs
output  [dw-1:0] iwb_dat_o;      // output data bus
 
//
// Data WISHBONE interface
//
input                   dwb_clk_i;      // clock input
input                   dwb_rst_i;      // reset input
input                   dwb_ack_i;      // normal termination
input                   dwb_err_i;      // termination w/ error
input                   dwb_rty_i;      // termination w/ retry
input   [dw-1:0] dwb_dat_i;      // input data bus
output                  dwb_cyc_o;      // cycle valid output
output  [aw-1:0] dwb_adr_o;      // address bus outputs
output                  dwb_stb_o;      // strobe output
output                  dwb_we_o;       // indicates write transfer
output  [3:0]            dwb_sel_o;      // byte select outputs
output  [dw-1:0] dwb_dat_o;      // output data bus
 
//
// External Debug Interface
//
input                   dbg_stall_i;    // External Stall Input
input   [dw-1:0] dbg_dat_i;      // External Data Input
input   [aw-1:0] dbg_adr_i;      // External Address Input
input   [2:0]            dbg_op_i;       // External Operation Select Input
input                   dbg_ewt_i;      // External Watchpoint Trigger Input
output  [3:0]            dbg_lss_o;      // External Load/Store Unit Status
output  [1:0]            dbg_is_o;       // External Insn Fetch Status
output  [10:0]           dbg_wp_o;       // Watchpoints Outputs
output                  dbg_bp_o;       // Breakpoint Output
output  [dw-1:0] dbg_dat_o;      // External Data Output
 
//
// Power Management
//
input                   pm_cpustall;
output  [3:0]            pm_clksd;
output                  pm_dc_gate;
output                  pm_ic_gate;
output                  pm_dmmu_gate;
output                  pm_immu_gate;
output                  pm_tt_gate;
output                  pm_cpu_gate;
output                  pm_wakeup;
output                  pm_lvolt;
 
 
//
// Internal wires and regs
//
 
//
// DC to BIU
//
wire                    dcbiu_rdy;
wire    [dw-1:0]         dcbiu_from_biu;
wire    [dw-1:0]         dcbiu_to_biu;
wire    [aw-1:0]         dcbiu_addr;
wire                    dcbiu_read;
wire                    dcbiu_write;
wire    [3:0]            dcbiu_sel;
 
//
// IC to BIU
//
wire                    icbiu_rdy;
wire    [dw-1:0] icbiu_from_biu;
wire    [aw-1:0] icbiu_addr;
wire                    icbiu_read;
wire    [3:0]            icbiu_sel;
 
//
// CPU's SPR access to various RISC units (shared wires)
//
wire                    supv;
wire    [aw-1:0] spr_addr;
wire    [dw-1:0] spr_dat_cpu;
wire    [31:0]           spr_cs;
wire                    spr_we;
 
//
// DMMU and CPU
//
wire                    dmmu_en;
wire                    dmmuexcept_miss;
wire                    dmmuexcept_fault;
wire    [31:0]           spr_dat_dmmu;
 
//
// DMMU and DC
//
wire    [aw-1:0] dcdmmu_paddr;
 
//
// DC and CPU's LSU
//
wire                    dclsu_stall;
wire                    dclsu_unstall;
wire    [aw-1:0] dclsu_addr;
wire    [aw-1:0] dclsu_from_dc;
wire    [aw-1:0] dclsu_to_dc;
wire    [`LSUOP_WIDTH-1:0] dclsu_lsuop;
wire                    dc_en;
 
//
// IMMU and CPU
//
wire                    immu_en;
wire                    immuexcept_miss;
wire                    immuexcept_fault;
wire    [31:0]           spr_dat_immu;
 
//
// IC and CPU's ifetch
//
wire                    icfetch_stall;
wire    [aw-1:0] icfetch_addr;
wire    [dw-1:0] icfetch_dataout;
wire    [`FETCHOP_WIDTH-1:0] icfetch_op;
wire                    ic_en;
 
//
// IMMU and IC
//
wire    [aw-1:0] icimmu_paddr;
 
//
// Connection between CPU and PIC
//
wire    [dw-1:0] spr_dat_pic;
wire                    pic_wakeup;
wire                    int_low;
wire                    int_high;
wire                    int_high_tt;
 
//
// Connection between CPU and PM
//
wire    [dw-1:0] spr_dat_pm;
 
//
// CPU and TT
//
wire    [dw-1:0] spr_dat_tt;
wire                    tt_int;
 
//
// Trace port and caches/MMUs
//
wire    [dw-1:0] spr_dat_du;
wire                    du_stall;
wire    [dw-1:0] du_addr;
wire    [dw-1:0] du_dat_du;
wire                    du_read;
wire                    du_write;
wire    [`EXCEPT_WIDTH-1:0] du_except;
 
wire                    ex_freeze;
wire    [`BRANCHOP_WIDTH-1:0]    branch_op;
 
//
// Assignments
//
assign int_high_tt = int_high | tt_int;
 
//
// Instantiation of Instruction WISHBONE BIU
//
wb_biu iwb_biu(
        // WISHBONE interface
        .wb_clk_i(iwb_clk_i),
        .wb_rst_i(iwb_rst_i),
        .wb_ack_i(iwb_ack_i),
        .wb_err_i(iwb_err_i),
        .wb_rty_i(iwb_rty_i),
        .wb_dat_i(iwb_dat_i),
        .wb_cyc_o(iwb_cyc_o),
        .wb_adr_o(iwb_adr_o),
        .wb_stb_o(iwb_stb_o),
        .wb_we_o(iwb_we_o),
        .wb_sel_o(iwb_sel_o),
        .wb_dat_o(iwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(32'b0),
        .biu_addr(icbiu_addr),
        .biu_read(icbiu_read),
        .biu_write(1'b0),
        .biu_rdy(icbiu_rdy),
        .biu_from_biu(icbiu_from_biu),
        .biu_sel(icbiu_sel)
);
 
//
// Instantiation of Data WISHBONE BIU
//
wb_biu dwb_biu(
        // WISHBONE interface
        .wb_clk_i(dwb_clk_i),
        .wb_rst_i(dwb_rst_i),
        .wb_ack_i(dwb_ack_i),
        .wb_err_i(dwb_err_i),
        .wb_rty_i(dwb_rty_i),
        .wb_dat_i(dwb_dat_i),
        .wb_cyc_o(dwb_cyc_o),
        .wb_adr_o(dwb_adr_o),
        .wb_stb_o(dwb_stb_o),
        .wb_we_o(dwb_we_o),
        .wb_sel_o(dwb_sel_o),
        .wb_dat_o(dwb_dat_o),
 
        // Internal RISC bus
        .biu_to_biu(dcbiu_to_biu),
        .biu_addr(dcbiu_addr),
        .biu_read(dcbiu_read),
        .biu_write(dcbiu_write),
        .biu_rdy(dcbiu_rdy),
        .biu_from_biu(dcbiu_from_biu),
        .biu_sel(dcbiu_sel)
);
 
//
// Instantiation of IMMU
//
immu immu(
        // Rst and clk
        .clk(clk),
        .rst(rst),
 
        // Fetch i/f
        .immu_en(immu_en),
        .supv(supv),
        .immufetch_vaddr(icfetch_addr),
        .immufetch_op(icfetch_op),
        .immufetch_stall(),
 
        // Except I/F
        .immuexcept_miss(immuexcept_miss),
        .immuexcept_fault(immuexcept_fault),
 
        // SPR access
        .spr_cs(spr_cs[`SPR_GROUP_IMMU]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_immu),
 
        // IC i/f
        .icimmu_paddr(icimmu_paddr)
);
 
//
// Instantiation of Instruction Cache
//
ic ic(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect IC to CPU's ifetch
        .icfetch_addr(icimmu_paddr),
        .icfetch_op(icfetch_op),
        .icfetch_dataout(icfetch_dataout),
        .icfetch_stall(icfetch_stall),
        .ic_en(ic_en),
 
        // SPR access
        .spr_cs(spr_cs[`SPR_GROUP_IC]),
        .spr_write(spr_we),
        .spr_dat_i(spr_dat_cpu),
 
        // These connect IC to BIU
        .icbiu_rdy(icbiu_rdy),
        .icbiu_datain(icbiu_from_biu),
        .icbiu_addr(icbiu_addr),
        .icbiu_read(icbiu_read),
        .icbiu_sel(icbiu_sel)
);
 
//
// Instantiation of Instruction Cache
//
cpu cpu(
        .clk(clk),
        .rst(rst),
 
        // Connection IC and IFETCHER inside CPU
        .ic_insn(icfetch_dataout),
        .ic_addr(icfetch_addr),
        .ic_stall(icfetch_stall),
        .ic_fetchop(icfetch_op),
        .ic_en(ic_en),
 
        // Connection CPU to external Trace port
        .ex_freeze(ex_freeze),
        .branch_op(branch_op),
        .du_stall(du_stall),
        .du_addr(du_addr),
        .du_dat_du(du_dat_du),
        .du_read(du_read),
        .du_write(du_write),
        .du_except(du_except),
 
        // Connection IMMU and CPU internally
        .immu_en(immu_en),
        .immuexcept_miss(immuexcept_miss),
        .immuexcept_fault(immuexcept_fault),
 
        // Connection DMMU and CPU internally
        .dmmu_en(dmmu_en),
        .dmmuexcept_miss(dmmuexcept_miss),
        .dmmuexcept_fault(dmmuexcept_fault),
 
        // Connection DC and CPU's LSU
        .dclsu_stall(dclsu_stall),
        .dclsu_unstall(dclsu_unstall),
        .dclsu_addr(dclsu_addr),
        .dclsu_datain(dclsu_from_dc),
        .dclsu_dataout(dclsu_to_dc),
        .dclsu_lsuop(dclsu_lsuop),
        .dc_en(dc_en),
 
        // Connection PIC and CPU's EXCEPT
        .int_high(int_high_tt),
        .int_low(int_low),
 
        // SPRs
        .supv(supv),
        .spr_addr(spr_addr),
        .spr_dataout(spr_dat_cpu),
        .spr_dat_pic(spr_dat_pic),
        .spr_dat_tt(spr_dat_tt),
        .spr_dat_pm(spr_dat_pm),
        .spr_dat_dmmu(spr_dat_dmmu),
        .spr_dat_immu(spr_dat_immu),
        .spr_dat_du(spr_dat_du),
        .spr_cs(spr_cs),
        .spr_we(spr_we)
);
 
//
// Instantiation of DMMU
//
dmmu dmmu(
        // Rst and clk
        .clk(clk),
        .rst(rst),
 
        // LSU i/f
        .dmmu_en(dmmu_en),
        .supv(supv),
        .dmmulsu_vaddr(dclsu_addr),
        .dmmulsu_lsuop(dclsu_lsuop),
        .dmmulsu_stall(),
 
        // Except I/F
        .dmmuexcept_miss(dmmuexcept_miss),
        .dmmuexcept_fault(dmmuexcept_fault),
 
        // SPR access
        .spr_cs(spr_cs[`SPR_GROUP_DMMU]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_dmmu),
 
        // DC i/f
        .dcdmmu_paddr(dcdmmu_paddr)
);
 
//
// Instantiation of Data Cache
//
dc dc(
        .clk(clk),
        .rst(rst),
        .clkdiv_by_2(clkdiv_by_2),
 
        // These connect DC to CPU's LSU
        .dclsu_addr(dcdmmu_paddr),
        .dclsu_lsuop(dclsu_lsuop),
        .dclsu_datain(dclsu_to_dc),
        .dclsu_dataout(dclsu_from_dc),
        .dclsu_stall(dclsu_stall),
        .dclsu_unstall(dclsu_unstall),
        .dc_en(dc_en),
 
        // SPR access
        .spr_cs(spr_cs[`SPR_GROUP_DC]),
        .spr_write(spr_we),
        .spr_dat_i(spr_dat_cpu),
 
        // These connect DC to BIU
        .dcbiu_rdy(dcbiu_rdy),
        .dcbiu_datain(dcbiu_from_biu),
        .dcbiu_dataout(dcbiu_to_biu),
        .dcbiu_addr(dcbiu_addr),
        .dcbiu_read(dcbiu_read),
        .dcbiu_write(dcbiu_write),
        .dcbiu_sel(dcbiu_sel)
);
 
//
// Instantiation of Debug Unit
//
du du(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .dclsu_lsuop(dclsu_lsuop),
        .icfetch_op(icfetch_op),
        .ex_freeze(ex_freeze),
        .branch_op(branch_op),
 
        // DU's access to SPR unit
        .du_stall(du_stall),
        .du_addr(du_addr),
        .du_dat_i(spr_dat_cpu),
        .du_dat_o(du_dat_du),
        .du_read(du_read),
        .du_write(du_write),
        .du_except(du_except),
 
        // Access to DU's SPRs
        .spr_cs(spr_cs[`SPR_GROUP_DU]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_du),
 
        // External Debug Interface
        .dbg_stall_i(dbg_stall_i),
        .dbg_dat_i(dbg_dat_i),
        .dbg_adr_i(dbg_adr_i),
        .dbg_op_i(dbg_op_i),
        .dbg_ewt_i(dbg_ewt_i),
        .dbg_lss_o(dbg_lss_o),
        .dbg_is_o(dbg_is_o),
        .dbg_wp_o(dbg_wp_o),
        .dbg_bp_o(dbg_bp_o),
        .dbg_dat_o(dbg_dat_o)
);
 
//
// Programmable interrupt controller
//
pic pic(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_PIC]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pic),
        .pic_wakeup(pic_wakeup),
        .int_low(int_low),
        .int_high(int_high),
 
        // PIC Interface
        .pic_int(pic_ints)
);
 
//
// Instantiation of Tick timer
//
tt tt(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .spr_cs(spr_cs[`SPR_GROUP_TT]),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_tt),
        .int(tt_int)
);
 
//
// Instantiation of Power Management
//
pm pm(
        // RISC Internal Interface
        .clk(clk),
        .rst(rst),
        .pic_wakeup(pic_wakeup),
        .spr_write(spr_we),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_cpu),
        .spr_dat_o(spr_dat_pm),
 
        // Power Management Interface
        .pm_clksd(pm_clksd),
        .pm_cpustall(pm_cpustall),
        .pm_dc_gate(pm_dc_gate),
        .pm_ic_gate(pm_ic_gate),
        .pm_dmmu_gate(pm_dmmu_gate),
        .pm_immu_gate(pm_immu_gate),
        .pm_tt_gate(pm_tt_gate),
        .pm_cpu_gate(pm_cpu_gate),
        .pm_wakeup(pm_wakeup),
        .pm_lvolt(pm_lvolt)
);
 
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [or1200.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200 Top Level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// OR1200 Top Level ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.9 2001/10/14 13:12:10 lampret`
48			`// MP3 version.`
49			`//`
50			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
51			`// no message`
52			`//`
53			`// Revision 1.4 2001/08/13 03:36:20 lampret`
54			`// Added cfg regs. Moved all defines into one defines.v file. More cleanup.`
55			`//`
56			`// Revision 1.3 2001/08/09 13:39:33 lampret`
57			`// Major clean-up.`
58			`//`
59			`// Revision 1.2 2001/07/22 03:31:54 lampret`
60			`// Fixed RAM's oen bug. Cache bypass under development.`
61			`//`
62			`// Revision 1.1 2001/07/20 00:46:21 lampret`
63			`// Development version of RTL. Libraries are missing.`
64			`//`
65			`//`
66	161	lampret
67	218	lampret	`// synopsys translate_off`
68			`include "timescale.v"
69			`// synopsys translate_on`
70			`include "defines.v"
71
72			`module or1200(`
73			`// System`
74			`clk, rst, pic_ints, clkdiv_by_2,`
75
76			`// Instruction WISHBONE INTERFACE`
77			`iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,`
78			`iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,`
79
80			`// Data WISHBONE INTERFACE`
81			`dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,`
82			`dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,`
83
84			`// External Debug Interface`
85			`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`
86			`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,`
87
88			`// Power Management`
89			`pm_clksd, pm_cpustall, pm_dc_gate, pm_ic_gate, pm_dmmu_gate,`
90			`pm_immu_gate, pm_tt_gate, pm_cpu_gate, pm_wakeup, pm_lvolt`
91
92			`);`
93
94			parameter dw = `OPERAND_WIDTH;
95			parameter aw = `OPERAND_WIDTH;
96			parameter ppic_ints = `PIC_INTS;
97
98			`//`
99			`// I/O`
100			`//`
101
102			`//`
103			`// System`
104			`//`
105			`input clk;`
106			`input rst;`
107			`input clkdiv_by_2;`
108			`input [ppic_ints-1:0] pic_ints;`
109
110			`//`
111			`// Instruction WISHBONE interface`
112			`//`
113			`input iwb_clk_i; // clock input`
114			`input iwb_rst_i; // reset input`
115			`input iwb_ack_i; // normal termination`
116			`input iwb_err_i; // termination w/ error`
117			`input iwb_rty_i; // termination w/ retry`
118			`input [dw-1:0] iwb_dat_i; // input data bus`
119			`output iwb_cyc_o; // cycle valid output`
120			`output [aw-1:0] iwb_adr_o; // address bus outputs`
121			`output iwb_stb_o; // strobe output`
122			`output iwb_we_o; // indicates write transfer`
123			`output [3:0] iwb_sel_o; // byte select outputs`
124			`output [dw-1:0] iwb_dat_o; // output data bus`
125
126			`//`
127			`// Data WISHBONE interface`
128			`//`
129			`input dwb_clk_i; // clock input`
130			`input dwb_rst_i; // reset input`
131			`input dwb_ack_i; // normal termination`
132			`input dwb_err_i; // termination w/ error`
133			`input dwb_rty_i; // termination w/ retry`
134			`input [dw-1:0] dwb_dat_i; // input data bus`
135			`output dwb_cyc_o; // cycle valid output`
136			`output [aw-1:0] dwb_adr_o; // address bus outputs`
137			`output dwb_stb_o; // strobe output`
138			`output dwb_we_o; // indicates write transfer`
139			`output [3:0] dwb_sel_o; // byte select outputs`
140			`output [dw-1:0] dwb_dat_o; // output data bus`
141
142			`//`
143			`// External Debug Interface`
144			`//`
145			`input dbg_stall_i; // External Stall Input`
146			`input [dw-1:0] dbg_dat_i; // External Data Input`
147			`input [aw-1:0] dbg_adr_i; // External Address Input`
148			`input [2:0] dbg_op_i; // External Operation Select Input`
149			`input dbg_ewt_i; // External Watchpoint Trigger Input`
150			`output [3:0] dbg_lss_o; // External Load/Store Unit Status`
151			`output [1:0] dbg_is_o; // External Insn Fetch Status`
152			`output [10:0] dbg_wp_o; // Watchpoints Outputs`
153			`output dbg_bp_o; // Breakpoint Output`
154			`output [dw-1:0] dbg_dat_o; // External Data Output`
155
156			`//`
157			`// Power Management`
158			`//`
159			`input pm_cpustall;`
160			`output [3:0] pm_clksd;`
161			`output pm_dc_gate;`
162			`output pm_ic_gate;`
163			`output pm_dmmu_gate;`
164			`output pm_immu_gate;`
165			`output pm_tt_gate;`
166			`output pm_cpu_gate;`
167			`output pm_wakeup;`
168			`output pm_lvolt;`
169
170
171			`//`
172			`// Internal wires and regs`
173			`//`
174
175			`//`
176			`// DC to BIU`
177			`//`
178			`wire dcbiu_rdy;`
179			`wire [dw-1:0] dcbiu_from_biu;`
180			`wire [dw-1:0] dcbiu_to_biu;`
181			`wire [aw-1:0] dcbiu_addr;`
182			`wire dcbiu_read;`
183			`wire dcbiu_write;`
184			`wire [3:0] dcbiu_sel;`
185
186			`//`
187			`// IC to BIU`
188			`//`
189			`wire icbiu_rdy;`
190			`wire [dw-1:0] icbiu_from_biu;`
191			`wire [aw-1:0] icbiu_addr;`
192			`wire icbiu_read;`
193			`wire [3:0] icbiu_sel;`
194
195			`//`
196			`// CPU's SPR access to various RISC units (shared wires)`
197			`//`
198			`wire supv;`
199			`wire [aw-1:0] spr_addr;`
200			`wire [dw-1:0] spr_dat_cpu;`
201			`wire [31:0] spr_cs;`
202			`wire spr_we;`
203
204			`//`
205			`// DMMU and CPU`
206			`//`
207			`wire dmmu_en;`
208			`wire dmmuexcept_miss;`
209			`wire dmmuexcept_fault;`
210			`wire [31:0] spr_dat_dmmu;`
211
212			`//`
213			`// DMMU and DC`
214			`//`
215			`wire [aw-1:0] dcdmmu_paddr;`
216
217			`//`
218			`// DC and CPU's LSU`
219			`//`
220			`wire dclsu_stall;`
221			`wire dclsu_unstall;`
222			`wire [aw-1:0] dclsu_addr;`
223			`wire [aw-1:0] dclsu_from_dc;`
224			`wire [aw-1:0] dclsu_to_dc;`
225			wire [`LSUOP_WIDTH-1:0] dclsu_lsuop;
226			`wire dc_en;`
227
228			`//`
229			`// IMMU and CPU`
230			`//`
231			`wire immu_en;`
232			`wire immuexcept_miss;`
233			`wire immuexcept_fault;`
234			`wire [31:0] spr_dat_immu;`
235
236			`//`
237			`// IC and CPU's ifetch`
238			`//`
239			`wire icfetch_stall;`
240			`wire [aw-1:0] icfetch_addr;`
241			`wire [dw-1:0] icfetch_dataout;`
242			wire [`FETCHOP_WIDTH-1:0] icfetch_op;
243			`wire ic_en;`
244
245			`//`
246			`// IMMU and IC`
247			`//`
248			`wire [aw-1:0] icimmu_paddr;`
249
250			`//`
251			`// Connection between CPU and PIC`
252			`//`
253			`wire [dw-1:0] spr_dat_pic;`
254			`wire pic_wakeup;`
255			`wire int_low;`
256			`wire int_high;`
257			`wire int_high_tt;`
258
259			`//`
260			`// Connection between CPU and PM`
261			`//`
262			`wire [dw-1:0] spr_dat_pm;`
263
264			`//`
265			`// CPU and TT`
266			`//`
267			`wire [dw-1:0] spr_dat_tt;`
268			`wire tt_int;`
269
270			`//`
271			`// Trace port and caches/MMUs`
272			`//`
273			`wire [dw-1:0] spr_dat_du;`
274			`wire du_stall;`
275			`wire [dw-1:0] du_addr;`
276			`wire [dw-1:0] du_dat_du;`
277			`wire du_read;`
278			`wire du_write;`
279			wire [`EXCEPT_WIDTH-1:0] du_except;
280
281	215	lampret	`wire ex_freeze;`
282			wire [`BRANCHOP_WIDTH-1:0] branch_op;
283	218	lampret
284			`//`
285			`// Assignments`
286			`//`
287			`assign int_high_tt = int_high \| tt_int;`
288
289			`//`
290			`// Instantiation of Instruction WISHBONE BIU`
291			`//`
292			`wb_biu iwb_biu(`
293			`// WISHBONE interface`
294			`.wb_clk_i(iwb_clk_i),`
295			`.wb_rst_i(iwb_rst_i),`
296			`.wb_ack_i(iwb_ack_i),`
297			`.wb_err_i(iwb_err_i),`
298			`.wb_rty_i(iwb_rty_i),`
299			`.wb_dat_i(iwb_dat_i),`
300			`.wb_cyc_o(iwb_cyc_o),`
301			`.wb_adr_o(iwb_adr_o),`
302			`.wb_stb_o(iwb_stb_o),`
303			`.wb_we_o(iwb_we_o),`
304			`.wb_sel_o(iwb_sel_o),`
305			`.wb_dat_o(iwb_dat_o),`
306
307			`// Internal RISC bus`
308			`.biu_to_biu(32'b0),`
309			`.biu_addr(icbiu_addr),`
310			`.biu_read(icbiu_read),`
311			`.biu_write(1'b0),`
312			`.biu_rdy(icbiu_rdy),`
313			`.biu_from_biu(icbiu_from_biu),`
314			`.biu_sel(icbiu_sel)`
315			`);`
316
317			`//`
318			`// Instantiation of Data WISHBONE BIU`
319			`//`
320			`wb_biu dwb_biu(`
321			`// WISHBONE interface`
322			`.wb_clk_i(dwb_clk_i),`
323			`.wb_rst_i(dwb_rst_i),`
324			`.wb_ack_i(dwb_ack_i),`
325			`.wb_err_i(dwb_err_i),`
326			`.wb_rty_i(dwb_rty_i),`
327			`.wb_dat_i(dwb_dat_i),`
328			`.wb_cyc_o(dwb_cyc_o),`
329			`.wb_adr_o(dwb_adr_o),`
330			`.wb_stb_o(dwb_stb_o),`
331			`.wb_we_o(dwb_we_o),`
332			`.wb_sel_o(dwb_sel_o),`
333			`.wb_dat_o(dwb_dat_o),`
334
335			`// Internal RISC bus`
336			`.biu_to_biu(dcbiu_to_biu),`
337			`.biu_addr(dcbiu_addr),`
338			`.biu_read(dcbiu_read),`
339			`.biu_write(dcbiu_write),`
340			`.biu_rdy(dcbiu_rdy),`
341			`.biu_from_biu(dcbiu_from_biu),`
342			`.biu_sel(dcbiu_sel)`
343			`);`
344
345			`//`
346			`// Instantiation of IMMU`
347			`//`
348			`immu immu(`
349			`// Rst and clk`
350			`.clk(clk),`
351			`.rst(rst),`
352
353			`// Fetch i/f`
354			`.immu_en(immu_en),`
355			`.supv(supv),`
356			`.immufetch_vaddr(icfetch_addr),`
357			`.immufetch_op(icfetch_op),`
358			`.immufetch_stall(),`
359
360			`// Except I/F`
361			`.immuexcept_miss(immuexcept_miss),`
362			`.immuexcept_fault(immuexcept_fault),`
363
364			`// SPR access`
365			.spr_cs(spr_cs[`SPR_GROUP_IMMU]),
366			`.spr_write(spr_we),`
367			`.spr_addr(spr_addr),`
368			`.spr_dat_i(spr_dat_cpu),`
369			`.spr_dat_o(spr_dat_immu),`
370
371			`// IC i/f`
372			`.icimmu_paddr(icimmu_paddr)`
373			`);`
374
375			`//`
376			`// Instantiation of Instruction Cache`
377			`//`
378			`ic ic(`
379			`.clk(clk),`
380			`.rst(rst),`
381			`.clkdiv_by_2(clkdiv_by_2),`
382
383			`// These connect IC to CPU's ifetch`
384			`.icfetch_addr(icimmu_paddr),`
385			`.icfetch_op(icfetch_op),`
386			`.icfetch_dataout(icfetch_dataout),`
387			`.icfetch_stall(icfetch_stall),`
388			`.ic_en(ic_en),`
389
390			`// SPR access`
391			.spr_cs(spr_cs[`SPR_GROUP_IC]),
392			`.spr_write(spr_we),`
393			`.spr_dat_i(spr_dat_cpu),`
394
395			`// These connect IC to BIU`
396			`.icbiu_rdy(icbiu_rdy),`
397			`.icbiu_datain(icbiu_from_biu),`
398			`.icbiu_addr(icbiu_addr),`
399			`.icbiu_read(icbiu_read),`
400			`.icbiu_sel(icbiu_sel)`
401			`);`
402
403			`//`
404			`// Instantiation of Instruction Cache`
405			`//`
406			`cpu cpu(`
407			`.clk(clk),`
408			`.rst(rst),`
409
410			`// Connection IC and IFETCHER inside CPU`
411			`.ic_insn(icfetch_dataout),`
412			`.ic_addr(icfetch_addr),`
413			`.ic_stall(icfetch_stall),`
414			`.ic_fetchop(icfetch_op),`
415			`.ic_en(ic_en),`
416
417			`// Connection CPU to external Trace port`
418	215	lampret	`.ex_freeze(ex_freeze),`
419			`.branch_op(branch_op),`
420	218	lampret	`.du_stall(du_stall),`
421			`.du_addr(du_addr),`
422			`.du_dat_du(du_dat_du),`
423			`.du_read(du_read),`
424			`.du_write(du_write),`
425			`.du_except(du_except),`
426
427			`// Connection IMMU and CPU internally`
428			`.immu_en(immu_en),`
429			`.immuexcept_miss(immuexcept_miss),`
430			`.immuexcept_fault(immuexcept_fault),`
431
432			`// Connection DMMU and CPU internally`
433			`.dmmu_en(dmmu_en),`
434			`.dmmuexcept_miss(dmmuexcept_miss),`
435			`.dmmuexcept_fault(dmmuexcept_fault),`
436
437			`// Connection DC and CPU's LSU`
438			`.dclsu_stall(dclsu_stall),`
439			`.dclsu_unstall(dclsu_unstall),`
440			`.dclsu_addr(dclsu_addr),`
441			`.dclsu_datain(dclsu_from_dc),`
442			`.dclsu_dataout(dclsu_to_dc),`
443			`.dclsu_lsuop(dclsu_lsuop),`
444			`.dc_en(dc_en),`
445
446			`// Connection PIC and CPU's EXCEPT`
447			`.int_high(int_high_tt),`
448			`.int_low(int_low),`
449
450			`// SPRs`
451			`.supv(supv),`
452			`.spr_addr(spr_addr),`
453			`.spr_dataout(spr_dat_cpu),`
454			`.spr_dat_pic(spr_dat_pic),`
455			`.spr_dat_tt(spr_dat_tt),`
456			`.spr_dat_pm(spr_dat_pm),`
457			`.spr_dat_dmmu(spr_dat_dmmu),`
458			`.spr_dat_immu(spr_dat_immu),`
459	215	lampret	`.spr_dat_du(spr_dat_du),`
460	218	lampret	`.spr_cs(spr_cs),`
461			`.spr_we(spr_we)`
462			`);`
463
464			`//`
465			`// Instantiation of DMMU`
466			`//`
467			`dmmu dmmu(`
468			`// Rst and clk`
469			`.clk(clk),`
470			`.rst(rst),`
471
472			`// LSU i/f`
473			`.dmmu_en(dmmu_en),`
474			`.supv(supv),`
475			`.dmmulsu_vaddr(dclsu_addr),`
476			`.dmmulsu_lsuop(dclsu_lsuop),`
477			`.dmmulsu_stall(),`
478
479			`// Except I/F`
480			`.dmmuexcept_miss(dmmuexcept_miss),`
481			`.dmmuexcept_fault(dmmuexcept_fault),`
482
483			`// SPR access`
484			.spr_cs(spr_cs[`SPR_GROUP_DMMU]),
485			`.spr_write(spr_we),`
486			`.spr_addr(spr_addr),`
487			`.spr_dat_i(spr_dat_cpu),`
488			`.spr_dat_o(spr_dat_dmmu),`
489
490			`// DC i/f`
491			`.dcdmmu_paddr(dcdmmu_paddr)`
492			`);`
493
494			`//`
495			`// Instantiation of Data Cache`
496			`//`
497			`dc dc(`
498			`.clk(clk),`
499			`.rst(rst),`
500			`.clkdiv_by_2(clkdiv_by_2),`
501
502			`// These connect DC to CPU's LSU`
503			`.dclsu_addr(dcdmmu_paddr),`
504			`.dclsu_lsuop(dclsu_lsuop),`
505			`.dclsu_datain(dclsu_to_dc),`
506			`.dclsu_dataout(dclsu_from_dc),`
507			`.dclsu_stall(dclsu_stall),`
508			`.dclsu_unstall(dclsu_unstall),`
509			`.dc_en(dc_en),`
510
511			`// SPR access`
512			.spr_cs(spr_cs[`SPR_GROUP_DC]),
513			`.spr_write(spr_we),`
514			`.spr_dat_i(spr_dat_cpu),`
515
516			`// These connect DC to BIU`
517			`.dcbiu_rdy(dcbiu_rdy),`
518			`.dcbiu_datain(dcbiu_from_biu),`
519			`.dcbiu_dataout(dcbiu_to_biu),`
520			`.dcbiu_addr(dcbiu_addr),`
521			`.dcbiu_read(dcbiu_read),`
522			`.dcbiu_write(dcbiu_write),`
523			`.dcbiu_sel(dcbiu_sel)`
524			`);`
525
526			`//`
527			`// Instantiation of Debug Unit`
528			`//`
529			`du du(`
530			`// RISC Internal Interface`
531			`.clk(clk),`
532			`.rst(rst),`
533			`.dclsu_lsuop(dclsu_lsuop),`
534			`.icfetch_op(icfetch_op),`
535	215	lampret	`.ex_freeze(ex_freeze),`
536			`.branch_op(branch_op),`
537	218	lampret
538			`// DU's access to SPR unit`
539			`.du_stall(du_stall),`
540			`.du_addr(du_addr),`
541			`.du_dat_i(spr_dat_cpu),`
542			`.du_dat_o(du_dat_du),`
543			`.du_read(du_read),`
544			`.du_write(du_write),`
545			`.du_except(du_except),`
546
547			`// Access to DU's SPRs`
548			.spr_cs(spr_cs[`SPR_GROUP_DU]),
549			`.spr_write(spr_we),`
550			`.spr_addr(spr_addr),`
551			`.spr_dat_i(spr_dat_cpu),`
552			`.spr_dat_o(spr_dat_du),`
553
554			`// External Debug Interface`
555			`.dbg_stall_i(dbg_stall_i),`
556			`.dbg_dat_i(dbg_dat_i),`
557			`.dbg_adr_i(dbg_adr_i),`
558			`.dbg_op_i(dbg_op_i),`
559			`.dbg_ewt_i(dbg_ewt_i),`
560			`.dbg_lss_o(dbg_lss_o),`
561			`.dbg_is_o(dbg_is_o),`
562			`.dbg_wp_o(dbg_wp_o),`
563			`.dbg_bp_o(dbg_bp_o),`
564			`.dbg_dat_o(dbg_dat_o)`
565			`);`
566
567			`//`
568			`// Programmable interrupt controller`
569			`//`
570			`pic pic(`
571			`// RISC Internal Interface`
572			`.clk(clk),`
573			`.rst(rst),`
574			.spr_cs(spr_cs[`SPR_GROUP_PIC]),
575			`.spr_write(spr_we),`
576			`.spr_addr(spr_addr),`
577			`.spr_dat_i(spr_dat_cpu),`
578			`.spr_dat_o(spr_dat_pic),`
579			`.pic_wakeup(pic_wakeup),`
580			`.int_low(int_low),`
581			`.int_high(int_high),`
582
583			`// PIC Interface`
584			`.pic_int(pic_ints)`
585			`);`
586
587			`//`
588			`// Instantiation of Tick timer`
589			`//`
590			`tt tt(`
591			`// RISC Internal Interface`
592			`.clk(clk),`
593			`.rst(rst),`
594			.spr_cs(spr_cs[`SPR_GROUP_TT]),
595			`.spr_write(spr_we),`
596			`.spr_addr(spr_addr),`
597			`.spr_dat_i(spr_dat_cpu),`
598			`.spr_dat_o(spr_dat_tt),`
599			`.int(tt_int)`
600			`);`
601
602			`//`
603			`// Instantiation of Power Management`
604			`//`
605			`pm pm(`
606			`// RISC Internal Interface`
607			`.clk(clk),`
608			`.rst(rst),`
609			`.pic_wakeup(pic_wakeup),`
610			`.spr_write(spr_we),`
611			`.spr_addr(spr_addr),`
612			`.spr_dat_i(spr_dat_cpu),`
613			`.spr_dat_o(spr_dat_pm),`
614
615			`// Power Management Interface`
616			`.pm_clksd(pm_clksd),`
617			`.pm_cpustall(pm_cpustall),`
618			`.pm_dc_gate(pm_dc_gate),`
619			`.pm_ic_gate(pm_ic_gate),`
620			`.pm_dmmu_gate(pm_dmmu_gate),`
621			`.pm_immu_gate(pm_immu_gate),`
622			`.pm_tt_gate(pm_tt_gate),`
623			`.pm_cpu_gate(pm_cpu_gate),`
624			`.pm_wakeup(pm_wakeup),`
625			`.pm_lvolt(pm_lvolt)`
626			`);`
627
628
629			`endmodule`