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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's reg2mem aligner                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Aligns register data to memory alignment.                   ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module reg2mem(addr, lsu_op, regdata, memdata);
 
parameter width = `OPERAND_WIDTH;
 
//
// I/O
//
input   [1:0]                    addr;
input   [`LSUOP_WIDTH-1:0]       lsu_op;
input   [width-1:0]              regdata;
output  [width-1:0]              memdata;
 
//
// Internal regs and wires
//
reg     [width-1:0]              memdata;
 
//
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
        casex({lsu_op, addr[1:0]})       // synopsys full_case parallel_case
                {`LSUOP_SB, 2'b00} : memdata[31:24] = regdata[7:0];
                {`LSUOP_SH, 2'b00} : memdata[31:24] = regdata[15:8];
                default : memdata[31:24] = regdata[31:24];
        endcase
end
 
//
// Mux to memdata[23:16]
//
always @(lsu_op or addr or regdata) begin
        casex({lsu_op, addr[1:0]})       // synopsys full_case parallel_case
                {`LSUOP_SW, 2'b00} : memdata[23:16] = regdata[23:16];
                default : memdata[23:16] = regdata[7:0];
        endcase
end
 
//
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
        casex({lsu_op, addr[1:0]})       // synopsys full_case parallel_case
                {`LSUOP_SB, 2'b10} : memdata[15:8] = regdata[7:0];
                default : memdata[15:8] = regdata[15:8];
        endcase
end
 
//
// Mux to memdata[7:0]
//
always @(regdata)
        memdata[7:0] = regdata[7:0];
 
endmodule

Line No.	Rev	Author	Line
1	215	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's reg2mem aligner ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Aligns register data to memory alignment. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
48			`// no message`
49			`//`
50			`// Revision 1.2 2001/08/09 13:39:33 lampret`
51			`// Major clean-up.`
52			`//`
53			`// Revision 1.1 2001/07/20 00:46:21 lampret`
54			`// Development version of RTL. Libraries are missing.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`module reg2mem(addr, lsu_op, regdata, memdata);`
64
65			parameter width = `OPERAND_WIDTH;
66
67			`//`
68			`// I/O`
69			`//`
70			`input [1:0] addr;`
71			input [`LSUOP_WIDTH-1:0] lsu_op;
72			`input [width-1:0] regdata;`
73			`output [width-1:0] memdata;`
74
75			`//`
76			`// Internal regs and wires`
77			`//`
78			`reg [width-1:0] memdata;`
79
80			`//`
81			`// Mux to memdata[31:24]`
82			`//`
83			`always @(lsu_op or addr or regdata) begin`
84			`casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case`
85			{`LSUOP_SB, 2'b00} : memdata[31:24] = regdata[7:0];
86			{`LSUOP_SH, 2'b00} : memdata[31:24] = regdata[15:8];
87			`default : memdata[31:24] = regdata[31:24];`
88			`endcase`
89			`end`
90
91			`//`
92			`// Mux to memdata[23:16]`
93			`//`
94			`always @(lsu_op or addr or regdata) begin`
95			`casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case`
96			{`LSUOP_SW, 2'b00} : memdata[23:16] = regdata[23:16];
97			`default : memdata[23:16] = regdata[7:0];`
98			`endcase`
99			`end`
100
101			`//`
102			`// Mux to memdata[15:8]`
103			`//`
104			`always @(lsu_op or addr or regdata) begin`
105			`casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case`
106			{`LSUOP_SB, 2'b10} : memdata[15:8] = regdata[7:0];
107			`default : memdata[15:8] = regdata[15:8];`
108			`endcase`
109			`end`
110
111			`//`
112			`// Mux to memdata[7:0]`
113			`//`
114			`always @(regdata)`
115			`memdata[7:0] = regdata[7:0];`
116
117			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [reg2mem.v] - Blame information for rev 215