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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file inside CPU                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of register file memories                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "general.h"
 
//`define XCV_RF
`define ART_DP
 
module rf(clk, rst, addrw, dataw, pipeline_freeze, we, addra, dataa, addrb, datab,
        rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w, tpdw
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `REGFILE_ADDR_WIDTH;
 
input clk, rst, pipeline_freeze, we;
 
input [dw-1:0] dataw;
output [dw-1:0] dataa;
output [dw-1:0] datab;
 
input [aw-1:0] addrw;
input [aw-1:0] addra;
input [aw-1:0] addrb;
 
// Trace port
output [31:0] rfa_tqa;
output [31:0] rfb_tqa;
output [`TP1R_WIDTH-1:0] rfa_tmuxed;
output [`TP1R_WIDTH-1:0] rfb_tmuxed;
input [`TP1W_WIDTH-1:0] tp1w;
input [31:0] tpdw;
 
wire [dw-1:0] from_rfa, from_rfb;
 
wire [dw-1:0] t_dataw; // for test port
wire [aw-1:0] t_addrw; // for test port
wire [aw-1:0] t_addra; // for test port
wire [aw-1:0] t_addrb; // for test port
 
reg [dw:0] dataa_saved, datab_saved;
 
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
 
// Stores operand from RF_A into temp reg when pipeline is frozen
always @(posedge clk or posedge rst)
        if (rst) begin
                dataa_saved <= #1 33'b0;
        end
        else if (pipeline_freeze & !dataa_saved[32]) begin
                dataa_saved <= #1 {1'b1, from_rfa};
        end
        else if (!pipeline_freeze)
                dataa_saved[32] <= #1 1'b0;
 
// Stores operand from RF_B into temp reg when pipeline is frozen
always @(posedge clk or posedge rst)
        if (rst) begin
                datab_saved <= #1 33'b0;
        end
        else if (pipeline_freeze & !datab_saved[32]) begin
                datab_saved <= #1 {1'b1, from_rfb};
        end
        else if (!pipeline_freeze)
                datab_saved[32] <= #1 1'b0;
 
`ifdef XCV_RF
// Instantiation of register file memory (A)
xcv_rfram rf(
        .clk(clk),
        .rst(rst),
        .we(we),
        .addrw(addrw),
        .dataw(dataw),
        .addra(addra),
        .dataa(from_rfa),
        .addrb(addrb),
        .datab(from_rfb)
);
 
`else
 
`ifdef ART_DP
// Instatiation of dual port high density artisan sram memory
art_hsdp_32x32 rf_a(
   .qa(from_rfa),
   .clka(clk),
   .cena(1'b0),
   .wena(1'b1),
   .aa(addra),
   .da(32'b0),
   .oena(1'b0),
   .qb(),
   .clkb(clk),
   .cenb(~we),
   .wenb(1'b0),
   .ab(addrw),
   .db(dataw),
   .oenb(1'b1)
);
 
art_hsdp_32x32 rf_b(
   .qa(from_rfb),
   .clka(clk),
   .cena(1'b0),
   .wena(1'b1),
   .aa(addrb),
   .da(32'b0),
   .oena(1'b0),
   .qb(),
   .clkb(clk),
   .cenb(~we),
   .wenb(1'b0),
   .ab(addrw),
   .db(dataw),
   .oenb(1'b1)
);
 
assign rfa_tqa = 32'b0;
assign rfb_tqa = 32'b0;
assign rfa_tmuxed = `TP1R_WIDTH'b0;
assign rfb_tmuxed = `TP1R_WIDTH'b0;
 
`else
 
// Instantiation of register file memory (A)
art_rf2r_32x32 rf_a(
        .QA(from_rfa),
 
        .OENSQA(rfa_tmuxed[`TP1R_RF_OENSQA]),
        .ASQA(rfa_tmuxed[`TP1R_RF_ASQA]),
        .TQA(rfa_tqa),
        .QSQA(rfa_tmuxed[`TP1R_RF_QSQA]),
        .DSOB(rfa_tmuxed[`TP1R_RF_DSOB]),
        .CENSQB(rfa_tmuxed[`TP1R_RF_CENSQB]),
        .ASQB(rfa_tmuxed[`TP1R_RF_ASQB]),
 
        .CLKA(clk),
        .CENA(1'b0),
        .OENA(1'b0),
        .AA(addra),
        .TISA(tp1w[`TP1W_RF_TISA]),
        .TMSA(tp1w[`TP1W_RF_TMSA]),
        .TCENA(tp1w[`TP1W_RF_TCENA]),
        .TOENA(tp1w[`TP1W_RF_TOENA]),
        .TQOENA(tp1w[`TP1W_RF_TQOENA]),
        .TAA(tp1w[`TP1W_RF_TAA]),
        .CLKB(clk),
        .CENB(~we),
        .AB(addrw),
        .DB(dataw),
        .TISB(tp1w[`TP1W_RF_TISB]),
        .TMSB(tp1w[`TP1W_RF_TMSB]),
        .TCENB(tp1w[`TP1W_RF_TCENB]),
        .TAB(tp1w[`TP1W_RF_TAB]),
        .TDB(tpdw),
        .SMSB(tp1w[`TP1W_RF_SMSB]),
        .DSIB(tp1w[`TP1W_RF_DSIB])
);
 
// Instantiation of register file memory (B)
art_rf2r_32x32 rf_b(
        .QA(from_rfb),
 
        .OENSQA(rfb_tmuxed[`TP1R_RF_OENSQA]),
        .ASQA(rfb_tmuxed[`TP1R_RF_ASQA]),
        .TQA(rfb_tqa),
        .QSQA(rfb_tmuxed[`TP1R_RF_QSQA]),
        .DSOB(rfb_tmuxed[`TP1R_RF_DSOB]),
        .CENSQB(rfb_tmuxed[`TP1R_RF_CENSQB]),
        .ASQB(rfb_tmuxed[`TP1R_RF_ASQB]),
 
        .CLKA(clk),
        .CENA(1'b0),
        .OENA(1'b0),
        .AA(addrb),
        .TISA(tp1w[`TP1W_RF_TISA]),
        .TMSA(tp1w[`TP1W_RF_TMSA]),
        .TCENA(tp1w[`TP1W_RF_TCENA]),
        .TOENA(tp1w[`TP1W_RF_TOENA]),
        .TQOENA(tp1w[`TP1W_RF_TQOENA]),
        .TAA(tp1w[`TP1W_RF_TAA]),
        .CLKB(clk),
        .CENB(~we),
        .AB(addrw),
        .DB(dataw),
        .TISB(tp1w[`TP1W_RF_TISB]),
        .TMSB(tp1w[`TP1W_RF_TMSB]),
        .TCENB(tp1w[`TP1W_RF_TCENB]),
        .TAB(tp1w[`TP1W_RF_TAB]),
        .TDB(tpdw),
        .SMSB(tp1w[`TP1W_RF_SMSB]),
        .DSIB(tp1w[`TP1W_RF_DSIB])
);
`endif
`endif
/*
art_rf2r_32x32 rf_a(
        .qa(from_rfa),
 
        .oensqa(rfa_tmuxed[`TP1R_RF_OENSQA]),
        .asqa(rfa_tmuxed[`TP1R_RF_ASQA]),
        .tqa(rfa_tqa),
        .qsqa(rfa_tmuxed[`TP1R_RF_QSQA]),
        .dsob(rfa_tmuxed[`TP1R_RF_DSOB]),
        .censqb(rfa_tmuxed[`TP1R_RF_CENSQB]),
        .asqb(rfa_tmuxed[`TP1R_RF_ASQB]),
 
        .clka(clk),
        .cena(1'b0),
        .oena(1'b0),
        .aa(addra),
        .tisa(tp1w[`TP1W_RF_TISA]),
        .tmsa(tp1w[`TP1W_RF_TMSA]),
        .tcena(tp1w[`TP1W_RF_TCENA]),
        .toena(tp1w[`TP1W_RF_TOENA]),
        .tqoena(tp1w[`TP1W_RF_TQOENA]),
        .taa(tp1w[`TP1W_RF_TAA]),
        .clkb(clk),
        .cenb(~we),
        .ab(addrw),
        .db(dataw),
        .tisb(tp1w[`TP1W_RF_TISB]),
        .tmsb(tp1w[`TP1W_RF_TMSB]),
        .tcenb(tp1w[`TP1W_RF_TCENB]),
        .tab(tp1w[`TP1W_RF_TAB]),
        .tdb(tpdw),
        .smsb(tp1w[`TP1W_RF_SMSB]),
        .dsib(tp1w[`TP1W_RF_DSIB])
);
 
// Instantiation of register file memory (B)
art_rf2r_32x32 rf_b(
        .qa(from_rfb),
 
        .oensqa(rfb_tmuxed[`TP1R_RF_OENSQA]),
        .asqa(rfb_tmuxed[`TP1R_RF_ASQA]),
        .tqa(rfb_tqa),
        .qsqa(rfb_tmuxed[`TP1R_RF_QSQA]),
        .dsob(rfb_tmuxed[`TP1R_RF_DSOB]),
        .censqb(rfb_tmuxed[`TP1R_RF_CENSQB]),
        .asqb(rfb_tmuxed[`TP1R_RF_ASQB]),
 
        .clka(clk),
        .cena(1'b0),
        .oena(1'b0),
        .aa(addrb),
        .tisa(tp1w[`TP1W_RF_TISA]),
        .tmsa(tp1w[`TP1W_RF_TMSA]),
        .tcena(tp1w[`TP1W_RF_TCENA]),
        .toena(tp1w[`TP1W_RF_TOENA]),
        .tqoena(tp1w[`TP1W_RF_TQOENA]),
        .taa(tp1w[`TP1W_RF_TAA]),
        .clkb(clk),
        .cenb(~we),
        .ab(addrw),
        .db(dataw),
        .tisb(tp1w[`TP1W_RF_TISB]),
        .tmsb(tp1w[`TP1W_RF_TMSB]),
        .tcenb(tp1w[`TP1W_RF_TCENB]),
        .tab(tp1w[`TP1W_RF_TAB]),
        .tdb(tpdw),
        .smsb(tp1w[`TP1W_RF_SMSB]),
        .dsib(tp1w[`TP1W_RF_DSIB])
);
*/
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [rf.v] - Blame information for rev 166

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's register file inside CPU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of register file memories ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	166	lampret	`// Revision 1.1 2001/07/20 00:46:21 lampret`
48			`// Development version of RTL. Libraries are missing.`
49	161	lampret	`//`
50	166	lampret	`//`
51	161	lampret
52			`include "general.h"
53
54			//`define XCV_RF
55			`define ART_DP
56
57			`module rf(clk, rst, addrw, dataw, pipeline_freeze, we, addra, dataa, addrb, datab,`
58			`rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w, tpdw`
59			`);`
60
61			parameter dw = `OPERAND_WIDTH;
62			parameter aw = `REGFILE_ADDR_WIDTH;
63
64			`input clk, rst, pipeline_freeze, we;`
65
66			`input [dw-1:0] dataw;`
67			`output [dw-1:0] dataa;`
68			`output [dw-1:0] datab;`
69
70			`input [aw-1:0] addrw;`
71			`input [aw-1:0] addra;`
72			`input [aw-1:0] addrb;`
73
74			`// Trace port`
75			`output [31:0] rfa_tqa;`
76			`output [31:0] rfb_tqa;`
77			output [`TP1R_WIDTH-1:0] rfa_tmuxed;
78			output [`TP1R_WIDTH-1:0] rfb_tmuxed;
79			input [`TP1W_WIDTH-1:0] tp1w;
80			`input [31:0] tpdw;`
81
82			`wire [dw-1:0] from_rfa, from_rfb;`
83
84			`wire [dw-1:0] t_dataw; // for test port`
85			`wire [aw-1:0] t_addrw; // for test port`
86			`wire [aw-1:0] t_addra; // for test port`
87			`wire [aw-1:0] t_addrb; // for test port`
88
89			`reg [dw:0] dataa_saved, datab_saved;`
90
91			`assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;`
92			`assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;`
93
94			`// Stores operand from RF_A into temp reg when pipeline is frozen`
95			`always @(posedge clk or posedge rst)`
96			`if (rst) begin`
97			`dataa_saved <= #1 33'b0;`
98			`end`
99			`else if (pipeline_freeze & !dataa_saved[32]) begin`
100			`dataa_saved <= #1 {1'b1, from_rfa};`
101			`end`
102			`else if (!pipeline_freeze)`
103			`dataa_saved[32] <= #1 1'b0;`
104
105			`// Stores operand from RF_B into temp reg when pipeline is frozen`
106			`always @(posedge clk or posedge rst)`
107			`if (rst) begin`
108			`datab_saved <= #1 33'b0;`
109			`end`
110			`else if (pipeline_freeze & !datab_saved[32]) begin`
111			`datab_saved <= #1 {1'b1, from_rfb};`
112			`end`
113			`else if (!pipeline_freeze)`
114			`datab_saved[32] <= #1 1'b0;`
115
116			`ifdef XCV_RF
117			`// Instantiation of register file memory (A)`
118			`xcv_rfram rf(`
119			`.clk(clk),`
120			`.rst(rst),`
121			`.we(we),`
122			`.addrw(addrw),`
123			`.dataw(dataw),`
124			`.addra(addra),`
125			`.dataa(from_rfa),`
126			`.addrb(addrb),`
127			`.datab(from_rfb)`
128			`);`
129
130			`else
131
132			`ifdef ART_DP
133			`// Instatiation of dual port high density artisan sram memory`
134			`art_hsdp_32x32 rf_a(`
135			`.qa(from_rfa),`
136			`.clka(clk),`
137			`.cena(1'b0),`
138			`.wena(1'b1),`
139			`.aa(addra),`
140			`.da(32'b0),`
141			`.oena(1'b0),`
142			`.qb(),`
143			`.clkb(clk),`
144	166	lampret	`.cenb(~we),`
145	161	lampret	`.wenb(1'b0),`
146			`.ab(addrw),`
147			`.db(dataw),`
148			`.oenb(1'b1)`
149			`);`
150
151			`art_hsdp_32x32 rf_b(`
152			`.qa(from_rfb),`
153			`.clka(clk),`
154			`.cena(1'b0),`
155			`.wena(1'b1),`
156			`.aa(addrb),`
157			`.da(32'b0),`
158			`.oena(1'b0),`
159			`.qb(),`
160			`.clkb(clk),`
161	166	lampret	`.cenb(~we),`
162	161	lampret	`.wenb(1'b0),`
163			`.ab(addrw),`
164			`.db(dataw),`
165			`.oenb(1'b1)`
166			`);`
167
168			`assign rfa_tqa = 32'b0;`
169			`assign rfb_tqa = 32'b0;`
170			assign rfa_tmuxed = `TP1R_WIDTH'b0;
171			assign rfb_tmuxed = `TP1R_WIDTH'b0;
172
173			`else
174
175			`// Instantiation of register file memory (A)`
176			`art_rf2r_32x32 rf_a(`
177			`.QA(from_rfa),`
178
179			.OENSQA(rfa_tmuxed[`TP1R_RF_OENSQA]),
180			.ASQA(rfa_tmuxed[`TP1R_RF_ASQA]),
181			`.TQA(rfa_tqa),`
182			.QSQA(rfa_tmuxed[`TP1R_RF_QSQA]),
183			.DSOB(rfa_tmuxed[`TP1R_RF_DSOB]),
184			.CENSQB(rfa_tmuxed[`TP1R_RF_CENSQB]),
185			.ASQB(rfa_tmuxed[`TP1R_RF_ASQB]),
186
187			`.CLKA(clk),`
188			`.CENA(1'b0),`
189			`.OENA(1'b0),`
190			`.AA(addra),`
191			.TISA(tp1w[`TP1W_RF_TISA]),
192			.TMSA(tp1w[`TP1W_RF_TMSA]),
193			.TCENA(tp1w[`TP1W_RF_TCENA]),
194			.TOENA(tp1w[`TP1W_RF_TOENA]),
195			.TQOENA(tp1w[`TP1W_RF_TQOENA]),
196			.TAA(tp1w[`TP1W_RF_TAA]),
197			`.CLKB(clk),`
198			`.CENB(~we),`
199			`.AB(addrw),`
200			`.DB(dataw),`
201			.TISB(tp1w[`TP1W_RF_TISB]),
202			.TMSB(tp1w[`TP1W_RF_TMSB]),
203			.TCENB(tp1w[`TP1W_RF_TCENB]),
204			.TAB(tp1w[`TP1W_RF_TAB]),
205			`.TDB(tpdw),`
206			.SMSB(tp1w[`TP1W_RF_SMSB]),
207			.DSIB(tp1w[`TP1W_RF_DSIB])
208			`);`
209
210			`// Instantiation of register file memory (B)`
211			`art_rf2r_32x32 rf_b(`
212			`.QA(from_rfb),`
213
214			.OENSQA(rfb_tmuxed[`TP1R_RF_OENSQA]),
215			.ASQA(rfb_tmuxed[`TP1R_RF_ASQA]),
216			`.TQA(rfb_tqa),`
217			.QSQA(rfb_tmuxed[`TP1R_RF_QSQA]),
218			.DSOB(rfb_tmuxed[`TP1R_RF_DSOB]),
219			.CENSQB(rfb_tmuxed[`TP1R_RF_CENSQB]),
220			.ASQB(rfb_tmuxed[`TP1R_RF_ASQB]),
221
222			`.CLKA(clk),`
223			`.CENA(1'b0),`
224			`.OENA(1'b0),`
225			`.AA(addrb),`
226			.TISA(tp1w[`TP1W_RF_TISA]),
227			.TMSA(tp1w[`TP1W_RF_TMSA]),
228			.TCENA(tp1w[`TP1W_RF_TCENA]),
229			.TOENA(tp1w[`TP1W_RF_TOENA]),
230			.TQOENA(tp1w[`TP1W_RF_TQOENA]),
231			.TAA(tp1w[`TP1W_RF_TAA]),
232			`.CLKB(clk),`
233			`.CENB(~we),`
234			`.AB(addrw),`
235			`.DB(dataw),`
236			.TISB(tp1w[`TP1W_RF_TISB]),
237			.TMSB(tp1w[`TP1W_RF_TMSB]),
238			.TCENB(tp1w[`TP1W_RF_TCENB]),
239			.TAB(tp1w[`TP1W_RF_TAB]),
240			`.TDB(tpdw),`
241			.SMSB(tp1w[`TP1W_RF_SMSB]),
242			.DSIB(tp1w[`TP1W_RF_DSIB])
243			`);`
244			`endif
245			`endif
246			`/*`
247			`art_rf2r_32x32 rf_a(`
248			`.qa(from_rfa),`
249
250			.oensqa(rfa_tmuxed[`TP1R_RF_OENSQA]),
251			.asqa(rfa_tmuxed[`TP1R_RF_ASQA]),
252			`.tqa(rfa_tqa),`
253			.qsqa(rfa_tmuxed[`TP1R_RF_QSQA]),
254			.dsob(rfa_tmuxed[`TP1R_RF_DSOB]),
255			.censqb(rfa_tmuxed[`TP1R_RF_CENSQB]),
256			.asqb(rfa_tmuxed[`TP1R_RF_ASQB]),
257
258			`.clka(clk),`
259			`.cena(1'b0),`
260			`.oena(1'b0),`
261			`.aa(addra),`
262			.tisa(tp1w[`TP1W_RF_TISA]),
263			.tmsa(tp1w[`TP1W_RF_TMSA]),
264			.tcena(tp1w[`TP1W_RF_TCENA]),
265			.toena(tp1w[`TP1W_RF_TOENA]),
266			.tqoena(tp1w[`TP1W_RF_TQOENA]),
267			.taa(tp1w[`TP1W_RF_TAA]),
268			`.clkb(clk),`
269			`.cenb(~we),`
270			`.ab(addrw),`
271			`.db(dataw),`
272			.tisb(tp1w[`TP1W_RF_TISB]),
273			.tmsb(tp1w[`TP1W_RF_TMSB]),
274			.tcenb(tp1w[`TP1W_RF_TCENB]),
275			.tab(tp1w[`TP1W_RF_TAB]),
276			`.tdb(tpdw),`
277			.smsb(tp1w[`TP1W_RF_SMSB]),
278			.dsib(tp1w[`TP1W_RF_DSIB])
279			`);`
280
281			`// Instantiation of register file memory (B)`
282			`art_rf2r_32x32 rf_b(`
283			`.qa(from_rfb),`
284
285			.oensqa(rfb_tmuxed[`TP1R_RF_OENSQA]),
286			.asqa(rfb_tmuxed[`TP1R_RF_ASQA]),
287			`.tqa(rfb_tqa),`
288			.qsqa(rfb_tmuxed[`TP1R_RF_QSQA]),
289			.dsob(rfb_tmuxed[`TP1R_RF_DSOB]),
290			.censqb(rfb_tmuxed[`TP1R_RF_CENSQB]),
291			.asqb(rfb_tmuxed[`TP1R_RF_ASQB]),
292
293			`.clka(clk),`
294			`.cena(1'b0),`
295			`.oena(1'b0),`
296			`.aa(addrb),`
297			.tisa(tp1w[`TP1W_RF_TISA]),
298			.tmsa(tp1w[`TP1W_RF_TMSA]),
299			.tcena(tp1w[`TP1W_RF_TCENA]),
300			.toena(tp1w[`TP1W_RF_TOENA]),
301			.tqoena(tp1w[`TP1W_RF_TQOENA]),
302			.taa(tp1w[`TP1W_RF_TAA]),
303			`.clkb(clk),`
304			`.cenb(~we),`
305			`.ab(addrw),`
306			`.db(dataw),`
307			.tisb(tp1w[`TP1W_RF_TISB]),
308			.tmsb(tp1w[`TP1W_RF_TMSB]),
309			.tcenb(tp1w[`TP1W_RF_TCENB]),
310			.tab(tp1w[`TP1W_RF_TAB]),
311			`.tdb(tpdw),`
312			.smsb(tp1w[`TP1W_RF_SMSB]),
313			.dsib(tp1w[`TP1W_RF_DSIB])
314			`);`
315			`*/`
316
317			`endmodule`