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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file inside CPU                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of register file memories                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
`include "timescale.v"
`include "defines.v"
 
module rf(
        // Clock and reset
        clk, rst,
 
        // Write i/f
        addrw, dataw, we,
 
        // Read i/f
        pipeline_freeze, addra, addrb, dataa, datab,
 
        // Debug
        rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `REGFILE_ADDR_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Write i/f
//
input   [aw-1:0]         addrw;
input   [dw-1:0]         dataw;
input                           we;
 
//
// Read i/f
//
input                           pipeline_freeze;
input   [aw-1:0]         addra;
input   [aw-1:0]         addrb;
output  [dw-1:0]         dataa;
output  [dw-1:0]         datab;
 
//
// Debug
//
output  [31:0]                   rfa_tqa;
output  [31:0]                   rfb_tqa;
output  [`TP1R_WIDTH-1:0]        rfa_tmuxed;
output  [`TP1R_WIDTH-1:0]        rfb_tmuxed;
input   [`TP1W_WIDTH-1:0]        tp1w;
 
//
// Internal wires and regs
//
wire    [dw-1:0]         from_rfa;
wire    [dw-1:0]         from_rfb;
wire    [dw-1:0]         t_dataw; // for test port
wire    [aw-1:0]         t_addrw; // for test port
wire    [aw-1:0]         t_addra; // for test port
wire    [aw-1:0]         t_addrb; // for test port
reg     [dw:0]                   dataa_saved;
reg     [dw:0]                   datab_saved;
 
//
// Simple assignments
//
assign rfa_tqa = 32'b0;
assign rfb_tqa = 32'b0;
assign rfa_tmuxed = `TP1R_WIDTH'b0;
assign rfb_tmuxed = `TP1R_WIDTH'b0;
 
//
// Operand A comes from RF or from saved A register
//
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
 
//
// Operand B comes from RF or from saved B register
//
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
 
//
// Stores operand from RF_A into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
        if (rst) begin
                dataa_saved <= #1 33'b0;
        end
        else if (pipeline_freeze & !dataa_saved[32]) begin
                dataa_saved <= #1 {1'b1, from_rfa};
        end
        else if (!pipeline_freeze)
                dataa_saved[32] <= #1 1'b0;
 
//
// Stores operand from RF_B into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
        if (rst) begin
                datab_saved <= #1 33'b0;
        end
        else if (pipeline_freeze & !datab_saved[32]) begin
                datab_saved <= #1 {1'b1, from_rfb};
        end
        else if (!pipeline_freeze)
                datab_saved[32] <= #1 1'b0;
 
//
// Instantiation of register file dual-port RAM A
//
generic_dpram_32x32 rf_a(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(1'b1),
        .oe_a(1'b1),
        .addr_a(addra),
        .do_a(from_rfa),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(we),
        .we_b(we),
        .addr_b(addrw),
        .di_b(dataw)
);
 
//
// Instantiation of register file dual-port RAM B
//
generic_dpram_32x32 rf_b(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(1'b1),
        .oe_a(1'b1),
        .addr_a(addrb),
        .do_a(from_rfb),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(we),
        .we_b(we),
        .addr_b(addrw),
        .di_b(dataw)
);
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's register file inside CPU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of register file memories ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	168	lampret	`// Revision 1.2 2001/07/22 03:31:54 lampret`
48			`// Fixed RAM's oen bug. Cache bypass under development.`
49			`//`
50	166	lampret	`// Revision 1.1 2001/07/20 00:46:21 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	166	lampret	`//`
54	161	lampret
55	168	lampret	`include "timescale.v"
56			`include "defines.v"
57	161	lampret
58	168	lampret	`module rf(`
59			`// Clock and reset`
60			`clk, rst,`
61	161	lampret
62	168	lampret	`// Write i/f`
63			`addrw, dataw, we,`
64
65			`// Read i/f`
66			`pipeline_freeze, addra, addrb, dataa, datab,`
67
68			`// Debug`
69			`rfa_tqa, rfb_tqa, rfa_tmuxed, rfb_tmuxed, tp1w`
70	161	lampret	`);`
71
72			parameter dw = `OPERAND_WIDTH;
73			parameter aw = `REGFILE_ADDR_WIDTH;
74
75	168	lampret	`//`
76			`// I/O`
77			`//`
78	161	lampret
79	168	lampret	`//`
80			`// Clock and reset`
81			`//`
82			`input clk;`
83			`input rst;`
84	161	lampret
85	168	lampret	`//`
86			`// Write i/f`
87			`//`
88			`input [aw-1:0] addrw;`
89			`input [dw-1:0] dataw;`
90			`input we;`
91	161	lampret
92	168	lampret	`//`
93			`// Read i/f`
94			`//`
95			`input pipeline_freeze;`
96			`input [aw-1:0] addra;`
97			`input [aw-1:0] addrb;`
98			`output [dw-1:0] dataa;`
99			`output [dw-1:0] datab;`
100	161	lampret
101	168	lampret	`//`
102			`// Debug`
103			`//`
104			`output [31:0] rfa_tqa;`
105			`output [31:0] rfb_tqa;`
106			output [`TP1R_WIDTH-1:0] rfa_tmuxed;
107			output [`TP1R_WIDTH-1:0] rfb_tmuxed;
108			input [`TP1W_WIDTH-1:0] tp1w;
109	161	lampret
110	168	lampret	`//`
111			`// Internal wires and regs`
112			`//`
113			`wire [dw-1:0] from_rfa;`
114			`wire [dw-1:0] from_rfb;`
115			`wire [dw-1:0] t_dataw; // for test port`
116			`wire [aw-1:0] t_addrw; // for test port`
117			`wire [aw-1:0] t_addra; // for test port`
118			`wire [aw-1:0] t_addrb; // for test port`
119			`reg [dw:0] dataa_saved;`
120			`reg [dw:0] datab_saved;`
121	161	lampret
122	168	lampret	`//`
123			`// Simple assignments`
124			`//`
125			`assign rfa_tqa = 32'b0;`
126			`assign rfb_tqa = 32'b0;`
127			assign rfa_tmuxed = `TP1R_WIDTH'b0;
128			assign rfb_tmuxed = `TP1R_WIDTH'b0;
129	161	lampret
130	168	lampret	`//`
131			`// Operand A comes from RF or from saved A register`
132			`//`
133	161	lampret	`assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;`
134	168	lampret
135			`//`
136			`// Operand B comes from RF or from saved B register`
137			`//`
138	161	lampret	`assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;`
139
140	168	lampret	`//`
141	161	lampret	`// Stores operand from RF_A into temp reg when pipeline is frozen`
142	168	lampret	`//`
143	161	lampret	`always @(posedge clk or posedge rst)`
144			`if (rst) begin`
145			`dataa_saved <= #1 33'b0;`
146			`end`
147			`else if (pipeline_freeze & !dataa_saved[32]) begin`
148			`dataa_saved <= #1 {1'b1, from_rfa};`
149			`end`
150			`else if (!pipeline_freeze)`
151			`dataa_saved[32] <= #1 1'b0;`
152
153	168	lampret	`//`
154	161	lampret	`// Stores operand from RF_B into temp reg when pipeline is frozen`
155	168	lampret	`//`
156	161	lampret	`always @(posedge clk or posedge rst)`
157			`if (rst) begin`
158			`datab_saved <= #1 33'b0;`
159			`end`
160			`else if (pipeline_freeze & !datab_saved[32]) begin`
161			`datab_saved <= #1 {1'b1, from_rfb};`
162			`end`
163			`else if (!pipeline_freeze)`
164			`datab_saved[32] <= #1 1'b0;`
165
166	168	lampret	`//`
167			`// Instantiation of register file dual-port RAM A`
168			`//`
169			`generic_dpram_32x32 rf_a(`
170			`// Port A`
171			`.clk_a(clk),`
172			`.rst_a(rst),`
173			`.ce_a(1'b1),`
174			`.oe_a(1'b1),`
175			`.addr_a(addra),`
176			`.do_a(from_rfa),`
177	161	lampret
178	168	lampret	`// Port B`
179			`.clk_b(clk),`
180			`.rst_b(rst),`
181			`.ce_b(we),`
182			`.we_b(we),`
183			`.addr_b(addrw),`
184			`.di_b(dataw)`
185	161	lampret	`);`
186
187	168	lampret	`//`
188			`// Instantiation of register file dual-port RAM B`
189			`//`
190			`generic_dpram_32x32 rf_b(`
191			`// Port A`
192			`.clk_a(clk),`
193			`.rst_a(rst),`
194			`.ce_a(1'b1),`
195			`.oe_a(1'b1),`
196			`.addr_a(addrb),`
197			`.do_a(from_rfb),`
198	161	lampret
199	168	lampret	`// Port B`
200			`.clk_b(clk),`
201			`.rst_b(rst),`
202			`.ce_b(we),`
203			`.we_b(we),`
204			`.addr_b(addrw),`
205			`.di_b(dataw)`
206	161	lampret	`);`
207
208			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [rf.v] - Blame information for rev 168