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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's register file inside CPU                           ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Instantiation of register file memories                     ////

////                                                              ////

////  To Do:                                                      ////

////   - make it smaller and faster                               ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.3  2001/08/09 13:39:33  lampret

// Major clean-up.

//

// Revision 1.2  2001/07/22 03:31:54  lampret

// Fixed RAM's oen bug. Cache bypass under development.

//

// Revision 1.1  2001/07/20 00:46:21  lampret

// Development version of RTL. Libraries are missing.

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "defines.v"

module rf(

        // Clock and reset

        clk, rst,

        // Write i/f

        addrw, dataw, we,

        // Read i/f

        id_freeze, addra, addrb, dataa, datab,

        // Debug

        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o

);

parameter dw = `OPERAND_WIDTH;

parameter aw = `REGFILE_ADDR_WIDTH;

//

// I/O

//

//

// Clock and reset

//

input                           clk;

input                           rst;

//

// Write i/f

//

input   [aw-1:0]         addrw;

input   [dw-1:0]         dataw;

input                           we;

//

// Read i/f

//

input                           id_freeze;

input   [aw-1:0]         addra;

input   [aw-1:0]         addrb;

output  [dw-1:0]         dataa;

output  [dw-1:0]         datab;

//

// SPR access for debugging purposes

//

input                           spr_cs;

input                           spr_write;

input   [31:0]                   spr_addr;

input   [31:0]                   spr_dat_i;

output  [31:0]                   spr_dat_o;

//

// Internal wires and regs

//

wire    [dw-1:0]         from_rfa;

wire    [dw-1:0]         from_rfb;

reg     [dw:0]                   dataa_saved;

reg     [dw:0]                   datab_saved;

wire    [aw-1:0]         rf_addra;

wire    [aw-1:0]         rf_addrw;

wire    [dw-1:0]         rf_dataw;

wire                            rf_we;

wire                            spr_valid;

//

// SPR access is valid when spr_cs is asserted and

// SPR address matches GPR addresses

//

assign spr_valid = spr_cs & (spr_addr[10:5] == `SPR_RF);

//

// SPR data output is always from RF A

//

assign spr_dat_o = from_rfa;

//

// Operand A comes from RF or from saved A register

//

assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;

//

// Operand B comes from RF or from saved B register

//

assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;

//

// RF A read address is either from SPRS or normal from CPU control

//

assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;

//

// RF write address is either from SPRS or normal from CPU control

//

assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;

//

// RF write data is either from SPRS or normal from CPU datapath

//

assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;

//

// RF write enable is either from SPRS or normal from CPU control

//

assign rf_we = (spr_valid & spr_write) | we;

//

// Stores operand from RF_A into temp reg when pipeline is frozen

//

always @(posedge clk or posedge rst)

        if (rst) begin

                dataa_saved <= #1 33'b0;

        end

        else if (id_freeze & !dataa_saved[32]) begin

                dataa_saved <= #1 {1'b1, from_rfa};

        end

        else if (!id_freeze)

                dataa_saved <= #1 33'b0;

//

// Stores operand from RF_B into temp reg when pipeline is frozen

//

always @(posedge clk or posedge rst)

        if (rst) begin

                datab_saved <= #1 33'b0;

        end

        else if (id_freeze & !datab_saved[32]) begin

                datab_saved <= #1 {1'b1, from_rfb};

        end

        else if (!id_freeze)

                datab_saved <= #1 33'b0;

//

// Instantiation of register file two-port RAM A

//

generic_tpram_32x32 rf_a(

        // Port A

        .clk_a(clk),

        .rst_a(rst),

        .ce_a(1'b1),

        .we_a(1'b0),

        .oe_a(1'b1),

        .addr_a(rf_addra),

        .di_a(32'h0000_0000),

        .do_a(from_rfa),

        // Port B

        .clk_b(clk),

        .rst_b(rst),

        .ce_b(rf_we),

        .we_b(rf_we),

        .oe_b(1'b0),

        .addr_b(rf_addrw),

        .di_b(rf_dataw),

        .do_b()

);

//

// Instantiation of register file two-port RAM B

//

generic_tpram_32x32 rf_b(

        // Port A

        .clk_a(clk),

        .rst_a(rst),

        .ce_a(1'b1),

        .we_a(1'b0),

        .oe_a(1'b1),

        .addr_a(addrb),

        .di_a(32'h0000_0000),

        .do_a(from_rfb),

        // Port B

        .clk_b(clk),

        .rst_b(rst),

        .ce_b(rf_we),

        .we_b(rf_we),

        .oe_b(1'b0),

        .addr_b(rf_addrw),

        .di_b(rf_dataw),

        .do_b()

);

endmodule