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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's register file inside CPU                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of register file memories                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.3  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/22 03:31:54  lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1  2001/07/20 00:46:21  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module rf(
        // Clock and reset
        clk, rst,
 
        // Write i/f
        addrw, dataw, we,
 
        // Read i/f
        id_freeze, addra, addrb, dataa, datab,
 
        // Debug
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OPERAND_WIDTH;
parameter aw = `REGFILE_ADDR_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Write i/f
//
input   [aw-1:0]         addrw;
input   [dw-1:0]         dataw;
input                           we;
 
//
// Read i/f
//
input                           id_freeze;
input   [aw-1:0]         addra;
input   [aw-1:0]         addrb;
output  [dw-1:0]         dataa;
output  [dw-1:0]         datab;
 
//
// SPR access for debugging purposes
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [dw-1:0]         from_rfa;
wire    [dw-1:0]         from_rfb;
reg     [dw:0]                   dataa_saved;
reg     [dw:0]                   datab_saved;
wire    [aw-1:0]         rf_addra;
wire    [aw-1:0]         rf_addrw;
wire    [dw-1:0]         rf_dataw;
wire                            rf_we;
wire                            spr_valid;
 
//
// SPR access is valid when spr_cs is asserted and
// SPR address matches GPR addresses
//
assign spr_valid = spr_cs & (spr_addr[10:5] == `SPR_RF);
 
//
// SPR data output is always from RF A
//
assign spr_dat_o = from_rfa;
 
//
// Operand A comes from RF or from saved A register
//
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
 
//
// Operand B comes from RF or from saved B register
//
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
 
//
// RF A read address is either from SPRS or normal from CPU control
//
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
 
//
// RF write address is either from SPRS or normal from CPU control
//
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
 
//
// RF write data is either from SPRS or normal from CPU datapath
//
assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
 
//
// RF write enable is either from SPRS or normal from CPU control
//
assign rf_we = (spr_valid & spr_write) | we;
 
//
// Stores operand from RF_A into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
        if (rst) begin
                dataa_saved <= #1 33'b0;
        end
        else if (id_freeze & !dataa_saved[32]) begin
                dataa_saved <= #1 {1'b1, from_rfa};
        end
        else if (!id_freeze)
                dataa_saved <= #1 33'b0;
 
//
// Stores operand from RF_B into temp reg when pipeline is frozen
//
always @(posedge clk or posedge rst)
        if (rst) begin
                datab_saved <= #1 33'b0;
        end
        else if (id_freeze & !datab_saved[32]) begin
                datab_saved <= #1 {1'b1, from_rfb};
        end
        else if (!id_freeze)
                datab_saved <= #1 33'b0;
 
//
// Instantiation of register file two-port RAM A
//
generic_dpram_32x32 rf_a(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(1'b1),
//      .we_a(1'b0),
        .oe_a(1'b1),
        .addr_a(rf_addra),
//      .di_a(32'h0000_0000),
        .do_a(from_rfa),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(rf_we),
        .we_b(rf_we),
//      .oe_b(1'b0),
        .addr_b(rf_addrw),
        .di_b(rf_dataw)
//      .do_b()
);
 
//
// Instantiation of register file two-port RAM B
//
generic_dpram_32x32 rf_b(
        // Port A
        .clk_a(clk),
        .rst_a(rst),
        .ce_a(1'b1),
//      .we_a(1'b0),
        .oe_a(1'b1),
        .addr_a(addrb),
//      .di_a(32'h0000_0000),
        .do_a(from_rfb),
 
        // Port B
        .clk_b(clk),
        .rst_b(rst),
        .ce_b(rf_we),
        .we_b(rf_we),
//      .oe_b(1'b0),
        .addr_b(rf_addrw),
        .di_b(rf_dataw)
//      .do_b()
);
 
endmodule

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [rf.v] - Blame information for rev 218

Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's register file inside CPU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of register file memories ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.8 2001/10/14 13:12:10 lampret`
48			`// MP3 version.`
49			`//`
50			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
51			`// no message`
52			`//`
53			`// Revision 1.3 2001/08/09 13:39:33 lampret`
54			`// Major clean-up.`
55			`//`
56			`// Revision 1.2 2001/07/22 03:31:54 lampret`
57			`// Fixed RAM's oen bug. Cache bypass under development.`
58			`//`
59			`// Revision 1.1 2001/07/20 00:46:21 lampret`
60			`// Development version of RTL. Libraries are missing.`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67			`include "defines.v"
68
69			`module rf(`
70			`// Clock and reset`
71			`clk, rst,`
72
73			`// Write i/f`
74			`addrw, dataw, we,`
75
76			`// Read i/f`
77			`id_freeze, addra, addrb, dataa, datab,`
78
79			`// Debug`
80			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
81			`);`
82
83			parameter dw = `OPERAND_WIDTH;
84			parameter aw = `REGFILE_ADDR_WIDTH;
85
86			`//`
87			`// I/O`
88			`//`
89
90			`//`
91			`// Clock and reset`
92			`//`
93			`input clk;`
94			`input rst;`
95
96			`//`
97			`// Write i/f`
98			`//`
99			`input [aw-1:0] addrw;`
100			`input [dw-1:0] dataw;`
101			`input we;`
102
103			`//`
104			`// Read i/f`
105			`//`
106			`input id_freeze;`
107			`input [aw-1:0] addra;`
108			`input [aw-1:0] addrb;`
109			`output [dw-1:0] dataa;`
110			`output [dw-1:0] datab;`
111
112			`//`
113			`// SPR access for debugging purposes`
114			`//`
115			`input spr_cs;`
116			`input spr_write;`
117			`input [31:0] spr_addr;`
118			`input [31:0] spr_dat_i;`
119			`output [31:0] spr_dat_o;`
120
121			`//`
122			`// Internal wires and regs`
123			`//`
124			`wire [dw-1:0] from_rfa;`
125			`wire [dw-1:0] from_rfb;`
126			`reg [dw:0] dataa_saved;`
127			`reg [dw:0] datab_saved;`
128			`wire [aw-1:0] rf_addra;`
129			`wire [aw-1:0] rf_addrw;`
130			`wire [dw-1:0] rf_dataw;`
131			`wire rf_we;`
132			`wire spr_valid;`
133
134			`//`
135			`// SPR access is valid when spr_cs is asserted and`
136			`// SPR address matches GPR addresses`
137			`//`
138			assign spr_valid = spr_cs & (spr_addr[10:5] == `SPR_RF);
139
140			`//`
141			`// SPR data output is always from RF A`
142			`//`
143			`assign spr_dat_o = from_rfa;`
144
145			`//`
146			`// Operand A comes from RF or from saved A register`
147			`//`
148			`assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;`
149
150			`//`
151			`// Operand B comes from RF or from saved B register`
152			`//`
153			`assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;`
154
155			`//`
156			`// RF A read address is either from SPRS or normal from CPU control`
157			`//`
158			`assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;`
159
160			`//`
161			`// RF write address is either from SPRS or normal from CPU control`
162			`//`
163			`assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;`
164
165			`//`
166			`// RF write data is either from SPRS or normal from CPU datapath`
167			`//`
168			`assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;`
169
170			`//`
171			`// RF write enable is either from SPRS or normal from CPU control`
172			`//`
173			`assign rf_we = (spr_valid & spr_write) \| we;`
174
175			`//`
176			`// Stores operand from RF_A into temp reg when pipeline is frozen`
177			`//`
178			`always @(posedge clk or posedge rst)`
179			`if (rst) begin`
180			`dataa_saved <= #1 33'b0;`
181			`end`
182			`else if (id_freeze & !dataa_saved[32]) begin`
183			`dataa_saved <= #1 {1'b1, from_rfa};`
184			`end`
185			`else if (!id_freeze)`
186			`dataa_saved <= #1 33'b0;`
187
188			`//`
189			`// Stores operand from RF_B into temp reg when pipeline is frozen`
190			`//`
191			`always @(posedge clk or posedge rst)`
192			`if (rst) begin`
193			`datab_saved <= #1 33'b0;`
194			`end`
195			`else if (id_freeze & !datab_saved[32]) begin`
196			`datab_saved <= #1 {1'b1, from_rfb};`
197			`end`
198			`else if (!id_freeze)`
199			`datab_saved <= #1 33'b0;`
200
201			`//`
202			`// Instantiation of register file two-port RAM A`
203			`//`
204			`generic_dpram_32x32 rf_a(`
205			`// Port A`
206			`.clk_a(clk),`
207			`.rst_a(rst),`
208			`.ce_a(1'b1),`
209			`// .we_a(1'b0),`
210			`.oe_a(1'b1),`
211			`.addr_a(rf_addra),`
212			`// .di_a(32'h0000_0000),`
213			`.do_a(from_rfa),`
214
215			`// Port B`
216			`.clk_b(clk),`
217			`.rst_b(rst),`
218			`.ce_b(rf_we),`
219			`.we_b(rf_we),`
220			`// .oe_b(1'b0),`
221			`.addr_b(rf_addrw),`
222			`.di_b(rf_dataw)`
223			`// .do_b()`
224			`);`
225
226			`//`
227			`// Instantiation of register file two-port RAM B`
228			`//`
229			`generic_dpram_32x32 rf_b(`
230			`// Port A`
231			`.clk_a(clk),`
232			`.rst_a(rst),`
233			`.ce_a(1'b1),`
234			`// .we_a(1'b0),`
235			`.oe_a(1'b1),`
236			`.addr_a(addrb),`
237			`// .di_a(32'h0000_0000),`
238			`.do_a(from_rfb),`
239
240			`// Port B`
241			`.clk_b(clk),`
242			`.rst_b(rst),`
243			`.ce_b(rf_we),`
244			`.we_b(rf_we),`
245			`// .oe_b(1'b0),`
246			`.addr_b(rf_addrw),`
247			`.di_b(rf_dataw)`
248			`// .do_b()`
249			`);`
250
251			`endmodule`