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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Tick Timer                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  TT according to OR1K architectural specification.           ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`include "general.h"
 
module tt(
        // RISC Internal Interface
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        int
);
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          int;            // Interrupt output
 
`ifdef TT_IMPLEMENTED
 
//
// TT Mode Register bits (or no register)
//
`ifdef TT_TTMR
reg     [31:0]   ttmr;   // TTMR bits
`else
wire    [31:0]   ttmr;   // No TTMR register
`endif
 
//
// TT Count Register bits (or no register)
//
`ifdef TT_TTCR
reg     [31:0]   ttcr;   // TTCR bits
`else
wire    [31:0]   ttcr;   // No TTCR register
`endif
 
//
// Internal wires & regs
//
wire            ttmr_sel;       // TTMR select
wire            ttcr_sel;       // TTCR select
wire            match;          // Asserted when TTMR[TP]
                                // is equal to TTCR[27:0]
wire            restart;        // Restart counter when asserted
wire            stop;           // Stop counter when asserted
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// TT registers address decoder
//
assign ttmr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTCR)) ? 1'b1 : 1'b0;
 
//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef TT_TTMR
always @(posedge clk or posedge rst)
        if (rst)
                ttmr <= 32'b0;
        else if (ttmr_sel && spr_write)
                ttmr <= #1 spr_dat_i;
        else if (ttmr[`TT_TTMR_IE])
                ttmr[`TT_TTMR_IP] <= #1 ttmr[`TT_TTMR_IP] | int;
`else
assign ttmr = {2'b11, 30'b0};    // TTMR[M] = 0x3
`endif
 
//
// Write to or increment of TTCR
//
`ifdef TT_TTCR
always @(posedge clk or posedge restart)
        if (restart)
                ttcr <= 32'b0;
        else if (ttcr_sel && spr_write)
                ttcr <= #1 spr_dat_i;
        else if (!stop)
                ttcr <= #1 ttcr + 1'd1;
`else
assign ttcr = 32'b0;
`endif
 
//
// Read TT registers
//
always @(spr_addr or ttmr or ttmr_sel or ttcr or ttcr_sel)
        case (spr_addr[`TTOFS_BITS])    // synopsys full_case parallel_case
`ifdef TT_READREGS
                `TT_OFS_TTMR: spr_dat_o <= ttmr;
`endif
                default: spr_dat_o <= ttcr;
        endcase
 
//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
assign match = (ttmr[`TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
 
//
// Restart when match and TTMR[M]==0x1 or when rst is asserted
//
assign restart = (match && (ttmr[`TT_TTMR_M] == 2'b01) || rst) ? 1'b1 : 1'b0;
 
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0
//
assign stop = (match && (ttmr[`TT_TTMR_M] == 2'b10) || (ttmr[`TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0;
 
//
// Generate an interrupt request
//
assign int = match & ttmr[`TT_TTMR_IE];
 
`else
 
//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign int = 1'b0;
 
//
// Read TT registers
//
`ifdef TT_READREGS
assign spr_dat_o = 32'b0;
`endif
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Tick Timer ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// TT according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48
49			`include "general.h"
50
51			`module tt(`
52			`// RISC Internal Interface`
53			`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
54			`int`
55			`);`
56
57			`//`
58			`// RISC Internal Interface`
59			`//`
60			`input clk; // Clock`
61			`input rst; // Reset`
62			`input spr_cs; // SPR CS`
63			`input spr_write; // SPR Write`
64			`input [31:0] spr_addr; // SPR Address`
65			`input [31:0] spr_dat_i; // SPR Write Data`
66			`output [31:0] spr_dat_o; // SPR Read Data`
67			`output int; // Interrupt output`
68
69			`ifdef TT_IMPLEMENTED
70
71			`//`
72			`// TT Mode Register bits (or no register)`
73			`//`
74			`ifdef TT_TTMR
75			`reg [31:0] ttmr; // TTMR bits`
76			`else
77			`wire [31:0] ttmr; // No TTMR register`
78			`endif
79
80			`//`
81			`// TT Count Register bits (or no register)`
82			`//`
83			`ifdef TT_TTCR
84			`reg [31:0] ttcr; // TTCR bits`
85			`else
86			`wire [31:0] ttcr; // No TTCR register`
87			`endif
88
89			`//`
90			`// Internal wires & regs`
91			`//`
92			`wire ttmr_sel; // TTMR select`
93			`wire ttcr_sel; // TTCR select`
94			`wire match; // Asserted when TTMR[TP]`
95			`// is equal to TTCR[27:0]`
96			`wire restart; // Restart counter when asserted`
97			`wire stop; // Stop counter when asserted`
98			`reg [31:0] spr_dat_o; // SPR data out`
99
100			`//`
101			`// TT registers address decoder`
102			`//`
103			assign ttmr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTMR)) ? 1'b1 : 1'b0;
104			assign ttcr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTCR)) ? 1'b1 : 1'b0;
105
106			`//`
107			`// Write to TTMR or update of TTMR[IP] bit`
108			`//`
109			`ifdef TT_TTMR
110			`always @(posedge clk or posedge rst)`
111			`if (rst)`
112			`ttmr <= 32'b0;`
113			`else if (ttmr_sel && spr_write)`
114			`ttmr <= #1 spr_dat_i;`
115			else if (ttmr[`TT_TTMR_IE])
116			ttmr[`TT_TTMR_IP] <= #1 ttmr[`TT_TTMR_IP] \| int;
117			`else
118			`assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3`
119			`endif
120
121			`//`
122			`// Write to or increment of TTCR`
123			`//`
124			`ifdef TT_TTCR
125			`always @(posedge clk or posedge restart)`
126			`if (restart)`
127			`ttcr <= 32'b0;`
128			`else if (ttcr_sel && spr_write)`
129			`ttcr <= #1 spr_dat_i;`
130			`else if (!stop)`
131			`ttcr <= #1 ttcr + 1'd1;`
132			`else
133			`assign ttcr = 32'b0;`
134			`endif
135
136			`//`
137			`// Read TT registers`
138			`//`
139			`always @(spr_addr or ttmr or ttmr_sel or ttcr or ttcr_sel)`
140			case (spr_addr[`TTOFS_BITS]) // synopsys full_case parallel_case
141			`ifdef TT_READREGS
142			`TT_OFS_TTMR: spr_dat_o <= ttmr;
143			`endif
144			`default: spr_dat_o <= ttcr;`
145			`endcase`
146
147			`//`
148			`// A match when TTMR[TP] is equal to TTCR[27:0]`
149			`//`
150			assign match = (ttmr[`TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
151
152			`//`
153			`// Restart when match and TTMR[M]==0x1 or when rst is asserted`
154			`//`
155			assign restart = (match && (ttmr[`TT_TTMR_M] == 2'b01) \|\| rst) ? 1'b1 : 1'b0;
156
157			`//`
158			`// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0`
159			`//`
160			assign stop = (match && (ttmr[`TT_TTMR_M] == 2'b10) \|\| (ttmr[`TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0;
161
162			`//`
163			`// Generate an interrupt request`
164			`//`
165			assign int = match & ttmr[`TT_TTMR_IE];
166
167			`else
168
169			`//`
170			`// When TT is not implemented, drive all outputs as would when TT is disabled`
171			`//`
172			`assign int = 1'b0;`
173
174			`//`
175			`// Read TT registers`
176			`//`
177			`ifdef TT_READREGS
178			`assign spr_dat_o = 32'b0;`
179			`endif
180
181			`endif
182
183			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [tt.v] - Blame information for rev 161