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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Tick Timer                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  TT according to OR1K architectural specification.           ////
////                                                              ////
////  To Do:                                                      ////
////   None                                                       ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:23  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
module tt(
        // RISC Internal Interface
        clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
        int
);
 
//
// RISC Internal Interface
//
input           clk;            // Clock
input           rst;            // Reset
input           spr_cs;         // SPR CS
input           spr_write;      // SPR Write
input   [31:0]   spr_addr;       // SPR Address
input   [31:0]   spr_dat_i;      // SPR Write Data
output  [31:0]   spr_dat_o;      // SPR Read Data
output          int;            // Interrupt output
 
`ifdef TT_IMPLEMENTED
 
//
// TT Mode Register bits (or no register)
//
`ifdef TT_TTMR
reg     [31:0]   ttmr;   // TTMR bits
`else
wire    [31:0]   ttmr;   // No TTMR register
`endif
 
//
// TT Count Register bits (or no register)
//
`ifdef TT_TTCR
reg     [31:0]   ttcr;   // TTCR bits
`else
wire    [31:0]   ttcr;   // No TTCR register
`endif
 
//
// Internal wires & regs
//
wire            ttmr_sel;       // TTMR select
wire            ttcr_sel;       // TTCR select
wire            match;          // Asserted when TTMR[TP]
                                // is equal to TTCR[27:0]
wire            restart;        // Restart counter when asserted
wire            stop;           // Stop counter when asserted
reg     [31:0]   spr_dat_o;      // SPR data out
 
//
// TT registers address decoder
//
assign ttmr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTMR)) ? 1'b1 : 1'b0;
assign ttcr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTCR)) ? 1'b1 : 1'b0;
 
//
// Write to TTMR or update of TTMR[IP] bit
//
`ifdef TT_TTMR
always @(posedge clk or posedge rst)
        if (rst)
                ttmr <= 32'b0;
        else if (ttmr_sel && spr_write)
                ttmr <= #1 spr_dat_i;
        else if (ttmr[`TT_TTMR_IE])
                ttmr[`TT_TTMR_IP] <= #1 ttmr[`TT_TTMR_IP] | int;
`else
assign ttmr = {2'b11, 30'b0};    // TTMR[M] = 0x3
`endif
 
//
// Write to or increment of TTCR
//
`ifdef TT_TTCR
always @(posedge clk or posedge restart)
        if (restart)
                ttcr <= 32'b0;
        else if (ttcr_sel && spr_write)
                ttcr <= #1 spr_dat_i;
        else if (!stop)
                ttcr <= #1 ttcr + 1'd1;
`else
assign ttcr = 32'b0;
`endif
 
//
// Read TT registers
//
always @(spr_addr or ttmr or ttmr_sel or ttcr or ttcr_sel)
        case (spr_addr[`TTOFS_BITS])    // synopsys full_case parallel_case
`ifdef TT_READREGS
                `TT_OFS_TTMR: spr_dat_o <= ttmr;
`endif
                default: spr_dat_o <= ttcr;
        endcase
 
//
// A match when TTMR[TP] is equal to TTCR[27:0]
//
assign match = (ttmr[`TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
 
//
// Restart when match and TTMR[M]==0x1 or when rst is asserted
//
assign restart = (match && (ttmr[`TT_TTMR_M] == 2'b01) || rst) ? 1'b1 : 1'b0;
 
//
// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0
//
assign stop = (match && (ttmr[`TT_TTMR_M] == 2'b10) || (ttmr[`TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0;
 
//
// Generate an interrupt request
//
assign int = match & ttmr[`TT_TTMR_IE];
 
`else
 
//
// When TT is not implemented, drive all outputs as would when TT is disabled
//
assign int = 1'b0;
 
//
// Read TT registers
//
`ifdef TT_READREGS
assign spr_dat_o = 32'b0;
`endif
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	161	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Tick Timer ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// TT according to OR1K architectural specification. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// None ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.2 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49			`//`
50	168	lampret	`// Revision 1.1 2001/07/20 00:46:23 lampret`
51			`// Development version of RTL. Libraries are missing.`
52	161	lampret	`//`
53	168	lampret	`//`
54	161	lampret
55	203	lampret	`// synopsys translate_off`
56	168	lampret	`include "timescale.v"
57	203	lampret	`// synopsys translate_on`
58	168	lampret	`include "defines.v"
59	161	lampret
60			`module tt(`
61			`// RISC Internal Interface`
62			`clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
63			`int`
64			`);`
65
66			`//`
67			`// RISC Internal Interface`
68			`//`
69			`input clk; // Clock`
70			`input rst; // Reset`
71			`input spr_cs; // SPR CS`
72			`input spr_write; // SPR Write`
73			`input [31:0] spr_addr; // SPR Address`
74			`input [31:0] spr_dat_i; // SPR Write Data`
75			`output [31:0] spr_dat_o; // SPR Read Data`
76			`output int; // Interrupt output`
77
78			`ifdef TT_IMPLEMENTED
79
80			`//`
81			`// TT Mode Register bits (or no register)`
82			`//`
83			`ifdef TT_TTMR
84			`reg [31:0] ttmr; // TTMR bits`
85			`else
86			`wire [31:0] ttmr; // No TTMR register`
87			`endif
88
89			`//`
90			`// TT Count Register bits (or no register)`
91			`//`
92			`ifdef TT_TTCR
93			`reg [31:0] ttcr; // TTCR bits`
94			`else
95			`wire [31:0] ttcr; // No TTCR register`
96			`endif
97
98			`//`
99			`// Internal wires & regs`
100			`//`
101			`wire ttmr_sel; // TTMR select`
102			`wire ttcr_sel; // TTCR select`
103			`wire match; // Asserted when TTMR[TP]`
104			`// is equal to TTCR[27:0]`
105			`wire restart; // Restart counter when asserted`
106			`wire stop; // Stop counter when asserted`
107			`reg [31:0] spr_dat_o; // SPR data out`
108
109			`//`
110			`// TT registers address decoder`
111			`//`
112			assign ttmr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTMR)) ? 1'b1 : 1'b0;
113			assign ttcr_sel = (spr_cs && (spr_addr[`TTOFS_BITS] == `TT_OFS_TTCR)) ? 1'b1 : 1'b0;
114
115			`//`
116			`// Write to TTMR or update of TTMR[IP] bit`
117			`//`
118			`ifdef TT_TTMR
119			`always @(posedge clk or posedge rst)`
120			`if (rst)`
121			`ttmr <= 32'b0;`
122			`else if (ttmr_sel && spr_write)`
123			`ttmr <= #1 spr_dat_i;`
124			else if (ttmr[`TT_TTMR_IE])
125			ttmr[`TT_TTMR_IP] <= #1 ttmr[`TT_TTMR_IP] \| int;
126			`else
127			`assign ttmr = {2'b11, 30'b0}; // TTMR[M] = 0x3`
128			`endif
129
130			`//`
131			`// Write to or increment of TTCR`
132			`//`
133			`ifdef TT_TTCR
134			`always @(posedge clk or posedge restart)`
135			`if (restart)`
136			`ttcr <= 32'b0;`
137			`else if (ttcr_sel && spr_write)`
138			`ttcr <= #1 spr_dat_i;`
139			`else if (!stop)`
140			`ttcr <= #1 ttcr + 1'd1;`
141			`else
142			`assign ttcr = 32'b0;`
143			`endif
144
145			`//`
146			`// Read TT registers`
147			`//`
148			`always @(spr_addr or ttmr or ttmr_sel or ttcr or ttcr_sel)`
149			case (spr_addr[`TTOFS_BITS]) // synopsys full_case parallel_case
150			`ifdef TT_READREGS
151			`TT_OFS_TTMR: spr_dat_o <= ttmr;
152			`endif
153			`default: spr_dat_o <= ttcr;`
154			`endcase`
155
156			`//`
157			`// A match when TTMR[TP] is equal to TTCR[27:0]`
158			`//`
159			assign match = (ttmr[`TT_TTMR_TP] == ttcr[27:0]) ? 1'b1 : 1'b0;
160
161			`//`
162			`// Restart when match and TTMR[M]==0x1 or when rst is asserted`
163			`//`
164			assign restart = (match && (ttmr[`TT_TTMR_M] == 2'b01) \|\| rst) ? 1'b1 : 1'b0;
165
166			`//`
167			`// Stop when match and TTMR[M]==0x2 or when TTMR[M]==0x0`
168			`//`
169			assign stop = (match && (ttmr[`TT_TTMR_M] == 2'b10) \|\| (ttmr[`TT_TTMR_M] == 2'b00)) ? 1'b1 : 1'b0;
170
171			`//`
172			`// Generate an interrupt request`
173			`//`
174			assign int = match & ttmr[`TT_TTMR_IE];
175
176			`else
177
178			`//`
179			`// When TT is not implemented, drive all outputs as would when TT is disabled`
180			`//`
181			`assign int = 1'b0;`
182
183			`//`
184			`// Read TT registers`
185			`//`
186			`ifdef TT_READREGS
187			`assign spr_dat_o = 32'b0;`
188			`endif
189
190			`endif
191
192			`endmodule`

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [tt.v] - Blame information for rev 203