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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  OR1200's WISHBONE BIU                                       ////

////                                                              ////

////  This file is part of the OpenRISC 1200 project              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  Implements WISHBONE interface                               ////

////                                                              ////

////  To Do:                                                      ////

////   - add support for wb_err_i                                 ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.3  2001/08/09 13:39:33  lampret

// Major clean-up.

//

// Revision 1.2  2001/07/22 03:31:54  lampret

// Fixed RAM's oen bug. Cache bypass under development.

//

// Revision 1.1  2001/07/20 00:46:23  lampret

// Development version of RTL. Libraries are missing.

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "defines.v"

module wb_biu(

        // WISHBONE interface

        wb_clk_i, wb_rst_i, wb_ack_i, wb_err_i, wb_rty_i, wb_dat_i,

        wb_cyc_o, wb_adr_o, wb_stb_o, wb_we_o, wb_sel_o, wb_dat_o,

        // Internal RISC bus

        biu_to_biu, biu_addr, biu_read, biu_write, biu_rdy, biu_from_biu, biu_sel

);

parameter dw = `OPERAND_WIDTH;

parameter aw = `OPERAND_WIDTH;

//

// WISHBONE interface

//

input                   wb_clk_i;       // clock input

input                   wb_rst_i;       // reset input

input                   wb_ack_i;       // normal termination

input                   wb_err_i;       // termination w/ error

input                   wb_rty_i;       // termination w/ retry

input   [dw-1:0] wb_dat_i;       // input data bus

output                  wb_cyc_o;       // cycle valid output

output  [aw-1:0] wb_adr_o;       // address bus outputs

output                  wb_stb_o;       // strobe output

output                  wb_we_o;        // indicates write transfer

output  [3:0]            wb_sel_o;       // byte select outputs

output  [dw-1:0] wb_dat_o;       // output data bus

//

// Internal RISC interface

//

input   [dw-1:0] biu_to_biu;     // input data bus

input   [aw-1:0] biu_addr;       // address bus

input                   biu_read;       // read request

input                   biu_write;      // write request

output                  biu_rdy;        // data valid

output  [dw-1:0] biu_from_biu;   // output data bus

input   [3:0]            biu_sel;        // byte select inputs

//

// Registers

//

`ifdef OR1200_REGISTERED_OUTPUTS

reg     [aw-1:0] wb_adr_o;       // address bus outputs

reg                     wb_stb_o;       // strobe output

reg                     wb_we_o;        // indicates write transfer

reg     [3:0]            wb_sel_o;       // byte select outputs

reg     [dw-1:0] wb_dat_o;       // output data bus

`endif

//

// WISHBONE I/F <-> Internal RISC I/F conversion

//

//

// Address bus

//

`ifdef OR1200_REGISTERED_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

                wb_adr_o <= #1 {aw{1'b0}};

        else

                wb_adr_o <= #1 biu_addr;

`else

assign wb_adr_o = biu_addr;

`endif

//

// Input data bus

//

assign biu_from_biu = wb_dat_i;

//

// Output data bus

//

`ifdef OR1200_REGISTERED_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

                wb_dat_o <= #1 {dw{1'b0}};

        else

                wb_dat_o <= #1 biu_to_biu;

`else

assign wb_dat_o = biu_to_biu;

`endif

//

// Acknowledgment of the data to the RISC

//

assign biu_rdy = wb_ack_i;

//

// WB cyc_o

//

assign wb_cyc_o = wb_stb_o;

//

// WB stb_o

//

`ifdef OR1200_REGISTERED_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

                wb_stb_o <= #1 1'b0;

        else

                wb_stb_o <= #1 (biu_read | biu_write);

`else

assign wb_stb_o = (biu_read | biu_write);

`endif

//

// WB we_o

//

`ifdef OR1200_REGISTERED_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

                wb_we_o <= #1 1'b0;

        else

                wb_we_o <= #1 biu_write;

`else

assign wb_we_o = biu_write;

`endif

//

// WB sel_o

//

`ifdef OR1200_REGISTERED_OUTPUTS

always @(posedge wb_clk_i or posedge wb_rst_i)

        if (wb_rst_i)

                wb_sel_o <= #1 4'b0000;

        else

                wb_sel_o <= #1 biu_sel;

`else

assign wb_sel_o = biu_sel;

`endif

endmodule