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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Xilinx Virtex RAM 32x8D                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Virtex dual-port memory                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
`ifdef XILINX_RAM32X1D
 
module xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
// I/O
//
output [7:0]     DPO;
output [7:0]     SPO;
input [4:0]      A;
input [4:0]      DPRA;
input [7:0]      D;
input           WCLK;
input           WE;
 
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
        .DPO(DPO[0]),
        .SPO(SPO[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
        .DPO(DPO[1]),
        .SPO(SPO[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
        .DPO(DPO[2]),
        .SPO(SPO[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
        .DPO(DPO[3]),
        .SPO(SPO[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
        .DPO(DPO[4]),
        .SPO(SPO[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
        .DPO(DPO[5]),
        .SPO(SPO[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
        .DPO(DPO[6]),
        .SPO(SPO[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
        .DPO(DPO[7]),
        .SPO(SPO[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
endmodule
 
`endif

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [xcv_ram32x8d.v] - Blame information for rev 168

Line No.	Rev	Author	Line
1	168	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Xilinx Virtex RAM 32x8D ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Virtex dual-port memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48
49			`ifdef XILINX_RAM32X1D
50
51			`module xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`
52
53			`//`
54			`// I/O`
55			`//`
56			`output [7:0] DPO;`
57			`output [7:0] SPO;`
58			`input [4:0] A;`
59			`input [4:0] DPRA;`
60			`input [7:0] D;`
61			`input WCLK;`
62			`input WE;`
63
64			`//`
65			`// Instantiation of block 0`
66			`//`
67			`RAM32X1D ram32x1d_0(`
68			`.DPO(DPO[0]),`
69			`.SPO(SPO[0]),`
70			`.A0(A[0]),`
71			`.A1(A[1]),`
72			`.A2(A[2]),`
73			`.A3(A[3]),`
74			`.A4(A[4]),`
75			`.D(D[0]),`
76			`.DPRA0(DPRA[0]),`
77			`.DPRA1(DPRA[1]),`
78			`.DPRA2(DPRA[2]),`
79			`.DPRA3(DPRA[3]),`
80			`.DPRA4(DPRA[4]),`
81			`.WCLK(WCLK),`
82			`.WE(WE)`
83			`);`
84
85			`//`
86			`// Instantiation of block 1`
87			`//`
88			`RAM32X1D ram32x1d_1(`
89			`.DPO(DPO[1]),`
90			`.SPO(SPO[1]),`
91			`.A0(A[0]),`
92			`.A1(A[1]),`
93			`.A2(A[2]),`
94			`.A3(A[3]),`
95			`.A4(A[4]),`
96			`.D(D[1]),`
97			`.DPRA0(DPRA[0]),`
98			`.DPRA1(DPRA[1]),`
99			`.DPRA2(DPRA[2]),`
100			`.DPRA3(DPRA[3]),`
101			`.DPRA4(DPRA[4]),`
102			`.WCLK(WCLK),`
103			`.WE(WE)`
104			`);`
105
106			`//`
107			`// Instantiation of block 2`
108			`//`
109			`RAM32X1D ram32x1d_2(`
110			`.DPO(DPO[2]),`
111			`.SPO(SPO[2]),`
112			`.A0(A[0]),`
113			`.A1(A[1]),`
114			`.A2(A[2]),`
115			`.A3(A[3]),`
116			`.A4(A[4]),`
117			`.D(D[2]),`
118			`.DPRA0(DPRA[0]),`
119			`.DPRA1(DPRA[1]),`
120			`.DPRA2(DPRA[2]),`
121			`.DPRA3(DPRA[3]),`
122			`.DPRA4(DPRA[4]),`
123			`.WCLK(WCLK),`
124			`.WE(WE)`
125			`);`
126
127			`//`
128			`// Instantiation of block 3`
129			`//`
130			`RAM32X1D ram32x1d_3(`
131			`.DPO(DPO[3]),`
132			`.SPO(SPO[3]),`
133			`.A0(A[0]),`
134			`.A1(A[1]),`
135			`.A2(A[2]),`
136			`.A3(A[3]),`
137			`.A4(A[4]),`
138			`.D(D[3]),`
139			`.DPRA0(DPRA[0]),`
140			`.DPRA1(DPRA[1]),`
141			`.DPRA2(DPRA[2]),`
142			`.DPRA3(DPRA[3]),`
143			`.DPRA4(DPRA[4]),`
144			`.WCLK(WCLK),`
145			`.WE(WE)`
146			`);`
147
148			`//`
149			`// Instantiation of block 4`
150			`//`
151			`RAM32X1D ram32x1d_4(`
152			`.DPO(DPO[4]),`
153			`.SPO(SPO[4]),`
154			`.A0(A[0]),`
155			`.A1(A[1]),`
156			`.A2(A[2]),`
157			`.A3(A[3]),`
158			`.A4(A[4]),`
159			`.D(D[4]),`
160			`.DPRA0(DPRA[0]),`
161			`.DPRA1(DPRA[1]),`
162			`.DPRA2(DPRA[2]),`
163			`.DPRA3(DPRA[3]),`
164			`.DPRA4(DPRA[4]),`
165			`.WCLK(WCLK),`
166			`.WE(WE)`
167			`);`
168
169			`//`
170			`// Instantiation of block 5`
171			`//`
172			`RAM32X1D ram32x1d_5(`
173			`.DPO(DPO[5]),`
174			`.SPO(SPO[5]),`
175			`.A0(A[0]),`
176			`.A1(A[1]),`
177			`.A2(A[2]),`
178			`.A3(A[3]),`
179			`.A4(A[4]),`
180			`.D(D[5]),`
181			`.DPRA0(DPRA[0]),`
182			`.DPRA1(DPRA[1]),`
183			`.DPRA2(DPRA[2]),`
184			`.DPRA3(DPRA[3]),`
185			`.DPRA4(DPRA[4]),`
186			`.WCLK(WCLK),`
187			`.WE(WE)`
188			`);`
189
190			`//`
191			`// Instantiation of block 6`
192			`//`
193			`RAM32X1D ram32x1d_6(`
194			`.DPO(DPO[6]),`
195			`.SPO(SPO[6]),`
196			`.A0(A[0]),`
197			`.A1(A[1]),`
198			`.A2(A[2]),`
199			`.A3(A[3]),`
200			`.A4(A[4]),`
201			`.D(D[6]),`
202			`.DPRA0(DPRA[0]),`
203			`.DPRA1(DPRA[1]),`
204			`.DPRA2(DPRA[2]),`
205			`.DPRA3(DPRA[3]),`
206			`.DPRA4(DPRA[4]),`
207			`.WCLK(WCLK),`
208			`.WE(WE)`
209			`);`
210
211			`//`
212			`// Instantiation of block 7`
213			`//`
214			`RAM32X1D ram32x1d_7(`
215			`.DPO(DPO[7]),`
216			`.SPO(SPO[7]),`
217			`.A0(A[0]),`
218			`.A1(A[1]),`
219			`.A2(A[2]),`
220			`.A3(A[3]),`
221			`.A4(A[4]),`
222			`.D(D[7]),`
223			`.DPRA0(DPRA[0]),`
224			`.DPRA1(DPRA[1]),`
225			`.DPRA2(DPRA[2]),`
226			`.DPRA3(DPRA[3]),`
227			`.DPRA4(DPRA[4]),`
228			`.WCLK(WCLK),`
229			`.WE(WE)`
230			`);`
231
232			`endmodule`
233
234			`endif