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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Xilinx Virtex RAM 32x8D                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Virtex dual-port memory                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`ifdef XILINX_RAM32X1D
 
module xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
// I/O
//
output [7:0]     DPO;
output [7:0]     SPO;
input [4:0]      A;
input [4:0]      DPRA;
input [7:0]      D;
input           WCLK;
input           WE;
 
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
        .DPO(DPO[0]),
        .SPO(SPO[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
        .DPO(DPO[1]),
        .SPO(SPO[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
        .DPO(DPO[2]),
        .SPO(SPO[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
        .DPO(DPO[3]),
        .SPO(SPO[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
        .DPO(DPO[4]),
        .SPO(SPO[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
        .DPO(DPO[5]),
        .SPO(SPO[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
        .DPO(DPO[6]),
        .SPO(SPO[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
        .DPO(DPO[7]),
        .SPO(SPO[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
endmodule
 
`endif

Line No.	Rev	Author	Line
1	168	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Xilinx Virtex RAM 32x8D ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Virtex dual-port memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	203	lampret	`// Revision 1.1 2001/08/09 13:39:33 lampret`
48			`// Major clean-up.`
49	168	lampret	`//`
50	203	lampret	`//`
51	168	lampret
52	203	lampret	`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55			`include "defines.v"
56
57	168	lampret	`ifdef XILINX_RAM32X1D
58
59			`module xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`
60
61			`//`
62			`// I/O`
63			`//`
64			`output [7:0] DPO;`
65			`output [7:0] SPO;`
66			`input [4:0] A;`
67			`input [4:0] DPRA;`
68			`input [7:0] D;`
69			`input WCLK;`
70			`input WE;`
71
72			`//`
73			`// Instantiation of block 0`
74			`//`
75			`RAM32X1D ram32x1d_0(`
76			`.DPO(DPO[0]),`
77			`.SPO(SPO[0]),`
78			`.A0(A[0]),`
79			`.A1(A[1]),`
80			`.A2(A[2]),`
81			`.A3(A[3]),`
82			`.A4(A[4]),`
83			`.D(D[0]),`
84			`.DPRA0(DPRA[0]),`
85			`.DPRA1(DPRA[1]),`
86			`.DPRA2(DPRA[2]),`
87			`.DPRA3(DPRA[3]),`
88			`.DPRA4(DPRA[4]),`
89			`.WCLK(WCLK),`
90			`.WE(WE)`
91			`);`
92
93			`//`
94			`// Instantiation of block 1`
95			`//`
96			`RAM32X1D ram32x1d_1(`
97			`.DPO(DPO[1]),`
98			`.SPO(SPO[1]),`
99			`.A0(A[0]),`
100			`.A1(A[1]),`
101			`.A2(A[2]),`
102			`.A3(A[3]),`
103			`.A4(A[4]),`
104			`.D(D[1]),`
105			`.DPRA0(DPRA[0]),`
106			`.DPRA1(DPRA[1]),`
107			`.DPRA2(DPRA[2]),`
108			`.DPRA3(DPRA[3]),`
109			`.DPRA4(DPRA[4]),`
110			`.WCLK(WCLK),`
111			`.WE(WE)`
112			`);`
113
114			`//`
115			`// Instantiation of block 2`
116			`//`
117			`RAM32X1D ram32x1d_2(`
118			`.DPO(DPO[2]),`
119			`.SPO(SPO[2]),`
120			`.A0(A[0]),`
121			`.A1(A[1]),`
122			`.A2(A[2]),`
123			`.A3(A[3]),`
124			`.A4(A[4]),`
125			`.D(D[2]),`
126			`.DPRA0(DPRA[0]),`
127			`.DPRA1(DPRA[1]),`
128			`.DPRA2(DPRA[2]),`
129			`.DPRA3(DPRA[3]),`
130			`.DPRA4(DPRA[4]),`
131			`.WCLK(WCLK),`
132			`.WE(WE)`
133			`);`
134
135			`//`
136			`// Instantiation of block 3`
137			`//`
138			`RAM32X1D ram32x1d_3(`
139			`.DPO(DPO[3]),`
140			`.SPO(SPO[3]),`
141			`.A0(A[0]),`
142			`.A1(A[1]),`
143			`.A2(A[2]),`
144			`.A3(A[3]),`
145			`.A4(A[4]),`
146			`.D(D[3]),`
147			`.DPRA0(DPRA[0]),`
148			`.DPRA1(DPRA[1]),`
149			`.DPRA2(DPRA[2]),`
150			`.DPRA3(DPRA[3]),`
151			`.DPRA4(DPRA[4]),`
152			`.WCLK(WCLK),`
153			`.WE(WE)`
154			`);`
155
156			`//`
157			`// Instantiation of block 4`
158			`//`
159			`RAM32X1D ram32x1d_4(`
160			`.DPO(DPO[4]),`
161			`.SPO(SPO[4]),`
162			`.A0(A[0]),`
163			`.A1(A[1]),`
164			`.A2(A[2]),`
165			`.A3(A[3]),`
166			`.A4(A[4]),`
167			`.D(D[4]),`
168			`.DPRA0(DPRA[0]),`
169			`.DPRA1(DPRA[1]),`
170			`.DPRA2(DPRA[2]),`
171			`.DPRA3(DPRA[3]),`
172			`.DPRA4(DPRA[4]),`
173			`.WCLK(WCLK),`
174			`.WE(WE)`
175			`);`
176
177			`//`
178			`// Instantiation of block 5`
179			`//`
180			`RAM32X1D ram32x1d_5(`
181			`.DPO(DPO[5]),`
182			`.SPO(SPO[5]),`
183			`.A0(A[0]),`
184			`.A1(A[1]),`
185			`.A2(A[2]),`
186			`.A3(A[3]),`
187			`.A4(A[4]),`
188			`.D(D[5]),`
189			`.DPRA0(DPRA[0]),`
190			`.DPRA1(DPRA[1]),`
191			`.DPRA2(DPRA[2]),`
192			`.DPRA3(DPRA[3]),`
193			`.DPRA4(DPRA[4]),`
194			`.WCLK(WCLK),`
195			`.WE(WE)`
196			`);`
197
198			`//`
199			`// Instantiation of block 6`
200			`//`
201			`RAM32X1D ram32x1d_6(`
202			`.DPO(DPO[6]),`
203			`.SPO(SPO[6]),`
204			`.A0(A[0]),`
205			`.A1(A[1]),`
206			`.A2(A[2]),`
207			`.A3(A[3]),`
208			`.A4(A[4]),`
209			`.D(D[6]),`
210			`.DPRA0(DPRA[0]),`
211			`.DPRA1(DPRA[1]),`
212			`.DPRA2(DPRA[2]),`
213			`.DPRA3(DPRA[3]),`
214			`.DPRA4(DPRA[4]),`
215			`.WCLK(WCLK),`
216			`.WE(WE)`
217			`);`
218
219			`//`
220			`// Instantiation of block 7`
221			`//`
222			`RAM32X1D ram32x1d_7(`
223			`.DPO(DPO[7]),`
224			`.SPO(SPO[7]),`
225			`.A0(A[0]),`
226			`.A1(A[1]),`
227			`.A2(A[2]),`
228			`.A3(A[3]),`
229			`.A4(A[4]),`
230			`.D(D[7]),`
231			`.DPRA0(DPRA[0]),`
232			`.DPRA1(DPRA[1]),`
233			`.DPRA2(DPRA[2]),`
234			`.DPRA3(DPRA[3]),`
235			`.DPRA4(DPRA[4]),`
236			`.WCLK(WCLK),`
237			`.WE(WE)`
238			`);`
239
240			`endmodule`
241
242			`endif

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[/] [or1k/] [branches/] [mp3_stable/] [or1200/] [rtl/] [verilog/] [xcv_ram32x8d.v] - Blame information for rev 205