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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Xilinx Virtex RAM 32x8D                                     ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Virtex dual-port memory                                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2001/10/14 13:12:10  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "defines.v"
 
`ifdef XILINX_RAM32X1D
 
module xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);
 
//
// I/O
//
output [7:0]     DPO;
output [7:0]     SPO;
input [4:0]      A;
input [4:0]      DPRA;
input [7:0]      D;
input           WCLK;
input           WE;
 
//
// Instantiation of block 0
//
RAM32X1D ram32x1d_0(
        .DPO(DPO[0]),
        .SPO(SPO[0]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[0]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 1
//
RAM32X1D ram32x1d_1(
        .DPO(DPO[1]),
        .SPO(SPO[1]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[1]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 2
//
RAM32X1D ram32x1d_2(
        .DPO(DPO[2]),
        .SPO(SPO[2]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[2]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 3
//
RAM32X1D ram32x1d_3(
        .DPO(DPO[3]),
        .SPO(SPO[3]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[3]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 4
//
RAM32X1D ram32x1d_4(
        .DPO(DPO[4]),
        .SPO(SPO[4]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[4]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 5
//
RAM32X1D ram32x1d_5(
        .DPO(DPO[5]),
        .SPO(SPO[5]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[5]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 6
//
RAM32X1D ram32x1d_6(
        .DPO(DPO[6]),
        .SPO(SPO[6]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[6]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
//
// Instantiation of block 7
//
RAM32X1D ram32x1d_7(
        .DPO(DPO[7]),
        .SPO(SPO[7]),
        .A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .A4(A[4]),
        .D(D[7]),
        .DPRA0(DPRA[0]),
        .DPRA1(DPRA[1]),
        .DPRA2(DPRA[2]),
        .DPRA3(DPRA[3]),
        .DPRA4(DPRA[4]),
        .WCLK(WCLK),
        .WE(WE)
);
 
endmodule
 
`endif

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Line No.	Rev	Author	Line
1	218	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Xilinx Virtex RAM 32x8D ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Virtex dual-port memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.6 2001/10/14 13:12:10 lampret`
48			`// MP3 version.`
49			`//`
50			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
51			`// no message`
52			`//`
53			`// Revision 1.1 2001/08/09 13:39:33 lampret`
54			`// Major clean-up.`
55			`//`
56			`//`
57
58			`// synopsys translate_off`
59			`include "timescale.v"
60			`// synopsys translate_on`
61			`include "defines.v"
62
63			`ifdef XILINX_RAM32X1D
64
65			`module xcv_ram32x8d (DPO, SPO, A, D, DPRA, WCLK, WE);`
66
67			`//`
68			`// I/O`
69			`//`
70			`output [7:0] DPO;`
71			`output [7:0] SPO;`
72			`input [4:0] A;`
73			`input [4:0] DPRA;`
74			`input [7:0] D;`
75			`input WCLK;`
76			`input WE;`
77
78			`//`
79			`// Instantiation of block 0`
80			`//`
81			`RAM32X1D ram32x1d_0(`
82			`.DPO(DPO[0]),`
83			`.SPO(SPO[0]),`
84			`.A0(A[0]),`
85			`.A1(A[1]),`
86			`.A2(A[2]),`
87			`.A3(A[3]),`
88			`.A4(A[4]),`
89			`.D(D[0]),`
90			`.DPRA0(DPRA[0]),`
91			`.DPRA1(DPRA[1]),`
92			`.DPRA2(DPRA[2]),`
93			`.DPRA3(DPRA[3]),`
94			`.DPRA4(DPRA[4]),`
95			`.WCLK(WCLK),`
96			`.WE(WE)`
97			`);`
98
99			`//`
100			`// Instantiation of block 1`
101			`//`
102			`RAM32X1D ram32x1d_1(`
103			`.DPO(DPO[1]),`
104			`.SPO(SPO[1]),`
105			`.A0(A[0]),`
106			`.A1(A[1]),`
107			`.A2(A[2]),`
108			`.A3(A[3]),`
109			`.A4(A[4]),`
110			`.D(D[1]),`
111			`.DPRA0(DPRA[0]),`
112			`.DPRA1(DPRA[1]),`
113			`.DPRA2(DPRA[2]),`
114			`.DPRA3(DPRA[3]),`
115			`.DPRA4(DPRA[4]),`
116			`.WCLK(WCLK),`
117			`.WE(WE)`
118			`);`
119
120			`//`
121			`// Instantiation of block 2`
122			`//`
123			`RAM32X1D ram32x1d_2(`
124			`.DPO(DPO[2]),`
125			`.SPO(SPO[2]),`
126			`.A0(A[0]),`
127			`.A1(A[1]),`
128			`.A2(A[2]),`
129			`.A3(A[3]),`
130			`.A4(A[4]),`
131			`.D(D[2]),`
132			`.DPRA0(DPRA[0]),`
133			`.DPRA1(DPRA[1]),`
134			`.DPRA2(DPRA[2]),`
135			`.DPRA3(DPRA[3]),`
136			`.DPRA4(DPRA[4]),`
137			`.WCLK(WCLK),`
138			`.WE(WE)`
139			`);`
140
141			`//`
142			`// Instantiation of block 3`
143			`//`
144			`RAM32X1D ram32x1d_3(`
145			`.DPO(DPO[3]),`
146			`.SPO(SPO[3]),`
147			`.A0(A[0]),`
148			`.A1(A[1]),`
149			`.A2(A[2]),`
150			`.A3(A[3]),`
151			`.A4(A[4]),`
152			`.D(D[3]),`
153			`.DPRA0(DPRA[0]),`
154			`.DPRA1(DPRA[1]),`
155			`.DPRA2(DPRA[2]),`
156			`.DPRA3(DPRA[3]),`
157			`.DPRA4(DPRA[4]),`
158			`.WCLK(WCLK),`
159			`.WE(WE)`
160			`);`
161
162			`//`
163			`// Instantiation of block 4`
164			`//`
165			`RAM32X1D ram32x1d_4(`
166			`.DPO(DPO[4]),`
167			`.SPO(SPO[4]),`
168			`.A0(A[0]),`
169			`.A1(A[1]),`
170			`.A2(A[2]),`
171			`.A3(A[3]),`
172			`.A4(A[4]),`
173			`.D(D[4]),`
174			`.DPRA0(DPRA[0]),`
175			`.DPRA1(DPRA[1]),`
176			`.DPRA2(DPRA[2]),`
177			`.DPRA3(DPRA[3]),`
178			`.DPRA4(DPRA[4]),`
179			`.WCLK(WCLK),`
180			`.WE(WE)`
181			`);`
182
183			`//`
184			`// Instantiation of block 5`
185			`//`
186			`RAM32X1D ram32x1d_5(`
187			`.DPO(DPO[5]),`
188			`.SPO(SPO[5]),`
189			`.A0(A[0]),`
190			`.A1(A[1]),`
191			`.A2(A[2]),`
192			`.A3(A[3]),`
193			`.A4(A[4]),`
194			`.D(D[5]),`
195			`.DPRA0(DPRA[0]),`
196			`.DPRA1(DPRA[1]),`
197			`.DPRA2(DPRA[2]),`
198			`.DPRA3(DPRA[3]),`
199			`.DPRA4(DPRA[4]),`
200			`.WCLK(WCLK),`
201			`.WE(WE)`
202			`);`
203
204			`//`
205			`// Instantiation of block 6`
206			`//`
207			`RAM32X1D ram32x1d_6(`
208			`.DPO(DPO[6]),`
209			`.SPO(SPO[6]),`
210			`.A0(A[0]),`
211			`.A1(A[1]),`
212			`.A2(A[2]),`
213			`.A3(A[3]),`
214			`.A4(A[4]),`
215			`.D(D[6]),`
216			`.DPRA0(DPRA[0]),`
217			`.DPRA1(DPRA[1]),`
218			`.DPRA2(DPRA[2]),`
219			`.DPRA3(DPRA[3]),`
220			`.DPRA4(DPRA[4]),`
221			`.WCLK(WCLK),`
222			`.WE(WE)`
223			`);`
224
225			`//`
226			`// Instantiation of block 7`
227			`//`
228			`RAM32X1D ram32x1d_7(`
229			`.DPO(DPO[7]),`
230			`.SPO(SPO[7]),`
231			`.A0(A[0]),`
232			`.A1(A[1]),`
233			`.A2(A[2]),`
234			`.A3(A[3]),`
235			`.A4(A[4]),`
236			`.D(D[7]),`
237			`.DPRA0(DPRA[0]),`
238			`.DPRA1(DPRA[1]),`
239			`.DPRA2(DPRA[2]),`
240			`.DPRA3(DPRA[3]),`
241			`.DPRA4(DPRA[4]),`
242			`.WCLK(WCLK),`
243			`.WE(WE)`
244			`);`
245
246			`endmodule`
247
248			`endif