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[/] [or1k/] [branches/] [oc/] [gdb-5.0/] [opcodes/] [arm-opc.h] - Blame information for rev 1765

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1 106 markom
/* Opcode table for the ARM.
2
 
3
   Copyright 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
4
 
5
   This program is free software; you can redistribute it and/or modify
6
   it under the terms of the GNU General Public License as published by
7
   the Free Software Foundation; either version 2, or (at your option)
8
   any later version.
9
 
10
   This program is distributed in the hope that it will be useful,
11
   but WITHOUT ANY WARRANTY; without even the implied warranty of
12
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
   GNU General Public License for more details.
14
 
15
   You should have received a copy of the GNU General Public License
16
   along with this program; if not, write to the Free Software
17
   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
18
 
19
 
20
struct arm_opcode {
21
    unsigned long value, mask;  /* recognise instruction if (op&mask)==value */
22
    char *assembler;            /* how to disassemble this instruction */
23
};
24
 
25
struct thumb_opcode
26
{
27
    unsigned short value, mask; /* recognise instruction if (op&mask)==value */
28
    char * assembler;           /* how to disassemble this instruction */
29
};
30
 
31
/* format of the assembler string :
32
 
33
   %%                   %
34
   %<bitfield>d         print the bitfield in decimal
35
   %<bitfield>x         print the bitfield in hex
36
   %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
37
   %<bitfield>r         print as an ARM register
38
   %<bitfield>f         print a floating point constant if >7 else a
39
                        floating point register
40
   %c                   print condition code (always bits 28-31)
41
   %P                   print floating point precision in arithmetic insn
42
   %Q                   print floating point precision in ldf/stf insn
43
   %R                   print floating point rounding mode
44
   %<bitnum>'c          print specified char iff bit is one
45
   %<bitnum>`c          print specified char iff bit is zero
46
   %<bitnum>?ab         print a if bit is one else print b
47
   %p                   print 'p' iff bits 12-15 are 15
48
   %t                   print 't' iff bit 21 set and bit 24 clear
49
   %h                   print 'h' iff bit 5 set, else print 'b'
50
   %o                   print operand2 (immediate or register + shift)
51
   %a                   print address for ldr/str instruction
52
   %s                   print address for ldr/str halfword/signextend instruction
53
   %b                   print branch destination
54
   %A                   print address for ldc/stc/ldf/stf instruction
55
   %m                   print register mask for ldm/stm instruction
56
   %C                   print the PSR sub type.
57
   %F                   print the COUNT field of a LFM/SFM instruction.
58
Thumb specific format options:
59
   %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
60
   %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
61
   %<bitfield>I         print bitfield as a signed decimal
62
                                (top bit of range being the sign bit)
63
   %M                   print Thumb register mask
64
   %N                   print Thumb register mask (with LR)
65
   %O                   print Thumb register mask (with PC)
66
   %T                   print Thumb condition code (always bits 8-11)
67
   %<bitfield>B         print Thumb branch destination (signed displacement)
68
   %<bitfield>W         print (bitfield * 4) as a decimal
69
   %<bitfield>H         print (bitfield * 2) as a decimal
70
   %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
71
*/
72
 
73
/* Note: There is a partial ordering in this table - it must be searched from
74
   the top to obtain a correct match. */
75
 
76
static struct arm_opcode arm_opcodes[] =
77
{
78
    /* ARM instructions */
79
    {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
80
    {0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
81
    {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
82
    {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
83
    {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
84
    {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
85
    {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
86
    {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"},
87
    {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"},
88
    {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
89
    {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
90
    {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
91
    {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
92
    {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
93
    {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
94
    {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
95
    {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
96
    {0x0120f000, 0x0db6f000, "msr%c\t%22?scpsr%C, %o"},
97
    {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?scpsr"},
98
    {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
99
    {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
100
    {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
101
    {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
102
    {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
103
    {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
104
    {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
105
    {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
106
    {0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
107
    {0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
108
    {0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
109
    {0x06000010, 0x0e000010, "undefined"},
110
    {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
111
    {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
112
    {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
113
    {0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
114
    {0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
115
 
116
    /* Floating point coprocessor instructions */
117
    {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
118
    {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
119
    {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
120
    {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
121
    {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
122
    {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
123
    {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
124
    {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
125
    {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
126
    {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
127
    {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
128
    {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
129
    {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
130
    {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
131
    {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
132
    {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
133
    {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
134
    {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
135
    {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
136
    {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
137
    {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
138
    {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
139
    {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
140
    {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
141
    {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
142
    {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
143
    {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
144
    {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
145
    {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
146
    {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
147
    {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
148
    {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
149
    {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
150
    {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
151
    {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
152
    {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
153
    {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
154
    {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
155
    {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
156
    {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
157
    {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
158
    {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
159
    {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
160
 
161
    /* Generic coprocessor instructions */
162
    {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
163
    {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
164
    {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
165
    {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
166
    {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
167
 
168
    /* The rest.  */
169
    {0x00000000, 0x00000000, "undefined instruction %0-31x"},
170
    {0x00000000, 0x00000000, 0}
171
};
172
 
173
#define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */
174
 
175
static struct thumb_opcode thumb_opcodes[] =
176
{
177
  /* Thumb instructions */
178
  {0x46C0, 0xFFFF, "nop\t\t\t(mov r8,r8)"}, /* format 5 instructions do not update the PSR */
179
  {0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"},
180
  /* format 4 */
181
  {0x4000, 0xFFC0, "and\t%0-2r, %3-5r"},
182
  {0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"},
183
  {0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"},
184
  {0x40C0, 0xFFC0, "lsr\t%0-2r, %3-5r"},
185
  {0x4100, 0xFFC0, "asr\t%0-2r, %3-5r"},
186
  {0x4140, 0xFFC0, "adc\t%0-2r, %3-5r"},
187
  {0x4180, 0xFFC0, "sbc\t%0-2r, %3-5r"},
188
  {0x41C0, 0xFFC0, "ror\t%0-2r, %3-5r"},
189
  {0x4200, 0xFFC0, "tst\t%0-2r, %3-5r"},
190
  {0x4240, 0xFFC0, "neg\t%0-2r, %3-5r"},
191
  {0x4280, 0xFFC0, "cmp\t%0-2r, %3-5r"},
192
  {0x42C0, 0xFFC0, "cmn\t%0-2r, %3-5r"},
193
  {0x4300, 0xFFC0, "orr\t%0-2r, %3-5r"},
194
  {0x4340, 0xFFC0, "mul\t%0-2r, %3-5r"},
195
  {0x4380, 0xFFC0, "bic\t%0-2r, %3-5r"},
196
  {0x43C0, 0xFFC0, "mvn\t%0-2r, %3-5r"},
197
  /* format 13 */
198
  {0xB000, 0xFF80, "add\tsp, #%0-6W"},
199
  {0xB080, 0xFF80, "sub\tsp, #%0-6W"},
200
  /* format 5 */
201
  {0x4700, 0xFF80, "bx\t%S"},
202
  {0x4400, 0xFF00, "add\t%D, %S"},
203
  {0x4500, 0xFF00, "cmp\t%D, %S"},
204
  {0x4600, 0xFF00, "mov\t%D, %S"},
205
  /* format 14 */
206
  {0xB400, 0xFE00, "push\t%N"},
207
  {0xBC00, 0xFE00, "pop\t%O"},
208
  /* format 2 */
209
  {0x1800, 0xFE00, "add\t%0-2r, %3-5r, %6-8r"},
210
  {0x1A00, 0xFE00, "sub\t%0-2r, %3-5r, %6-8r"},
211
  {0x1C00, 0xFE00, "add\t%0-2r, %3-5r, #%6-8d"},
212
  {0x1E00, 0xFE00, "sub\t%0-2r, %3-5r, #%6-8d"},
213
  /* format 8 */
214
  {0x5200, 0xFE00, "strh\t%0-2r, [%3-5r, %6-8r]"},
215
  {0x5A00, 0xFE00, "ldrh\t%0-2r, [%3-5r, %6-8r]"},
216
  {0x5600, 0xF600, "lds%11?hb\t%0-2r, [%3-5r, %6-8r]"},
217
  /* format 7 */
218
  {0x5000, 0xFA00, "str%10'b\t%0-2r, [%3-5r, %6-8r]"},
219
  {0x5800, 0xFA00, "ldr%10'b\t%0-2r, [%3-5r, %6-8r]"},
220
  /* format 1 */
221
  {0x0000, 0xF800, "lsl\t%0-2r, %3-5r, #%6-10d"},
222
  {0x0800, 0xF800, "lsr\t%0-2r, %3-5r, #%6-10d"},
223
  {0x1000, 0xF800, "asr\t%0-2r, %3-5r, #%6-10d"},
224
  /* format 3 */
225
  {0x2000, 0xF800, "mov\t%8-10r, #%0-7d"},
226
  {0x2800, 0xF800, "cmp\t%8-10r, #%0-7d"},
227
  {0x3000, 0xF800, "add\t%8-10r, #%0-7d"},
228
  {0x3800, 0xF800, "sub\t%8-10r, #%0-7d"},
229
  /* format 6 */
230
  {0x4800, 0xF800, "ldr\t%8-10r, [pc, #%0-7W]\t(%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
231
  /* format 9 */
232
  {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
233
  {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
234
  {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
235
  {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
236
  /* format 10 */
237
  {0x8000, 0xF800, "strh\t%0-2r, [%3-5r, #%6-10H]"},
238
  {0x8800, 0xF800, "ldrh\t%0-2r, [%3-5r, #%6-10H]"},
239
  /* format 11 */
240
  {0x9000, 0xF800, "str\t%8-10r, [sp, #%0-7W]"},
241
  {0x9800, 0xF800, "ldr\t%8-10r, [sp, #%0-7W]"},
242
  /* format 12 */
243
  {0xA000, 0xF800, "add\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
244
  {0xA800, 0xF800, "add\t%8-10r, sp, #%0-7W"},
245
  /* format 15 */
246
  {0xC000, 0xF800, "stmia\t%8-10r!,%M"},
247
  {0xC800, 0xF800, "ldmia\t%8-10r!,%M"},
248
  /* format 18 */
249
  {0xE000, 0xF800, "b\t%0-10B"},
250
  {0xE800, 0xF800, "undefined"},
251
  /* format 19 */
252
  {0xF000, 0xF800, ""}, /* special processing required in disassembler */
253
  {0xF800, 0xF800, "second half of BL instruction %0-15x"},
254
  /* format 16 */
255
  {0xD000, 0xFF00, "beq\t%0-7B"},
256
  {0xD100, 0xFF00, "bne\t%0-7B"},
257
  {0xD200, 0xFF00, "bcs\t%0-7B"},
258
  {0xD300, 0xFF00, "bcc\t%0-7B"},
259
  {0xD400, 0xFF00, "bmi\t%0-7B"},
260
  {0xD500, 0xFF00, "bpl\t%0-7B"},
261
  {0xD600, 0xFF00, "bvs\t%0-7B"},
262
  {0xD700, 0xFF00, "bvc\t%0-7B"},
263
  {0xD800, 0xFF00, "bhi\t%0-7B"},
264
  {0xD900, 0xFF00, "bls\t%0-7B"},
265
  {0xDA00, 0xFF00, "bge\t%0-7B"},
266
  {0xDB00, 0xFF00, "blt\t%0-7B"},
267
  {0xDC00, 0xFF00, "bgt\t%0-7B"},
268
  {0xDD00, 0xFF00, "ble\t%0-7B"},
269
  /* format 17 */
270
  {0xDE00, 0xFF00, "bal\t%0-7B"},
271
  {0xDF00, 0xFF00, "swi\t%0-7d"},
272
  /* format 9 */
273
  {0x6000, 0xF800, "str\t%0-2r, [%3-5r, #%6-10W]"},
274
  {0x6800, 0xF800, "ldr\t%0-2r, [%3-5r, #%6-10W]"},
275
  {0x7000, 0xF800, "strb\t%0-2r, [%3-5r, #%6-10d]"},
276
  {0x7800, 0xF800, "ldrb\t%0-2r, [%3-5r, #%6-10d]"},
277
  /* the rest */
278
  {0x0000, 0x0000, "undefined instruction %0-15x"},
279
  {0x0000, 0x0000, 0}
280
};
281
 
282
#define BDISP23(x) ((((((x) & 0x07ff) << 11) | (((x) & 0x07ff0000) >> 16)) \
283
                     ^ 0x200000) - 0x200000) /* 23bit */
284
 

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