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markom |
/* Simulator parallel routines for CGEN simulators (and maybe others).
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Copyright (C) 1999, 2000 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This file is part of the GNU instruction set simulator.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sim-main.h"
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#include "cgen-mem.h"
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#include "cgen-par.h"
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/* Functions required by the cgen interface. These functions add various
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kinds of writes to the write queue. */
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void sim_queue_bi_write (SIM_CPU *cpu, BI *target, BI value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_BI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.bi_write.target = target;
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element->kinds.bi_write.value = value;
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}
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void sim_queue_qi_write (SIM_CPU *cpu, UQI *target, UQI value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_QI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.qi_write.target = target;
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element->kinds.qi_write.value = value;
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}
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void sim_queue_si_write (SIM_CPU *cpu, SI *target, SI value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_SI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.si_write.target = target;
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element->kinds.si_write.value = value;
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}
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void sim_queue_sf_write (SIM_CPU *cpu, SI *target, SF value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_SF_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.sf_write.target = target;
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element->kinds.sf_write.value = value;
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}
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void sim_queue_pc_write (SIM_CPU *cpu, USI value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_PC_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.pc_write.value = value;
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}
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void sim_queue_fn_hi_write (
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, UHI),
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UINT regno,
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UHI value
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)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_HI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_hi_write.function = write_function;
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element->kinds.fn_hi_write.regno = regno;
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element->kinds.fn_hi_write.value = value;
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}
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void sim_queue_fn_si_write (
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, USI),
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UINT regno,
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USI value
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)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_SI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_si_write.function = write_function;
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element->kinds.fn_si_write.regno = regno;
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element->kinds.fn_si_write.value = value;
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}
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void sim_queue_fn_sf_write (
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, SF),
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UINT regno,
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SF value
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)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_SF_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_sf_write.function = write_function;
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element->kinds.fn_sf_write.regno = regno;
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element->kinds.fn_sf_write.value = value;
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}
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void sim_queue_fn_di_write (
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, DI),
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UINT regno,
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DI value
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)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_DI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_di_write.function = write_function;
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element->kinds.fn_di_write.regno = regno;
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element->kinds.fn_di_write.value = value;
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}
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void sim_queue_fn_xi_write (
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, SI *),
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UINT regno,
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SI *value
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)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_XI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_xi_write.function = write_function;
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element->kinds.fn_xi_write.regno = regno;
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element->kinds.fn_xi_write.value[0] = value[0];
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element->kinds.fn_xi_write.value[1] = value[1];
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element->kinds.fn_xi_write.value[2] = value[2];
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element->kinds.fn_xi_write.value[3] = value[3];
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}
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void sim_queue_fn_df_write (
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, UINT, DF),
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UINT regno,
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DF value
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)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_DF_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_df_write.function = write_function;
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element->kinds.fn_df_write.regno = regno;
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element->kinds.fn_df_write.value = value;
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}
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void sim_queue_fn_pc_write (
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SIM_CPU *cpu,
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void (*write_function)(SIM_CPU *cpu, USI),
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USI value
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)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_FN_PC_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.fn_pc_write.function = write_function;
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element->kinds.fn_pc_write.value = value;
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}
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void sim_queue_mem_qi_write (SIM_CPU *cpu, SI address, QI value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_QI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_qi_write.address = address;
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element->kinds.mem_qi_write.value = value;
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}
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void sim_queue_mem_hi_write (SIM_CPU *cpu, SI address, HI value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_HI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_hi_write.address = address;
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element->kinds.mem_hi_write.value = value;
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}
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void sim_queue_mem_si_write (SIM_CPU *cpu, SI address, SI value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_SI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_si_write.address = address;
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element->kinds.mem_si_write.value = value;
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}
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void sim_queue_mem_di_write (SIM_CPU *cpu, SI address, DI value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_DI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_di_write.address = address;
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element->kinds.mem_di_write.value = value;
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}
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void sim_queue_mem_df_write (SIM_CPU *cpu, SI address, DF value)
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{
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_DF_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_df_write.address = address;
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element->kinds.mem_df_write.value = value;
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}
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void sim_queue_mem_xi_write (SIM_CPU *cpu, SI address, SI *value)
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{
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| 241 |
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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element->kind = CGEN_MEM_XI_WRITE;
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element->insn_address = CPU_PC_GET (cpu);
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element->kinds.mem_xi_write.address = address;
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element->kinds.mem_xi_write.value[0] = value[0];
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element->kinds.mem_xi_write.value[1] = value[1];
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| 248 |
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element->kinds.mem_xi_write.value[2] = value[2];
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| 249 |
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element->kinds.mem_xi_write.value[3] = value[3];
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| 250 |
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}
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| 251 |
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| 252 |
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void sim_queue_fn_mem_qi_write (
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| 253 |
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SIM_CPU *cpu,
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| 254 |
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void (*write_function)(SIM_CPU *cpu, IADDR, SI, QI),
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SI address,
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| 256 |
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QI value
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| 257 |
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)
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| 258 |
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{
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| 259 |
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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| 260 |
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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| 261 |
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element->kind = CGEN_FN_MEM_QI_WRITE;
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| 262 |
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element->insn_address = CPU_PC_GET (cpu);
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| 263 |
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element->kinds.fn_mem_qi_write.function = write_function;
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| 264 |
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element->kinds.fn_mem_qi_write.address = address;
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| 265 |
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element->kinds.fn_mem_qi_write.value = value;
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| 266 |
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}
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| 267 |
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| 268 |
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void sim_queue_fn_mem_hi_write (
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| 269 |
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SIM_CPU *cpu,
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| 270 |
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void (*write_function)(SIM_CPU *cpu, IADDR, SI, HI),
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| 271 |
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SI address,
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| 272 |
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HI value
|
| 273 |
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)
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| 274 |
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{
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| 275 |
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
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| 276 |
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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| 277 |
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element->kind = CGEN_FN_MEM_HI_WRITE;
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| 278 |
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element->insn_address = CPU_PC_GET (cpu);
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| 279 |
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element->kinds.fn_mem_hi_write.function = write_function;
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| 280 |
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element->kinds.fn_mem_hi_write.address = address;
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| 281 |
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element->kinds.fn_mem_hi_write.value = value;
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| 282 |
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}
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| 283 |
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| 284 |
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void sim_queue_fn_mem_si_write (
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| 285 |
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SIM_CPU *cpu,
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| 286 |
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void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI),
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| 287 |
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SI address,
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| 288 |
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SI value
|
| 289 |
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)
|
| 290 |
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{
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| 291 |
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CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
| 292 |
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CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
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| 293 |
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element->kind = CGEN_FN_MEM_SI_WRITE;
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| 294 |
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element->insn_address = CPU_PC_GET (cpu);
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| 295 |
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element->kinds.fn_mem_si_write.function = write_function;
|
| 296 |
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element->kinds.fn_mem_si_write.address = address;
|
| 297 |
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element->kinds.fn_mem_si_write.value = value;
|
| 298 |
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}
|
| 299 |
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| 300 |
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void sim_queue_fn_mem_di_write (
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| 301 |
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SIM_CPU *cpu,
|
| 302 |
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|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, DI),
|
| 303 |
|
|
SI address,
|
| 304 |
|
|
DI value
|
| 305 |
|
|
)
|
| 306 |
|
|
{
|
| 307 |
|
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
| 308 |
|
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
| 309 |
|
|
element->kind = CGEN_FN_MEM_DI_WRITE;
|
| 310 |
|
|
element->insn_address = CPU_PC_GET (cpu);
|
| 311 |
|
|
element->kinds.fn_mem_di_write.function = write_function;
|
| 312 |
|
|
element->kinds.fn_mem_di_write.address = address;
|
| 313 |
|
|
element->kinds.fn_mem_di_write.value = value;
|
| 314 |
|
|
}
|
| 315 |
|
|
|
| 316 |
|
|
void sim_queue_fn_mem_df_write (
|
| 317 |
|
|
SIM_CPU *cpu,
|
| 318 |
|
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, DF),
|
| 319 |
|
|
SI address,
|
| 320 |
|
|
DF value
|
| 321 |
|
|
)
|
| 322 |
|
|
{
|
| 323 |
|
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
| 324 |
|
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
| 325 |
|
|
element->kind = CGEN_FN_MEM_DF_WRITE;
|
| 326 |
|
|
element->insn_address = CPU_PC_GET (cpu);
|
| 327 |
|
|
element->kinds.fn_mem_df_write.function = write_function;
|
| 328 |
|
|
element->kinds.fn_mem_df_write.address = address;
|
| 329 |
|
|
element->kinds.fn_mem_df_write.value = value;
|
| 330 |
|
|
}
|
| 331 |
|
|
|
| 332 |
|
|
void sim_queue_fn_mem_xi_write (
|
| 333 |
|
|
SIM_CPU *cpu,
|
| 334 |
|
|
void (*write_function)(SIM_CPU *cpu, IADDR, SI, SI *),
|
| 335 |
|
|
SI address,
|
| 336 |
|
|
SI *value
|
| 337 |
|
|
)
|
| 338 |
|
|
{
|
| 339 |
|
|
CGEN_WRITE_QUEUE *q = CPU_WRITE_QUEUE (cpu);
|
| 340 |
|
|
CGEN_WRITE_QUEUE_ELEMENT *element = CGEN_WRITE_QUEUE_NEXT (q);
|
| 341 |
|
|
element->kind = CGEN_FN_MEM_XI_WRITE;
|
| 342 |
|
|
element->insn_address = CPU_PC_GET (cpu);
|
| 343 |
|
|
element->kinds.fn_mem_xi_write.function = write_function;
|
| 344 |
|
|
element->kinds.fn_mem_xi_write.address = address;
|
| 345 |
|
|
element->kinds.fn_mem_xi_write.value[0] = value[0];
|
| 346 |
|
|
element->kinds.fn_mem_xi_write.value[1] = value[1];
|
| 347 |
|
|
element->kinds.fn_mem_xi_write.value[2] = value[2];
|
| 348 |
|
|
element->kinds.fn_mem_xi_write.value[3] = value[3];
|
| 349 |
|
|
}
|
| 350 |
|
|
|
| 351 |
|
|
/* Execute a write stored on the write queue. */
|
| 352 |
|
|
void
|
| 353 |
|
|
cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item)
|
| 354 |
|
|
{
|
| 355 |
|
|
IADDR pc;
|
| 356 |
|
|
switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item))
|
| 357 |
|
|
{
|
| 358 |
|
|
case CGEN_BI_WRITE:
|
| 359 |
|
|
*item->kinds.bi_write.target = item->kinds.bi_write.value;
|
| 360 |
|
|
break;
|
| 361 |
|
|
case CGEN_QI_WRITE:
|
| 362 |
|
|
*item->kinds.qi_write.target = item->kinds.qi_write.value;
|
| 363 |
|
|
break;
|
| 364 |
|
|
case CGEN_SI_WRITE:
|
| 365 |
|
|
*item->kinds.si_write.target = item->kinds.si_write.value;
|
| 366 |
|
|
break;
|
| 367 |
|
|
case CGEN_SF_WRITE:
|
| 368 |
|
|
*item->kinds.sf_write.target = item->kinds.sf_write.value;
|
| 369 |
|
|
break;
|
| 370 |
|
|
case CGEN_PC_WRITE:
|
| 371 |
|
|
CPU_PC_SET (cpu, item->kinds.pc_write.value);
|
| 372 |
|
|
break;
|
| 373 |
|
|
case CGEN_FN_HI_WRITE:
|
| 374 |
|
|
item->kinds.fn_hi_write.function (cpu,
|
| 375 |
|
|
item->kinds.fn_hi_write.regno,
|
| 376 |
|
|
item->kinds.fn_hi_write.value);
|
| 377 |
|
|
break;
|
| 378 |
|
|
case CGEN_FN_SI_WRITE:
|
| 379 |
|
|
item->kinds.fn_si_write.function (cpu,
|
| 380 |
|
|
item->kinds.fn_si_write.regno,
|
| 381 |
|
|
item->kinds.fn_si_write.value);
|
| 382 |
|
|
break;
|
| 383 |
|
|
case CGEN_FN_SF_WRITE:
|
| 384 |
|
|
item->kinds.fn_sf_write.function (cpu,
|
| 385 |
|
|
item->kinds.fn_sf_write.regno,
|
| 386 |
|
|
item->kinds.fn_sf_write.value);
|
| 387 |
|
|
break;
|
| 388 |
|
|
case CGEN_FN_DI_WRITE:
|
| 389 |
|
|
item->kinds.fn_di_write.function (cpu,
|
| 390 |
|
|
item->kinds.fn_di_write.regno,
|
| 391 |
|
|
item->kinds.fn_di_write.value);
|
| 392 |
|
|
break;
|
| 393 |
|
|
case CGEN_FN_DF_WRITE:
|
| 394 |
|
|
item->kinds.fn_df_write.function (cpu,
|
| 395 |
|
|
item->kinds.fn_df_write.regno,
|
| 396 |
|
|
item->kinds.fn_df_write.value);
|
| 397 |
|
|
break;
|
| 398 |
|
|
case CGEN_FN_XI_WRITE:
|
| 399 |
|
|
item->kinds.fn_xi_write.function (cpu,
|
| 400 |
|
|
item->kinds.fn_xi_write.regno,
|
| 401 |
|
|
item->kinds.fn_xi_write.value);
|
| 402 |
|
|
break;
|
| 403 |
|
|
case CGEN_FN_PC_WRITE:
|
| 404 |
|
|
item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value);
|
| 405 |
|
|
break;
|
| 406 |
|
|
case CGEN_MEM_QI_WRITE:
|
| 407 |
|
|
pc = item->insn_address;
|
| 408 |
|
|
SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address,
|
| 409 |
|
|
item->kinds.mem_qi_write.value);
|
| 410 |
|
|
break;
|
| 411 |
|
|
case CGEN_MEM_HI_WRITE:
|
| 412 |
|
|
pc = item->insn_address;
|
| 413 |
|
|
SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address,
|
| 414 |
|
|
item->kinds.mem_hi_write.value);
|
| 415 |
|
|
break;
|
| 416 |
|
|
case CGEN_MEM_SI_WRITE:
|
| 417 |
|
|
pc = item->insn_address;
|
| 418 |
|
|
SETMEMSI (cpu, pc, item->kinds.mem_si_write.address,
|
| 419 |
|
|
item->kinds.mem_si_write.value);
|
| 420 |
|
|
break;
|
| 421 |
|
|
case CGEN_MEM_DI_WRITE:
|
| 422 |
|
|
pc = item->insn_address;
|
| 423 |
|
|
SETMEMDI (cpu, pc, item->kinds.mem_di_write.address,
|
| 424 |
|
|
item->kinds.mem_di_write.value);
|
| 425 |
|
|
break;
|
| 426 |
|
|
case CGEN_MEM_DF_WRITE:
|
| 427 |
|
|
pc = item->insn_address;
|
| 428 |
|
|
SETMEMDF (cpu, pc, item->kinds.mem_df_write.address,
|
| 429 |
|
|
item->kinds.mem_df_write.value);
|
| 430 |
|
|
break;
|
| 431 |
|
|
case CGEN_MEM_XI_WRITE:
|
| 432 |
|
|
pc = item->insn_address;
|
| 433 |
|
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address,
|
| 434 |
|
|
item->kinds.mem_xi_write.value[0]);
|
| 435 |
|
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 4,
|
| 436 |
|
|
item->kinds.mem_xi_write.value[1]);
|
| 437 |
|
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 8,
|
| 438 |
|
|
item->kinds.mem_xi_write.value[2]);
|
| 439 |
|
|
SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 12,
|
| 440 |
|
|
item->kinds.mem_xi_write.value[3]);
|
| 441 |
|
|
break;
|
| 442 |
|
|
case CGEN_FN_MEM_QI_WRITE:
|
| 443 |
|
|
pc = item->insn_address;
|
| 444 |
|
|
item->kinds.fn_mem_qi_write.function (cpu, pc,
|
| 445 |
|
|
item->kinds.fn_mem_qi_write.address,
|
| 446 |
|
|
item->kinds.fn_mem_qi_write.value);
|
| 447 |
|
|
break;
|
| 448 |
|
|
case CGEN_FN_MEM_HI_WRITE:
|
| 449 |
|
|
pc = item->insn_address;
|
| 450 |
|
|
item->kinds.fn_mem_hi_write.function (cpu, pc,
|
| 451 |
|
|
item->kinds.fn_mem_hi_write.address,
|
| 452 |
|
|
item->kinds.fn_mem_hi_write.value);
|
| 453 |
|
|
break;
|
| 454 |
|
|
case CGEN_FN_MEM_SI_WRITE:
|
| 455 |
|
|
pc = item->insn_address;
|
| 456 |
|
|
item->kinds.fn_mem_si_write.function (cpu, pc,
|
| 457 |
|
|
item->kinds.fn_mem_si_write.address,
|
| 458 |
|
|
item->kinds.fn_mem_si_write.value);
|
| 459 |
|
|
break;
|
| 460 |
|
|
case CGEN_FN_MEM_DI_WRITE:
|
| 461 |
|
|
pc = item->insn_address;
|
| 462 |
|
|
item->kinds.fn_mem_di_write.function (cpu, pc,
|
| 463 |
|
|
item->kinds.fn_mem_di_write.address,
|
| 464 |
|
|
item->kinds.fn_mem_di_write.value);
|
| 465 |
|
|
break;
|
| 466 |
|
|
case CGEN_FN_MEM_DF_WRITE:
|
| 467 |
|
|
pc = item->insn_address;
|
| 468 |
|
|
item->kinds.fn_mem_df_write.function (cpu, pc,
|
| 469 |
|
|
item->kinds.fn_mem_df_write.address,
|
| 470 |
|
|
item->kinds.fn_mem_df_write.value);
|
| 471 |
|
|
break;
|
| 472 |
|
|
case CGEN_FN_MEM_XI_WRITE:
|
| 473 |
|
|
pc = item->insn_address;
|
| 474 |
|
|
item->kinds.fn_mem_xi_write.function (cpu, pc,
|
| 475 |
|
|
item->kinds.fn_mem_xi_write.address,
|
| 476 |
|
|
item->kinds.fn_mem_xi_write.value);
|
| 477 |
|
|
break;
|
| 478 |
|
|
default:
|
| 479 |
|
|
abort ();
|
| 480 |
|
|
break; /* FIXME: for now....print message later. */
|
| 481 |
|
|
}
|
| 482 |
|
|
}
|
| 483 |
|
|
|
| 484 |
|
|
/* Utilities for the write queue. */
|
| 485 |
|
|
CGEN_WRITE_QUEUE_ELEMENT *
|
| 486 |
|
|
cgen_write_queue_overflow (CGEN_WRITE_QUEUE *q)
|
| 487 |
|
|
{
|
| 488 |
|
|
abort (); /* FIXME: for now....print message later. */
|
| 489 |
|
|
return 0;
|
| 490 |
|
|
}
|
