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[/] [or1k/] [branches/] [oc/] [gdb-5.0/] [sim/] [fr30/] [cpu.h] - Blame information for rev 1771

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1 106 markom
/* CPU family header for fr30bf.
2
 
3
THIS FILE IS MACHINE GENERATED WITH CGEN.
4
 
5
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6
 
7
This file is part of the GNU Simulators.
8
 
9
This program is free software; you can redistribute it and/or modify
10
it under the terms of the GNU General Public License as published by
11
the Free Software Foundation; either version 2, or (at your option)
12
any later version.
13
 
14
This program is distributed in the hope that it will be useful,
15
but WITHOUT ANY WARRANTY; without even the implied warranty of
16
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17
GNU General Public License for more details.
18
 
19
You should have received a copy of the GNU General Public License along
20
with this program; if not, write to the Free Software Foundation, Inc.,
21
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
 
23
*/
24
 
25
#ifndef CPU_FR30BF_H
26
#define CPU_FR30BF_H
27
 
28
/* Maximum number of instructions that are fetched at a time.
29
   This is for LIW type instructions sets (e.g. m32r).  */
30
#define MAX_LIW_INSNS 1
31
 
32
/* Maximum number of instructions that can be executed in parallel.  */
33
#define MAX_PARALLEL_INSNS 1
34
 
35
/* CPU state information.  */
36
typedef struct {
37
  /* Hardware elements.  */
38
  struct {
39
  /* program counter */
40
  USI h_pc;
41
#define GET_H_PC() CPU (h_pc)
42
#define SET_H_PC(x) (CPU (h_pc) = (x))
43
  /* general registers */
44
  SI h_gr[16];
45
#define GET_H_GR(a1) CPU (h_gr)[a1]
46
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47
  /* coprocessor registers */
48
  SI h_cr[16];
49
#define GET_H_CR(a1) CPU (h_cr)[a1]
50
#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
51
  /* dedicated registers */
52
  SI h_dr[6];
53
#define GET_H_DR(index) fr30bf_h_dr_get_handler (current_cpu, index)
54
#define SET_H_DR(index, x) \
55
do { \
56
fr30bf_h_dr_set_handler (current_cpu, (index), (x));\
57
} while (0)
58
  /* processor status */
59
  USI h_ps;
60
#define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu)
61
#define SET_H_PS(x) \
62
do { \
63
fr30bf_h_ps_set_handler (current_cpu, (x));\
64
} while (0)
65
  /* General Register 13 explicitly required */
66
  SI h_r13;
67
#define GET_H_R13() CPU (h_r13)
68
#define SET_H_R13(x) (CPU (h_r13) = (x))
69
  /* General Register 14 explicitly required */
70
  SI h_r14;
71
#define GET_H_R14() CPU (h_r14)
72
#define SET_H_R14(x) (CPU (h_r14) = (x))
73
  /* General Register 15 explicitly required */
74
  SI h_r15;
75
#define GET_H_R15() CPU (h_r15)
76
#define SET_H_R15(x) (CPU (h_r15) = (x))
77
  /* negative         bit */
78
  BI h_nbit;
79
#define GET_H_NBIT() CPU (h_nbit)
80
#define SET_H_NBIT(x) (CPU (h_nbit) = (x))
81
  /* zero             bit */
82
  BI h_zbit;
83
#define GET_H_ZBIT() CPU (h_zbit)
84
#define SET_H_ZBIT(x) (CPU (h_zbit) = (x))
85
  /* overflow         bit */
86
  BI h_vbit;
87
#define GET_H_VBIT() CPU (h_vbit)
88
#define SET_H_VBIT(x) (CPU (h_vbit) = (x))
89
  /* carry            bit */
90
  BI h_cbit;
91
#define GET_H_CBIT() CPU (h_cbit)
92
#define SET_H_CBIT(x) (CPU (h_cbit) = (x))
93
  /* interrupt enable bit */
94
  BI h_ibit;
95
#define GET_H_IBIT() CPU (h_ibit)
96
#define SET_H_IBIT(x) (CPU (h_ibit) = (x))
97
  /* stack bit */
98
  BI h_sbit;
99
#define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu)
100
#define SET_H_SBIT(x) \
101
do { \
102
fr30bf_h_sbit_set_handler (current_cpu, (x));\
103
} while (0)
104
  /* trace trap       bit */
105
  BI h_tbit;
106
#define GET_H_TBIT() CPU (h_tbit)
107
#define SET_H_TBIT(x) (CPU (h_tbit) = (x))
108
  /* division 0       bit */
109
  BI h_d0bit;
110
#define GET_H_D0BIT() CPU (h_d0bit)
111
#define SET_H_D0BIT(x) (CPU (h_d0bit) = (x))
112
  /* division 1       bit */
113
  BI h_d1bit;
114
#define GET_H_D1BIT() CPU (h_d1bit)
115
#define SET_H_D1BIT(x) (CPU (h_d1bit) = (x))
116
  /* condition code bits */
117
  UQI h_ccr;
118
#define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu)
119
#define SET_H_CCR(x) \
120
do { \
121
fr30bf_h_ccr_set_handler (current_cpu, (x));\
122
} while (0)
123
  /* system condition bits */
124
  UQI h_scr;
125
#define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu)
126
#define SET_H_SCR(x) \
127
do { \
128
fr30bf_h_scr_set_handler (current_cpu, (x));\
129
} while (0)
130
  /* interrupt level mask */
131
  UQI h_ilm;
132
#define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu)
133
#define SET_H_ILM(x) \
134
do { \
135
fr30bf_h_ilm_set_handler (current_cpu, (x));\
136
} while (0)
137
  } hardware;
138
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
139
} FR30BF_CPU_DATA;
140
 
141
/* Cover fns for register access.  */
142
USI fr30bf_h_pc_get (SIM_CPU *);
143
void fr30bf_h_pc_set (SIM_CPU *, USI);
144
SI fr30bf_h_gr_get (SIM_CPU *, UINT);
145
void fr30bf_h_gr_set (SIM_CPU *, UINT, SI);
146
SI fr30bf_h_cr_get (SIM_CPU *, UINT);
147
void fr30bf_h_cr_set (SIM_CPU *, UINT, SI);
148
SI fr30bf_h_dr_get (SIM_CPU *, UINT);
149
void fr30bf_h_dr_set (SIM_CPU *, UINT, SI);
150
USI fr30bf_h_ps_get (SIM_CPU *);
151
void fr30bf_h_ps_set (SIM_CPU *, USI);
152
SI fr30bf_h_r13_get (SIM_CPU *);
153
void fr30bf_h_r13_set (SIM_CPU *, SI);
154
SI fr30bf_h_r14_get (SIM_CPU *);
155
void fr30bf_h_r14_set (SIM_CPU *, SI);
156
SI fr30bf_h_r15_get (SIM_CPU *);
157
void fr30bf_h_r15_set (SIM_CPU *, SI);
158
BI fr30bf_h_nbit_get (SIM_CPU *);
159
void fr30bf_h_nbit_set (SIM_CPU *, BI);
160
BI fr30bf_h_zbit_get (SIM_CPU *);
161
void fr30bf_h_zbit_set (SIM_CPU *, BI);
162
BI fr30bf_h_vbit_get (SIM_CPU *);
163
void fr30bf_h_vbit_set (SIM_CPU *, BI);
164
BI fr30bf_h_cbit_get (SIM_CPU *);
165
void fr30bf_h_cbit_set (SIM_CPU *, BI);
166
BI fr30bf_h_ibit_get (SIM_CPU *);
167
void fr30bf_h_ibit_set (SIM_CPU *, BI);
168
BI fr30bf_h_sbit_get (SIM_CPU *);
169
void fr30bf_h_sbit_set (SIM_CPU *, BI);
170
BI fr30bf_h_tbit_get (SIM_CPU *);
171
void fr30bf_h_tbit_set (SIM_CPU *, BI);
172
BI fr30bf_h_d0bit_get (SIM_CPU *);
173
void fr30bf_h_d0bit_set (SIM_CPU *, BI);
174
BI fr30bf_h_d1bit_get (SIM_CPU *);
175
void fr30bf_h_d1bit_set (SIM_CPU *, BI);
176
UQI fr30bf_h_ccr_get (SIM_CPU *);
177
void fr30bf_h_ccr_set (SIM_CPU *, UQI);
178
UQI fr30bf_h_scr_get (SIM_CPU *);
179
void fr30bf_h_scr_set (SIM_CPU *, UQI);
180
UQI fr30bf_h_ilm_get (SIM_CPU *);
181
void fr30bf_h_ilm_set (SIM_CPU *, UQI);
182
 
183
/* These must be hand-written.  */
184
extern CPUREG_FETCH_FN fr30bf_fetch_register;
185
extern CPUREG_STORE_FN fr30bf_store_register;
186
 
187
typedef struct {
188
  UINT load_regs;
189
  UINT load_regs_pending;
190
} MODEL_FR30_1_DATA;
191
 
192
/* Instruction argument buffer.  */
193
 
194
union sem_fields {
195
  struct { /* no operands */
196
    int empty;
197
  } fmt_empty;
198
  struct { /*  */
199
    IADDR i_label9;
200
  } sfmt_brad;
201
  struct { /*  */
202
    UINT f_u8;
203
  } sfmt_int;
204
  struct { /*  */
205
    IADDR i_label12;
206
  } sfmt_call;
207
  struct { /*  */
208
    SI f_s10;
209
    unsigned char in_h_gr_15;
210
    unsigned char out_h_gr_15;
211
  } sfmt_addsp;
212
  struct { /*  */
213
    USI f_dir10;
214
    unsigned char in_h_gr_15;
215
    unsigned char out_h_gr_15;
216
  } sfmt_dmovr15pi;
217
  struct { /*  */
218
    UINT f_dir8;
219
    unsigned char in_h_gr_13;
220
    unsigned char out_h_gr_13;
221
  } sfmt_dmovr13pib;
222
  struct { /*  */
223
    USI f_dir9;
224
    unsigned char in_h_gr_13;
225
    unsigned char out_h_gr_13;
226
  } sfmt_dmovr13pih;
227
  struct { /*  */
228
    USI f_dir10;
229
    unsigned char in_h_gr_13;
230
    unsigned char out_h_gr_13;
231
  } sfmt_dmovr13pi;
232
  struct { /*  */
233
    SI* i_Ri;
234
    UINT f_Rs1;
235
    unsigned char in_Ri;
236
  } sfmt_mov2dr;
237
  struct { /*  */
238
    SI* i_Ri;
239
    UINT f_Rs1;
240
    unsigned char out_Ri;
241
  } sfmt_movdr;
242
  struct { /*  */
243
    UINT f_Rs2;
244
    unsigned char in_h_gr_15;
245
    unsigned char out_h_gr_15;
246
  } sfmt_ldr15dr;
247
  struct { /*  */
248
    SI* i_Ri;
249
    UINT f_i32;
250
    unsigned char out_Ri;
251
  } sfmt_ldi32;
252
  struct { /*  */
253
    SI* i_Ri;
254
    UINT f_i20;
255
    unsigned char out_Ri;
256
  } sfmt_ldi20;
257
  struct { /*  */
258
    SI* i_Ri;
259
    UINT f_i8;
260
    unsigned char out_Ri;
261
  } sfmt_ldi8;
262
  struct { /*  */
263
    SI* i_Ri;
264
    unsigned char in_Ri;
265
    unsigned char in_h_gr_15;
266
    unsigned char out_h_gr_15;
267
  } sfmt_str15gr;
268
  struct { /*  */
269
    SI* i_Ri;
270
    USI f_udisp6;
271
    unsigned char in_Ri;
272
    unsigned char in_h_gr_15;
273
  } sfmt_str15;
274
  struct { /*  */
275
    SI* i_Ri;
276
    INT f_disp8;
277
    unsigned char in_Ri;
278
    unsigned char in_h_gr_14;
279
  } sfmt_str14b;
280
  struct { /*  */
281
    SI* i_Ri;
282
    SI f_disp9;
283
    unsigned char in_Ri;
284
    unsigned char in_h_gr_14;
285
  } sfmt_str14h;
286
  struct { /*  */
287
    SI* i_Ri;
288
    SI f_disp10;
289
    unsigned char in_Ri;
290
    unsigned char in_h_gr_14;
291
  } sfmt_str14;
292
  struct { /*  */
293
    SI* i_Ri;
294
    USI f_udisp6;
295
    unsigned char in_h_gr_15;
296
    unsigned char out_Ri;
297
  } sfmt_ldr15;
298
  struct { /*  */
299
    SI* i_Ri;
300
    INT f_disp8;
301
    unsigned char in_h_gr_14;
302
    unsigned char out_Ri;
303
  } sfmt_ldr14ub;
304
  struct { /*  */
305
    SI* i_Ri;
306
    SI f_disp9;
307
    unsigned char in_h_gr_14;
308
    unsigned char out_Ri;
309
  } sfmt_ldr14uh;
310
  struct { /*  */
311
    SI* i_Ri;
312
    SI f_disp10;
313
    unsigned char in_h_gr_14;
314
    unsigned char out_Ri;
315
  } sfmt_ldr14;
316
  struct { /*  */
317
    SI* i_Ri;
318
    SI f_m4;
319
    unsigned char in_Ri;
320
    unsigned char out_Ri;
321
  } sfmt_add2;
322
  struct { /*  */
323
    SI* i_Ri;
324
    UINT f_u4;
325
    unsigned char in_Ri;
326
    unsigned char out_Ri;
327
  } sfmt_addi;
328
  struct { /*  */
329
    USI f_u10;
330
    unsigned char in_h_gr_14;
331
    unsigned char in_h_gr_15;
332
    unsigned char out_h_gr_14;
333
    unsigned char out_h_gr_15;
334
  } sfmt_enter;
335
  struct { /*  */
336
    SI* i_Ri;
337
    SI* i_Rj;
338
    unsigned char in_Ri;
339
    unsigned char in_Rj;
340
    unsigned char in_h_gr_13;
341
  } sfmt_str13;
342
  struct { /*  */
343
    SI* i_Ri;
344
    UINT f_Ri;
345
    unsigned char in_h_gr_15;
346
    unsigned char out_Ri;
347
    unsigned char out_h_gr_15;
348
  } sfmt_ldr15gr;
349
  struct { /*  */
350
    SI* i_Ri;
351
    SI* i_Rj;
352
    unsigned char in_Rj;
353
    unsigned char in_h_gr_13;
354
    unsigned char out_Ri;
355
  } sfmt_ldr13;
356
  struct { /*  */
357
    SI* i_Ri;
358
    SI* i_Rj;
359
    unsigned char in_Ri;
360
    unsigned char in_Rj;
361
    unsigned char out_Ri;
362
  } sfmt_add;
363
  struct { /*  */
364
    UINT f_reglist_hi_st;
365
    unsigned char in_h_gr_10;
366
    unsigned char in_h_gr_11;
367
    unsigned char in_h_gr_12;
368
    unsigned char in_h_gr_13;
369
    unsigned char in_h_gr_14;
370
    unsigned char in_h_gr_15;
371
    unsigned char in_h_gr_8;
372
    unsigned char in_h_gr_9;
373
    unsigned char out_h_gr_15;
374
  } sfmt_stm1;
375
  struct { /*  */
376
    UINT f_reglist_hi_ld;
377
    unsigned char in_h_gr_15;
378
    unsigned char out_h_gr_10;
379
    unsigned char out_h_gr_11;
380
    unsigned char out_h_gr_12;
381
    unsigned char out_h_gr_13;
382
    unsigned char out_h_gr_14;
383
    unsigned char out_h_gr_15;
384
    unsigned char out_h_gr_8;
385
    unsigned char out_h_gr_9;
386
  } sfmt_ldm1;
387
  struct { /*  */
388
    UINT f_reglist_low_st;
389
    unsigned char in_h_gr_0;
390
    unsigned char in_h_gr_1;
391
    unsigned char in_h_gr_15;
392
    unsigned char in_h_gr_2;
393
    unsigned char in_h_gr_3;
394
    unsigned char in_h_gr_4;
395
    unsigned char in_h_gr_5;
396
    unsigned char in_h_gr_6;
397
    unsigned char in_h_gr_7;
398
    unsigned char out_h_gr_15;
399
  } sfmt_stm0;
400
  struct { /*  */
401
    UINT f_reglist_low_ld;
402
    unsigned char in_h_gr_15;
403
    unsigned char out_h_gr_0;
404
    unsigned char out_h_gr_1;
405
    unsigned char out_h_gr_15;
406
    unsigned char out_h_gr_2;
407
    unsigned char out_h_gr_3;
408
    unsigned char out_h_gr_4;
409
    unsigned char out_h_gr_5;
410
    unsigned char out_h_gr_6;
411
    unsigned char out_h_gr_7;
412
  } sfmt_ldm0;
413
#if WITH_SCACHE_PBB
414
  /* Writeback handler.  */
415
  struct {
416
    /* Pointer to argbuf entry for insn whose results need writing back.  */
417
    const struct argbuf *abuf;
418
  } write;
419
  /* x-before handler */
420
  struct {
421
    /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
422
    int first_p;
423
  } before;
424
  /* x-after handler */
425
  struct {
426
    int empty;
427
  } after;
428
  /* This entry is used to terminate each pbb.  */
429
  struct {
430
    /* Number of insns in pbb.  */
431
    int insn_count;
432
    /* Next pbb to execute.  */
433
    SCACHE *next;
434
    SCACHE *branch_target;
435
  } chain;
436
#endif
437
};
438
 
439
/* The ARGBUF struct.  */
440
struct argbuf {
441
  /* These are the baseclass definitions.  */
442
  IADDR addr;
443
  const IDESC *idesc;
444
  char trace_p;
445
  char profile_p;
446
  /* ??? Temporary hack for skip insns.  */
447
  char skip_count;
448
  char unused;
449
  /* cpu specific data follows */
450
  union sem semantic;
451
  int written;
452
  union sem_fields fields;
453
};
454
 
455
/* A cached insn.
456
 
457
   ??? SCACHE used to contain more than just argbuf.  We could delete the
458
   type entirely and always just use ARGBUF, but for future concerns and as
459
   a level of abstraction it is left in.  */
460
 
461
struct scache {
462
  struct argbuf argbuf;
463
};
464
 
465
/* Macros to simplify extraction, reading and semantic code.
466
   These define and assign the local vars that contain the insn's fields.  */
467
 
468
#define EXTRACT_IFMT_EMPTY_VARS \
469
  unsigned int length;
470
#define EXTRACT_IFMT_EMPTY_CODE \
471
  length = 0; \
472
 
473
#define EXTRACT_IFMT_ADD_VARS \
474
  UINT f_op1; \
475
  UINT f_op2; \
476
  UINT f_Rj; \
477
  UINT f_Ri; \
478
  unsigned int length;
479
#define EXTRACT_IFMT_ADD_CODE \
480
  length = 2; \
481
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
482
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
483
  f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
484
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
485
 
486
#define EXTRACT_IFMT_ADDI_VARS \
487
  UINT f_op1; \
488
  UINT f_op2; \
489
  UINT f_u4; \
490
  UINT f_Ri; \
491
  unsigned int length;
492
#define EXTRACT_IFMT_ADDI_CODE \
493
  length = 2; \
494
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
495
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
496
  f_u4 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
497
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
498
 
499
#define EXTRACT_IFMT_ADD2_VARS \
500
  UINT f_op1; \
501
  UINT f_op2; \
502
  SI f_m4; \
503
  UINT f_Ri; \
504
  unsigned int length;
505
#define EXTRACT_IFMT_ADD2_CODE \
506
  length = 2; \
507
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
508
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
509
  f_m4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 4)) | (((-1) << (4)))); \
510
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
511
 
512
#define EXTRACT_IFMT_DIV0S_VARS \
513
  UINT f_op1; \
514
  UINT f_op2; \
515
  UINT f_op3; \
516
  UINT f_Ri; \
517
  unsigned int length;
518
#define EXTRACT_IFMT_DIV0S_CODE \
519
  length = 2; \
520
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
521
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
522
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
523
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
524
 
525
#define EXTRACT_IFMT_DIV3_VARS \
526
  UINT f_op1; \
527
  UINT f_op2; \
528
  UINT f_op3; \
529
  UINT f_op4; \
530
  unsigned int length;
531
#define EXTRACT_IFMT_DIV3_CODE \
532
  length = 2; \
533
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
534
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
535
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
536
  f_op4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
537
 
538
#define EXTRACT_IFMT_LDI8_VARS \
539
  UINT f_op1; \
540
  UINT f_i8; \
541
  UINT f_Ri; \
542
  unsigned int length;
543
#define EXTRACT_IFMT_LDI8_CODE \
544
  length = 2; \
545
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
546
  f_i8 = EXTRACT_MSB0_UINT (insn, 16, 4, 8); \
547
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
548
 
549
#define EXTRACT_IFMT_LDI20_VARS \
550
  UINT f_op1; \
551
  UINT f_i20_4; \
552
  UINT f_i20_16; \
553
  UINT f_i20; \
554
  UINT f_op2; \
555
  UINT f_Ri; \
556
  /* Contents of trailing part of insn.  */ \
557
  UINT word_1; \
558
  unsigned int length;
559
#define EXTRACT_IFMT_LDI20_CODE \
560
  length = 4; \
561
  word_1 = GETIMEMUHI (current_cpu, pc + 2); \
562
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
563
  f_i20_4 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
564
  f_i20_16 = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 16) << 0)); \
565
{\
566
  f_i20 = ((((f_i20_4) << (16))) | (f_i20_16));\
567
}\
568
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
569
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
570
 
571
#define EXTRACT_IFMT_LDI32_VARS \
572
  UINT f_op1; \
573
  UINT f_i32; \
574
  UINT f_op2; \
575
  UINT f_op3; \
576
  UINT f_Ri; \
577
  /* Contents of trailing part of insn.  */ \
578
  UINT word_1; \
579
  UINT word_2; \
580
  unsigned int length;
581
#define EXTRACT_IFMT_LDI32_CODE \
582
  length = 6; \
583
  word_1 = GETIMEMUHI (current_cpu, pc + 2); \
584
  word_2 = GETIMEMUHI (current_cpu, pc + 4); \
585
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
586
  f_i32 = (0|(EXTRACT_MSB0_UINT (word_2, 16, 0, 16) << 0)|(EXTRACT_MSB0_UINT (word_1, 16, 0, 16) << 16)); \
587
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
588
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
589
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
590
 
591
#define EXTRACT_IFMT_LDR14_VARS \
592
  UINT f_op1; \
593
  SI f_disp10; \
594
  UINT f_Ri; \
595
  unsigned int length;
596
#define EXTRACT_IFMT_LDR14_CODE \
597
  length = 2; \
598
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
599
  f_disp10 = ((EXTRACT_MSB0_INT (insn, 16, 4, 8)) << (2)); \
600
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
601
 
602
#define EXTRACT_IFMT_LDR14UH_VARS \
603
  UINT f_op1; \
604
  SI f_disp9; \
605
  UINT f_Ri; \
606
  unsigned int length;
607
#define EXTRACT_IFMT_LDR14UH_CODE \
608
  length = 2; \
609
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
610
  f_disp9 = ((EXTRACT_MSB0_INT (insn, 16, 4, 8)) << (1)); \
611
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
612
 
613
#define EXTRACT_IFMT_LDR14UB_VARS \
614
  UINT f_op1; \
615
  INT f_disp8; \
616
  UINT f_Ri; \
617
  unsigned int length;
618
#define EXTRACT_IFMT_LDR14UB_CODE \
619
  length = 2; \
620
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
621
  f_disp8 = EXTRACT_MSB0_INT (insn, 16, 4, 8); \
622
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
623
 
624
#define EXTRACT_IFMT_LDR15_VARS \
625
  UINT f_op1; \
626
  UINT f_op2; \
627
  USI f_udisp6; \
628
  UINT f_Ri; \
629
  unsigned int length;
630
#define EXTRACT_IFMT_LDR15_CODE \
631
  length = 2; \
632
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
633
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
634
  f_udisp6 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 4)) << (2)); \
635
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
636
 
637
#define EXTRACT_IFMT_LDR15DR_VARS \
638
  UINT f_op1; \
639
  UINT f_op2; \
640
  UINT f_op3; \
641
  UINT f_Rs2; \
642
  unsigned int length;
643
#define EXTRACT_IFMT_LDR15DR_CODE \
644
  length = 2; \
645
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
646
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
647
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
648
  f_Rs2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
649
 
650
#define EXTRACT_IFMT_MOVDR_VARS \
651
  UINT f_op1; \
652
  UINT f_op2; \
653
  UINT f_Rs1; \
654
  UINT f_Ri; \
655
  unsigned int length;
656
#define EXTRACT_IFMT_MOVDR_CODE \
657
  length = 2; \
658
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
659
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
660
  f_Rs1 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
661
  f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
662
 
663
#define EXTRACT_IFMT_CALL_VARS \
664
  UINT f_op1; \
665
  UINT f_op5; \
666
  SI f_rel12; \
667
  unsigned int length;
668
#define EXTRACT_IFMT_CALL_CODE \
669
  length = 2; \
670
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
671
  f_op5 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
672
  f_rel12 = ((((EXTRACT_MSB0_INT (insn, 16, 5, 11)) << (1))) + (((pc) + (2)))); \
673
 
674
#define EXTRACT_IFMT_INT_VARS \
675
  UINT f_op1; \
676
  UINT f_op2; \
677
  UINT f_u8; \
678
  unsigned int length;
679
#define EXTRACT_IFMT_INT_CODE \
680
  length = 2; \
681
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
682
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
683
  f_u8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
684
 
685
#define EXTRACT_IFMT_BRAD_VARS \
686
  UINT f_op1; \
687
  UINT f_cc; \
688
  SI f_rel9; \
689
  unsigned int length;
690
#define EXTRACT_IFMT_BRAD_CODE \
691
  length = 2; \
692
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
693
  f_cc = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
694
  f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); \
695
 
696
#define EXTRACT_IFMT_DMOVR13_VARS \
697
  UINT f_op1; \
698
  UINT f_op2; \
699
  USI f_dir10; \
700
  unsigned int length;
701
#define EXTRACT_IFMT_DMOVR13_CODE \
702
  length = 2; \
703
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
704
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
705
  f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
706
 
707
#define EXTRACT_IFMT_DMOVR13H_VARS \
708
  UINT f_op1; \
709
  UINT f_op2; \
710
  USI f_dir9; \
711
  unsigned int length;
712
#define EXTRACT_IFMT_DMOVR13H_CODE \
713
  length = 2; \
714
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
715
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
716
  f_dir9 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \
717
 
718
#define EXTRACT_IFMT_DMOVR13B_VARS \
719
  UINT f_op1; \
720
  UINT f_op2; \
721
  UINT f_dir8; \
722
  unsigned int length;
723
#define EXTRACT_IFMT_DMOVR13B_CODE \
724
  length = 2; \
725
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
726
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
727
  f_dir8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
728
 
729
#define EXTRACT_IFMT_COPOP_VARS \
730
  UINT f_op1; \
731
  UINT f_ccc; \
732
  UINT f_op2; \
733
  UINT f_op3; \
734
  UINT f_CRj; \
735
  UINT f_u4c; \
736
  UINT f_CRi; \
737
  /* Contents of trailing part of insn.  */ \
738
  UINT word_1; \
739
  unsigned int length;
740
#define EXTRACT_IFMT_COPOP_CODE \
741
  length = 4; \
742
  word_1 = GETIMEMUHI (current_cpu, pc + 2); \
743
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
744
  f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
745
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
746
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
747
  f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
748
  f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
749
  f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
750
 
751
#define EXTRACT_IFMT_COPLD_VARS \
752
  UINT f_op1; \
753
  UINT f_ccc; \
754
  UINT f_op2; \
755
  UINT f_op3; \
756
  UINT f_Rjc; \
757
  UINT f_u4c; \
758
  UINT f_CRi; \
759
  /* Contents of trailing part of insn.  */ \
760
  UINT word_1; \
761
  unsigned int length;
762
#define EXTRACT_IFMT_COPLD_CODE \
763
  length = 4; \
764
  word_1 = GETIMEMUHI (current_cpu, pc + 2); \
765
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
766
  f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
767
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
768
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
769
  f_Rjc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
770
  f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
771
  f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
772
 
773
#define EXTRACT_IFMT_COPST_VARS \
774
  UINT f_op1; \
775
  UINT f_ccc; \
776
  UINT f_op2; \
777
  UINT f_op3; \
778
  UINT f_CRj; \
779
  UINT f_u4c; \
780
  UINT f_Ric; \
781
  /* Contents of trailing part of insn.  */ \
782
  UINT word_1; \
783
  unsigned int length;
784
#define EXTRACT_IFMT_COPST_CODE \
785
  length = 4; \
786
  word_1 = GETIMEMUHI (current_cpu, pc + 2); \
787
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
788
  f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
789
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
790
  f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
791
  f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
792
  f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
793
  f_Ric = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
794
 
795
#define EXTRACT_IFMT_ADDSP_VARS \
796
  UINT f_op1; \
797
  UINT f_op2; \
798
  SI f_s10; \
799
  unsigned int length;
800
#define EXTRACT_IFMT_ADDSP_CODE \
801
  length = 2; \
802
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
803
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
804
  f_s10 = ((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2)); \
805
 
806
#define EXTRACT_IFMT_LDM0_VARS \
807
  UINT f_op1; \
808
  UINT f_op2; \
809
  UINT f_reglist_low_ld; \
810
  unsigned int length;
811
#define EXTRACT_IFMT_LDM0_CODE \
812
  length = 2; \
813
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
814
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
815
  f_reglist_low_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
816
 
817
#define EXTRACT_IFMT_LDM1_VARS \
818
  UINT f_op1; \
819
  UINT f_op2; \
820
  UINT f_reglist_hi_ld; \
821
  unsigned int length;
822
#define EXTRACT_IFMT_LDM1_CODE \
823
  length = 2; \
824
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
825
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
826
  f_reglist_hi_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
827
 
828
#define EXTRACT_IFMT_STM0_VARS \
829
  UINT f_op1; \
830
  UINT f_op2; \
831
  UINT f_reglist_low_st; \
832
  unsigned int length;
833
#define EXTRACT_IFMT_STM0_CODE \
834
  length = 2; \
835
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
836
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
837
  f_reglist_low_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
838
 
839
#define EXTRACT_IFMT_STM1_VARS \
840
  UINT f_op1; \
841
  UINT f_op2; \
842
  UINT f_reglist_hi_st; \
843
  unsigned int length;
844
#define EXTRACT_IFMT_STM1_CODE \
845
  length = 2; \
846
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
847
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
848
  f_reglist_hi_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
849
 
850
#define EXTRACT_IFMT_ENTER_VARS \
851
  UINT f_op1; \
852
  UINT f_op2; \
853
  USI f_u10; \
854
  unsigned int length;
855
#define EXTRACT_IFMT_ENTER_CODE \
856
  length = 2; \
857
  f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
858
  f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
859
  f_u10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
860
 
861
/* Collection of various things for the trace handler to use.  */
862
 
863
typedef struct trace_record {
864
  IADDR pc;
865
  /* FIXME:wip */
866
} TRACE_RECORD;
867
 
868
#endif /* CPU_FR30BF_H */

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