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/* collection of junk waiting time to sort out
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Copyright (C) 1998, 1999 Free Software Foundation, Inc.
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Contributed by Cygnus Solutions.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef FR30_SIM_H
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#define FR30_SIM_H
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/* gdb register numbers */
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#define PC_REGNUM 16
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#define PS_REGNUM 17
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#define TBR_REGNUM 18
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#define RP_REGNUM 19
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#define SSP_REGNUM 20
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#define USP_REGNUM 21
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#define MDH_REGNUM 22
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#define MDL_REGNUM 23
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extern BI fr30bf_h_sbit_get_handler (SIM_CPU *);
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extern void fr30bf_h_sbit_set_handler (SIM_CPU *, BI);
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extern UQI fr30bf_h_ccr_get_handler (SIM_CPU *);
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extern void fr30bf_h_ccr_set_handler (SIM_CPU *, UQI);
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extern UQI fr30bf_h_scr_get_handler (SIM_CPU *);
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extern void fr30bf_h_scr_set_handler (SIM_CPU *, UQI);
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extern UQI fr30bf_h_ilm_get_handler (SIM_CPU *);
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extern void fr30bf_h_ilm_set_handler (SIM_CPU *, UQI);
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extern USI fr30bf_h_ps_get_handler (SIM_CPU *);
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extern void fr30bf_h_ps_set_handler (SIM_CPU *, USI);
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extern SI fr30bf_h_dr_get_handler (SIM_CPU *, UINT);
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extern void fr30bf_h_dr_set_handler (SIM_CPU *, UINT, SI);
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#define GETTWI GETTSI
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#define SETTWI SETTSI
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/* Hardware/device support.
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??? Will eventually want to move device stuff to config files. */
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/* Special purpose traps. */
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#define TRAP_SYSCALL 10
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#define TRAP_BREAKPOINT 9
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/* Support for the MCCR register (Cache Control Register) is needed in order
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for overlays to work correctly with the scache: cached instructions need
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to be flushed when the instruction space is changed at runtime. */
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/* Cache Control Register */
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#define MCCR_ADDR 0xffffffff
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#define MCCR_CP 0x80
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/* not supported */
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#define MCCR_CM0 2
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#define MCCR_CM1 1
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/* Serial device addresses. */
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/* These are the values for the MSA2000 board.
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??? Will eventually need to move this to a config file. */
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#define UART_INCHAR_ADDR 0xff004009
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#define UART_OUTCHAR_ADDR 0xff004007
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#define UART_STATUS_ADDR 0xff004002
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#define UART_INPUT_READY 0x4
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#define UART_OUTPUT_READY 0x1
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/* Start address and length of all device support. */
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#define FR30_DEVICE_ADDR 0xff000000
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#define FR30_DEVICE_LEN 0x00ffffff
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/* sim_core_attach device argument. */
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extern device fr30_devices;
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/* FIXME: Temporary, until device support ready. */
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struct _device { int foo; };
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/* Handle the trap insn. */
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USI fr30_int (SIM_CPU *, PCADDR, int);
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#endif /* FR30_SIM_H */
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