OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [oc/] [gdb-5.0/] [sim/] [h8300/] [compile.c] - Blame information for rev 1771

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 106 markom
/*
2
 * Simulator for the Hitachi H8/300 architecture.
3
 *
4
 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
5
 *
6
 * This file is part of H8/300 sim
7
 *
8
 *
9
 * THIS SOFTWARE IS NOT COPYRIGHTED
10
 *
11
 * Cygnus offers the following for use in the public domain.  Cygnus makes no
12
 * warranty with regard to the software or its performance and the user
13
 * accepts the software "AS IS" with all faults.
14
 *
15
 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16
 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17
 * AND FITNESS FOR A PARTICULAR PURPOSE.
18
 */
19
 
20
#include "config.h"
21
 
22
#include <stdio.h>
23
#include <signal.h>
24
#ifdef HAVE_TIME_H
25
#include <time.h>
26
#endif
27
#ifdef HAVE_STDLIB_H
28
#include <stdlib.h>
29
#endif
30
#ifdef HAVE_SYS_PARAM_H
31
#include <sys/param.h>
32
#endif
33
#include "wait.h"
34
#include "ansidecl.h"
35
#include "bfd.h"
36
#include "callback.h"
37
#include "remote-sim.h"
38
 
39
#ifndef SIGTRAP
40
# define SIGTRAP 5
41
#endif
42
 
43
int debug;
44
 
45
host_callback *sim_callback;
46
 
47
static SIM_OPEN_KIND sim_kind;
48
static char *myname;
49
 
50
/* FIXME: Needs to live in header file.
51
   This header should also include the things in remote-sim.h.
52
   One could move this to remote-sim.h but this function isn't needed
53
   by gdb.  */
54
void sim_set_simcache_size PARAMS ((int));
55
 
56
#define X(op, size)  op*4+size
57
 
58
#define SP (h8300hmode ? SL:SW)
59
#define SB 0
60
#define SW 1
61
#define SL 2
62
#define OP_REG 1
63
#define OP_DEC 2
64
#define OP_DISP 3
65
#define OP_INC 4
66
#define OP_PCREL 5
67
#define OP_MEM 6
68
#define OP_CCR 7
69
#define OP_IMM 8
70
#define OP_ABS 10
71
#define h8_opcodes ops
72
#define DEFINE_TABLE
73
#include "opcode/h8300.h"
74
 
75
#include "inst.h"
76
 
77
/* The rate at which to call the host's poll_quit callback. */
78
 
79
#define POLL_QUIT_INTERVAL 0x80000
80
 
81
#define LOW_BYTE(x) ((x) & 0xff)
82
#define HIGH_BYTE(x) (((x)>>8) & 0xff)
83
#define P(X,Y) ((X<<8) | Y)
84
 
85
#define BUILDSR()   cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
86
 
87
#define GETSR()             \
88
  c = (cpu.ccr >> 0) & 1;\
89
  v = (cpu.ccr >> 1) & 1;\
90
  nz = !((cpu.ccr >> 2) & 1);\
91
  n = (cpu.ccr >> 3) & 1;
92
 
93
#ifdef __CHAR_IS_SIGNED__
94
#define SEXTCHAR(x) ((char)(x))
95
#endif
96
 
97
#ifndef SEXTCHAR
98
#define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
99
#endif
100
 
101
#define UEXTCHAR(x) ((x) & 0xff)
102
#define UEXTSHORT(x) ((x) & 0xffff)
103
#define SEXTSHORT(x) ((short)(x))
104
 
105
static cpu_state_type cpu;
106
 
107
int h8300hmode = 0;
108
int h8300smode = 0;
109
 
110
static int memory_size;
111
 
112
 
113
static int
114
get_now ()
115
{
116
#ifndef WIN32
117
  return time (0);
118
#endif
119
  return 0;
120
}
121
 
122
static int
123
now_persec ()
124
{
125
  return 1;
126
}
127
 
128
 
129
static int
130
bitfrom (x)
131
{
132
  switch (x & SIZE)
133
    {
134
    case L_8:
135
      return SB;
136
    case L_16:
137
      return SW;
138
    case L_32:
139
      return SL;
140
    case L_P:
141
      return h8300hmode ? SL : SW;
142
    }
143
}
144
 
145
static
146
unsigned int
147
lvalue (x, rn)
148
{
149
  switch (x / 4)
150
    {
151
    case OP_DISP:
152
      if (rn == 8)
153
        {
154
          return X (OP_IMM, SP);
155
        }
156
      return X (OP_REG, SP);
157
 
158
    case OP_MEM:
159
 
160
      return X (OP_MEM, SP);
161
    default:
162
      abort ();
163
    }
164
}
165
 
166
static unsigned int
167
decode (addr, data, dst)
168
     int addr;
169
     unsigned char *data;
170
     decoded_inst *dst;
171
 
172
{
173
  int rs = 0;
174
  int rd = 0;
175
  int rdisp = 0;
176
  int abs = 0;
177
  int plen = 0;
178
  int bit = 0;
179
 
180
  struct h8_opcode *q = h8_opcodes;
181
  int size = 0;
182
  dst->dst.type = -1;
183
  dst->src.type = -1;
184
  /* Find the exact opcode/arg combo */
185
  while (q->name)
186
    {
187
      op_type *nib;
188
      unsigned int len = 0;
189
 
190
      nib = q->data.nib;
191
 
192
      while (1)
193
        {
194
          op_type looking_for = *nib;
195
          int thisnib = data[len >> 1];
196
 
197
          thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
198
 
199
          if (looking_for < 16 && looking_for >= 0)
200
            {
201
              if (looking_for != thisnib)
202
                goto fail;
203
            }
204
          else
205
            {
206
              if ((int) looking_for & (int) B31)
207
                {
208
                  if (!(((int) thisnib & 0x8) != 0))
209
                    goto fail;
210
                  looking_for = (op_type) ((int) looking_for & ~(int)
211
                                           B31);
212
                  thisnib &= 0x7;
213
                }
214
              if ((int) looking_for & (int) B30)
215
                {
216
                  if (!(((int) thisnib & 0x8) == 0))
217
                    goto fail;
218
                  looking_for = (op_type) ((int) looking_for & ~(int) B30);
219
                }
220
              if (looking_for & DBIT)
221
                {
222
                  if ((looking_for & 5) != (thisnib & 5))
223
                    goto fail;
224
                  abs = (thisnib & 0x8) ? 2 : 1;
225
                }
226
              else if (looking_for & (REG | IND | INC | DEC))
227
                {
228
                  if (looking_for & REG)
229
                    {
230
                      /*
231
                       * Can work out size from the
232
                       * register
233
                       */
234
                      size = bitfrom (looking_for);
235
                    }
236
                  if (looking_for & SRC)
237
                    {
238
                      rs = thisnib;
239
                    }
240
                  else
241
                    {
242
                      rd = thisnib;
243
                    }
244
                }
245
              else if (looking_for & L_16)
246
                {
247
                  abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
248
                  plen = 16;
249
                  if (looking_for & (PCREL | DISP))
250
                    {
251
                      abs = (short) (abs);
252
                    }
253
                }
254
              else if (looking_for & ABSJMP)
255
                {
256
                  abs =
257
                    (data[1] << 16)
258
                    | (data[2] << 8)
259
                    | (data[3]);
260
                }
261
              else if (looking_for & MEMIND)
262
                {
263
                  abs = data[1];
264
                }
265
              else if (looking_for & L_32)
266
                {
267
                  int i = len >> 1;
268
                  abs = (data[i] << 24)
269
                    | (data[i + 1] << 16)
270
                    | (data[i + 2] << 8)
271
                    | (data[i + 3]);
272
 
273
                  plen = 32;
274
                }
275
              else if (looking_for & L_24)
276
                {
277
                  int i = len >> 1;
278
                  abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
279
                  plen = 24;
280
                }
281
              else if (looking_for & IGNORE)
282
                {
283
                  /* nothing to do */
284
                }
285
              else if (looking_for & DISPREG)
286
                {
287
                  rdisp = thisnib & 0x7;
288
                }
289
              else if (looking_for & KBIT)
290
                {
291
                  switch (thisnib)
292
                    {
293
                    case 9:
294
                      abs = 4;
295
                      break;
296
                    case 8:
297
                      abs = 2;
298
                      break;
299
                    case 0:
300
                      abs = 1;
301
                      break;
302
                    }
303
                }
304
              else if (looking_for & L_8)
305
                {
306
                  plen = 8;
307
 
308
                  if (looking_for & PCREL)
309
                    {
310
                      abs = SEXTCHAR (data[len >> 1]);
311
                    }
312
                  else if (looking_for & ABS8MEM)
313
                    {
314
                      plen = 8;
315
                      abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
316
                      abs |= data[len >> 1] & 0xff ;
317
                    }
318
                   else
319
                    {
320
                      abs = data[len >> 1] & 0xff;
321
                    }
322
                }
323
              else if (looking_for & L_3)
324
                {
325
                  plen = 3;
326
 
327
                  bit = thisnib;
328
                }
329
              else if (looking_for == E)
330
                {
331
                  dst->op = q;
332
 
333
                  /* Fill in the args */
334
                  {
335
                    op_type *args = q->args.nib;
336
                    int hadone = 0;
337
 
338
                    while (*args != E)
339
                      {
340
                        int x = *args;
341
                        int rn = (x & DST) ? rd : rs;
342
                        ea_type *p;
343
 
344
                        if (x & DST)
345
                          {
346
                            p = &(dst->dst);
347
                          }
348
                        else
349
                          {
350
                            p = &(dst->src);
351
                          }
352
 
353
                        if (x & (L_3))
354
                          {
355
                            p->type = X (OP_IMM, size);
356
                            p->literal = bit;
357
                          }
358
                        else if (x & (IMM | KBIT | DBIT))
359
                          {
360
                            p->type = X (OP_IMM, size);
361
                            p->literal = abs;
362
                          }
363
                        else if (x & REG)
364
                          {
365
                            /* Reset the size, some
366
                               ops (like mul) have two sizes */
367
 
368
                            size = bitfrom (x);
369
                            p->type = X (OP_REG, size);
370
                            p->reg = rn;
371
                          }
372
                        else if (x & INC)
373
                          {
374
                            p->type = X (OP_INC, size);
375
                            p->reg = rn & 0x7;
376
                          }
377
                        else if (x & DEC)
378
                          {
379
                            p->type = X (OP_DEC, size);
380
                            p->reg = rn & 0x7;
381
                          }
382
                        else if (x & IND)
383
                          {
384
                            p->type = X (OP_DISP, size);
385
                            p->reg = rn & 0x7;
386
                            p->literal = 0;
387
                          }
388
                        else if (x & (ABS | ABSJMP | ABS8MEM))
389
                          {
390
                            p->type = X (OP_DISP, size);
391
                            p->literal = abs;
392
                            p->reg = 8;
393
                          }
394
                        else if (x & MEMIND)
395
                          {
396
                            p->type = X (OP_MEM, size);
397
                            p->literal = abs;
398
                          }
399
                        else if (x & PCREL)
400
                          {
401
                            p->type = X (OP_PCREL, size);
402
                            p->literal = abs + addr + 2;
403
                            if (x & L_16)
404
                              p->literal += 2;
405
                          }
406
                        else if (x & ABSJMP)
407
                          {
408
                            p->type = X (OP_IMM, SP);
409
                            p->literal = abs;
410
                          }
411
                        else if (x & DISP)
412
                          {
413
                            p->type = X (OP_DISP, size);
414
                            p->literal = abs;
415
                            p->reg = rdisp & 0x7;
416
                          }
417
                        else if (x & CCR)
418
                          {
419
                            p->type = OP_CCR;
420
                          }
421
                        else
422
                          printf ("Hmmmm %x", x);
423
 
424
                        args++;
425
                      }
426
                  }
427
 
428
                  /*
429
                     * But a jmp or a jsr gets
430
                     * automagically lvalued, since we
431
                     * branch to their address not their
432
                     * contents
433
                   */
434
                  if (q->how == O (O_JSR, SB)
435
                      || q->how == O (O_JMP, SB))
436
                    {
437
                      dst->src.type = lvalue (dst->src.type, dst->src.reg);
438
                    }
439
 
440
                  if (dst->dst.type == -1)
441
                    dst->dst = dst->src;
442
 
443
                  dst->opcode = q->how;
444
                  dst->cycles = q->time;
445
 
446
                  /* And a jsr to 0xc4 is turned into a magic trap */
447
 
448
                  if (dst->opcode == O (O_JSR, SB))
449
                    {
450
                      if (dst->src.literal == 0xc4)
451
                        {
452
                          dst->opcode = O (O_SYSCALL, SB);
453
                        }
454
                    }
455
 
456
                  dst->next_pc = addr + len / 2;
457
                  return;
458
                }
459
              else
460
                {
461
                  printf ("Dont understand %x \n", looking_for);
462
                }
463
            }
464
 
465
          len++;
466
          nib++;
467
        }
468
 
469
    fail:
470
      q++;
471
    }
472
 
473
  dst->opcode = O (O_ILL, SB);
474
}
475
 
476
 
477
static void
478
compile (pc)
479
{
480
  int idx;
481
 
482
  /* find the next cache entry to use */
483
 
484
  idx = cpu.cache_top + 1;
485
  cpu.compiles++;
486
  if (idx >= cpu.csize)
487
    {
488
      idx = 1;
489
    }
490
  cpu.cache_top = idx;
491
 
492
  /* Throw away its old meaning */
493
  cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
494
 
495
  /* set to new address */
496
  cpu.cache[idx].oldpc = pc;
497
 
498
  /* fill in instruction info */
499
  decode (pc, cpu.memory + pc, cpu.cache + idx);
500
 
501
  /* point to new cache entry */
502
  cpu.cache_idx[pc] = idx;
503
}
504
 
505
 
506
static unsigned char *breg[18];
507
static unsigned short *wreg[18];
508
static unsigned int *lreg[18];
509
 
510
#define GET_B_REG(x) *(breg[x])
511
#define SET_B_REG(x,y) (*(breg[x])) = (y)
512
#define GET_W_REG(x) *(wreg[x])
513
#define SET_W_REG(x,y) (*(wreg[x])) = (y)
514
 
515
#define GET_L_REG(x) *(lreg[x])
516
#define SET_L_REG(x,y) (*(lreg[x])) = (y)
517
 
518
#define GET_MEMORY_L(x) \
519
  (x < memory_size \
520
   ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
521
      | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
522
   : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
523
      | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
524
 
525
#define GET_MEMORY_W(x) \
526
  (x < memory_size \
527
   ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
528
   : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
529
 
530
 
531
#define GET_MEMORY_B(x) \
532
  (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
533
 
534
#define SET_MEMORY_L(x,y)  \
535
{  register unsigned char *_p; register int __y = y; \
536
   _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
537
   _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
538
   _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
539
 
540
#define SET_MEMORY_W(x,y) \
541
{  register unsigned char *_p; register int __y = y; \
542
   _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
543
   _p[0] = (__y)>>8; _p[1] =(__y);}
544
 
545
#define SET_MEMORY_B(x,y) \
546
  (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
547
 
548
int
549
fetch (arg, n)
550
     ea_type *arg;
551
{
552
  int rn = arg->reg;
553
  int abs = arg->literal;
554
  int r;
555
  int t;
556
 
557
  switch (arg->type)
558
    {
559
    case X (OP_REG, SB):
560
      return GET_B_REG (rn);
561
    case X (OP_REG, SW):
562
      return GET_W_REG (rn);
563
    case X (OP_REG, SL):
564
      return GET_L_REG (rn);
565
    case X (OP_IMM, SB):
566
    case X (OP_IMM, SW):
567
    case X (OP_IMM, SL):
568
      return abs;
569
    case X (OP_DEC, SB):
570
      abort ();
571
 
572
    case X (OP_INC, SB):
573
      t = GET_L_REG (rn);
574
      t &= cpu.mask;
575
      r = GET_MEMORY_B (t);
576
      t++;
577
      t = t & cpu.mask;
578
      SET_L_REG (rn, t);
579
      return r;
580
      break;
581
    case X (OP_INC, SW):
582
      t = GET_L_REG (rn);
583
      t &= cpu.mask;
584
      r = GET_MEMORY_W (t);
585
      t += 2;
586
      t = t & cpu.mask;
587
      SET_L_REG (rn, t);
588
      return r;
589
    case X (OP_INC, SL):
590
      t = GET_L_REG (rn);
591
      t &= cpu.mask;
592
      r = GET_MEMORY_L (t);
593
 
594
      t += 4;
595
      t = t & cpu.mask;
596
      SET_L_REG (rn, t);
597
      return r;
598
 
599
    case X (OP_DISP, SB):
600
      t = GET_L_REG (rn) + abs;
601
      t &= cpu.mask;
602
      return GET_MEMORY_B (t);
603
 
604
    case X (OP_DISP, SW):
605
      t = GET_L_REG (rn) + abs;
606
      t &= cpu.mask;
607
      return GET_MEMORY_W (t);
608
 
609
    case X (OP_DISP, SL):
610
      t = GET_L_REG (rn) + abs;
611
      t &= cpu.mask;
612
      return GET_MEMORY_L (t);
613
 
614
    case X (OP_MEM, SL):
615
      t = GET_MEMORY_L (abs);
616
      t &= cpu.mask;
617
      return t;
618
 
619
    case X (OP_MEM, SW):
620
      t = GET_MEMORY_W (abs);
621
      t &= cpu.mask;
622
      return t;
623
 
624
    default:
625
      abort ();
626
 
627
    }
628
}
629
 
630
 
631
static
632
void
633
store (arg, n)
634
     ea_type *arg;
635
     int n;
636
{
637
  int rn = arg->reg;
638
  int abs = arg->literal;
639
  int t;
640
 
641
  switch (arg->type)
642
    {
643
    case X (OP_REG, SB):
644
      SET_B_REG (rn, n);
645
      break;
646
    case X (OP_REG, SW):
647
      SET_W_REG (rn, n);
648
      break;
649
    case X (OP_REG, SL):
650
      SET_L_REG (rn, n);
651
      break;
652
 
653
    case X (OP_DEC, SB):
654
      t = GET_L_REG (rn) - 1;
655
      t &= cpu.mask;
656
      SET_L_REG (rn, t);
657
      SET_MEMORY_B (t, n);
658
 
659
      break;
660
    case X (OP_DEC, SW):
661
      t = (GET_L_REG (rn) - 2) & cpu.mask;
662
      SET_L_REG (rn, t);
663
      SET_MEMORY_W (t, n);
664
      break;
665
 
666
    case X (OP_DEC, SL):
667
      t = (GET_L_REG (rn) - 4) & cpu.mask;
668
      SET_L_REG (rn, t);
669
      SET_MEMORY_L (t, n);
670
      break;
671
 
672
    case X (OP_DISP, SB):
673
      t = GET_L_REG (rn) + abs;
674
      t &= cpu.mask;
675
      SET_MEMORY_B (t, n);
676
      break;
677
 
678
    case X (OP_DISP, SW):
679
      t = GET_L_REG (rn) + abs;
680
      t &= cpu.mask;
681
      SET_MEMORY_W (t, n);
682
      break;
683
 
684
    case X (OP_DISP, SL):
685
      t = GET_L_REG (rn) + abs;
686
      t &= cpu.mask;
687
      SET_MEMORY_L (t, n);
688
      break;
689
    default:
690
      abort ();
691
    }
692
}
693
 
694
 
695
static union
696
{
697
  short int i;
698
  struct
699
    {
700
      char low;
701
      char high;
702
    }
703
  u;
704
}
705
 
706
littleendian;
707
 
708
static
709
void
710
init_pointers ()
711
{
712
  static int init;
713
 
714
  if (!init)
715
    {
716
      int i;
717
 
718
      init = 1;
719
      littleendian.i = 1;
720
 
721
      if (h8300hmode)
722
        memory_size = H8300H_MSIZE;
723
      else
724
        memory_size = H8300_MSIZE;
725
      cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
726
      cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
727
      cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
728
 
729
      /* `msize' must be a power of two */
730
      if ((memory_size & (memory_size - 1)) != 0)
731
        abort ();
732
      cpu.mask = memory_size - 1;
733
 
734
      for (i = 0; i < 9; i++)
735
        {
736
          cpu.regs[i] = 0;
737
        }
738
 
739
      for (i = 0; i < 8; i++)
740
        {
741
          unsigned char *p = (unsigned char *) (cpu.regs + i);
742
          unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
743
          unsigned short *q = (unsigned short *) (cpu.regs + i);
744
          unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
745
          cpu.regs[i] = 0x00112233;
746
          while (p < e)
747
            {
748
              if (*p == 0x22)
749
                {
750
                  breg[i] = p;
751
                }
752
              if (*p == 0x33)
753
                {
754
                  breg[i + 8] = p;
755
                }
756
              p++;
757
            }
758
          while (q < u)
759
            {
760
              if (*q == 0x2233)
761
                {
762
                  wreg[i] = q;
763
                }
764
              if (*q == 0x0011)
765
                {
766
                  wreg[i + 8] = q;
767
                }
768
              q++;
769
            }
770
          cpu.regs[i] = 0;
771
          lreg[i] = &cpu.regs[i];
772
        }
773
 
774
      lreg[8] = &cpu.regs[8];
775
 
776
      /* initialize the seg registers */
777
      if (!cpu.cache)
778
        sim_set_simcache_size (CSIZE);
779
    }
780
}
781
 
782
static void
783
control_c (sig, code, scp, addr)
784
     int sig;
785
     int code;
786
     char *scp;
787
     char *addr;
788
{
789
  cpu.state = SIM_STATE_STOPPED;
790
  cpu.exception = SIGINT;
791
}
792
 
793
#define C (c != 0)
794
#define Z (nz == 0)
795
#define V (v != 0)
796
#define N (n != 0)
797
 
798
static int
799
mop (code, bsize, sign)
800
     decoded_inst *code;
801
     int bsize;
802
     int sign;
803
{
804
  int multiplier;
805
  int multiplicand;
806
  int result;
807
  int n, nz;
808
 
809
  if (sign)
810
    {
811
      multiplicand =
812
        bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
813
        SEXTSHORT (GET_W_REG (code->dst.reg));
814
      multiplier =
815
        bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
816
        SEXTSHORT (GET_W_REG (code->src.reg));
817
    }
818
  else
819
    {
820
      multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
821
        UEXTSHORT (GET_W_REG (code->dst.reg));
822
      multiplier =
823
        bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
824
        UEXTSHORT (GET_W_REG (code->src.reg));
825
 
826
    }
827
  result = multiplier * multiplicand;
828
 
829
  if (sign)
830
    {
831
      n = result & (bsize ? 0x8000 : 0x80000000);
832
      nz = result & (bsize ? 0xffff : 0xffffffff);
833
    }
834
  if (bsize)
835
    {
836
      SET_W_REG (code->dst.reg, result);
837
    }
838
  else
839
    {
840
      SET_L_REG (code->dst.reg, result);
841
    }
842
/*  return ((n==1) << 1) | (nz==1); */
843
 
844
}
845
 
846
#define ONOT(name, how) \
847
case O(name, SB):                               \
848
{                                               \
849
  int t;                                        \
850
  int hm = 0x80;                                \
851
  rd = GET_B_REG (code->src.reg);               \
852
  how;                                          \
853
  goto shift8;                                  \
854
}                                               \
855
case O(name, SW):                               \
856
{                                               \
857
  int t;                                        \
858
  int hm = 0x8000;                              \
859
  rd = GET_W_REG (code->src.reg);               \
860
  how;                                          \
861
  goto shift16;                                 \
862
}                                               \
863
case O(name, SL):                               \
864
{                                               \
865
  int t;                                        \
866
  int hm = 0x80000000;                          \
867
  rd = GET_L_REG (code->src.reg);               \
868
  how;                                          \
869
  goto shift32;                                 \
870
}
871
 
872
#define OSHIFTS(name, how1, how2) \
873
case O(name, SB):                               \
874
{                                               \
875
  int t;                                        \
876
  int hm = 0x80;                                \
877
  rd = GET_B_REG (code->src.reg);               \
878
  if ((GET_MEMORY_B (pc + 1) & 0x40) == 0)       \
879
    {                                           \
880
      how1;                                     \
881
    }                                           \
882
  else                                          \
883
    {                                           \
884
      how2;                                     \
885
    }                                           \
886
  goto shift8;                                  \
887
}                                               \
888
case O(name, SW):                               \
889
{                                               \
890
  int t;                                        \
891
  int hm = 0x8000;                              \
892
  rd = GET_W_REG (code->src.reg);               \
893
  if ((GET_MEMORY_B (pc + 1) & 0x40) == 0)       \
894
    {                                           \
895
      how1;                                     \
896
    }                                           \
897
  else                                          \
898
    {                                           \
899
      how2;                                     \
900
    }                                           \
901
  goto shift16;                                 \
902
}                                               \
903
case O(name, SL):                               \
904
{                                               \
905
  int t;                                        \
906
  int hm = 0x80000000;                          \
907
  rd = GET_L_REG (code->src.reg);               \
908
  if ((GET_MEMORY_B (pc + 1) & 0x40) == 0)       \
909
    {                                           \
910
      how1;                                     \
911
    }                                           \
912
  else                                          \
913
    {                                           \
914
      how2;                                     \
915
    }                                           \
916
  goto shift32;                                 \
917
}
918
 
919
#define OBITOP(name,f, s, op)                   \
920
case  O(name, SB):                              \
921
{                                               \
922
  int m;                                        \
923
  int b;                                        \
924
  if (f) ea = fetch (&code->dst);               \
925
  m=1<< fetch(&code->src);                      \
926
  op;                                           \
927
  if(s) store (&code->dst,ea); goto next;       \
928
}
929
 
930
int
931
sim_stop (sd)
932
     SIM_DESC sd;
933
{
934
  cpu.state = SIM_STATE_STOPPED;
935
  cpu.exception = SIGINT;
936
  return 1;
937
}
938
 
939
void
940
sim_resume (sd, step, siggnal)
941
     SIM_DESC sd;
942
{
943
  static int init1;
944
  int cycles = 0;
945
  int insts = 0;
946
  int tick_start = get_now ();
947
  void (*prev) ();
948
  int poll_count = 0;
949
  int res;
950
  int tmp;
951
  int rd;
952
  int ea;
953
  int bit;
954
  int pc;
955
  int c, nz, v, n;
956
  int oldmask;
957
  init_pointers ();
958
 
959
  prev = signal (SIGINT, control_c);
960
 
961
  if (step)
962
    {
963
      cpu.state = SIM_STATE_STOPPED;
964
      cpu.exception = SIGTRAP;
965
    }
966
  else
967
    {
968
      cpu.state = SIM_STATE_RUNNING;
969
      cpu.exception = 0;
970
    }
971
 
972
  pc = cpu.pc;
973
 
974
  /* The PC should never be odd.  */
975
  if (pc & 0x1)
976
    abort ();
977
 
978
  GETSR ();
979
  oldmask = cpu.mask;
980
  if (!h8300hmode)
981
    cpu.mask = 0xffff;
982
  do
983
    {
984
      int cidx;
985
      decoded_inst *code;
986
 
987
    top:
988
      cidx = cpu.cache_idx[pc];
989
      code = cpu.cache + cidx;
990
 
991
 
992
#define ALUOP(STORE, NAME, HOW) \
993
    case O(NAME,SB):  HOW; if(STORE)goto alu8;else goto just_flags_alu8;  \
994
    case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
995
    case O(NAME,SL):  HOW; if(STORE)goto alu32;else goto just_flags_alu32;
996
 
997
 
998
#define LOGOP(NAME, HOW) \
999
    case O(NAME,SB): HOW; goto log8;\
1000
    case O(NAME, SW): HOW; goto log16;\
1001
    case O(NAME,SL): HOW; goto log32;
1002
 
1003
 
1004
 
1005
#if ADEBUG
1006
      if (debug)
1007
        {
1008
          printf ("%x %d %s\n", pc, code->opcode,
1009
                  code->op ? code->op->name : "**");
1010
        }
1011
      cpu.stats[code->opcode]++;
1012
 
1013
#endif
1014
 
1015
      cycles += code->cycles;
1016
      insts++;
1017
      switch (code->opcode)
1018
        {
1019
        case 0:
1020
          /*
1021
           * This opcode is a fake for when we get to an
1022
           * instruction which hasnt been compiled
1023
           */
1024
          compile (pc);
1025
          goto top;
1026
          break;
1027
 
1028
 
1029
        case O (O_SUBX, SB):
1030
          rd = fetch (&code->dst);
1031
          ea = fetch (&code->src);
1032
          ea = -(ea + C);
1033
          res = rd + ea;
1034
          goto alu8;
1035
 
1036
        case O (O_ADDX, SB):
1037
          rd = fetch (&code->dst);
1038
          ea = fetch (&code->src);
1039
          ea = C + ea;
1040
          res = rd + ea;
1041
          goto alu8;
1042
 
1043
#define EA    ea = fetch(&code->src);
1044
#define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1045
 
1046
          ALUOP (1, O_SUB, RD_EA;
1047
                 ea = -ea;
1048
                 res = rd + ea);
1049
          ALUOP (1, O_NEG, EA;
1050
                 ea = -ea;
1051
                 rd = 0;
1052
                 res = rd + ea);
1053
 
1054
        case O (O_ADD, SB):
1055
          rd = GET_B_REG (code->dst.reg);
1056
          ea = fetch (&code->src);
1057
          res = rd + ea;
1058
          goto alu8;
1059
        case O (O_ADD, SW):
1060
          rd = GET_W_REG (code->dst.reg);
1061
          ea = fetch (&code->src);
1062
          res = rd + ea;
1063
          goto alu16;
1064
        case O (O_ADD, SL):
1065
          rd = GET_L_REG (code->dst.reg);
1066
          ea = fetch (&code->src);
1067
          res = rd + ea;
1068
          goto alu32;
1069
 
1070
 
1071
          LOGOP (O_AND, RD_EA;
1072
                 res = rd & ea);
1073
 
1074
          LOGOP (O_OR, RD_EA;
1075
                 res = rd | ea);
1076
 
1077
          LOGOP (O_XOR, RD_EA;
1078
                 res = rd ^ ea);
1079
 
1080
 
1081
        case O (O_MOV_TO_MEM, SB):
1082
          res = GET_B_REG (code->src.reg);
1083
          goto log8;
1084
        case O (O_MOV_TO_MEM, SW):
1085
          res = GET_W_REG (code->src.reg);
1086
          goto log16;
1087
        case O (O_MOV_TO_MEM, SL):
1088
          res = GET_L_REG (code->src.reg);
1089
          goto log32;
1090
 
1091
 
1092
        case O (O_MOV_TO_REG, SB):
1093
          res = fetch (&code->src);
1094
          SET_B_REG (code->dst.reg, res);
1095
          goto just_flags_log8;
1096
        case O (O_MOV_TO_REG, SW):
1097
          res = fetch (&code->src);
1098
          SET_W_REG (code->dst.reg, res);
1099
          goto just_flags_log16;
1100
        case O (O_MOV_TO_REG, SL):
1101
          res = fetch (&code->src);
1102
          SET_L_REG (code->dst.reg, res);
1103
          goto just_flags_log32;
1104
 
1105
 
1106
        case O (O_ADDS, SL):
1107
          SET_L_REG (code->dst.reg,
1108
                     GET_L_REG (code->dst.reg)
1109
                     + code->src.literal);
1110
 
1111
          goto next;
1112
 
1113
        case O (O_SUBS, SL):
1114
          SET_L_REG (code->dst.reg,
1115
                     GET_L_REG (code->dst.reg)
1116
                     - code->src.literal);
1117
          goto next;
1118
 
1119
        case O (O_CMP, SB):
1120
          rd = fetch (&code->dst);
1121
          ea = fetch (&code->src);
1122
          ea = -ea;
1123
          res = rd + ea;
1124
          goto just_flags_alu8;
1125
 
1126
        case O (O_CMP, SW):
1127
          rd = fetch (&code->dst);
1128
          ea = fetch (&code->src);
1129
          ea = -ea;
1130
          res = rd + ea;
1131
          goto just_flags_alu16;
1132
 
1133
        case O (O_CMP, SL):
1134
          rd = fetch (&code->dst);
1135
          ea = fetch (&code->src);
1136
          ea = -ea;
1137
          res = rd + ea;
1138
          goto just_flags_alu32;
1139
 
1140
 
1141
        case O (O_DEC, SB):
1142
          rd = GET_B_REG (code->src.reg);
1143
          ea = -1;
1144
          res = rd + ea;
1145
          SET_B_REG (code->src.reg, res);
1146
          goto just_flags_inc8;
1147
 
1148
        case O (O_DEC, SW):
1149
          rd = GET_W_REG (code->dst.reg);
1150
          ea = -code->src.literal;
1151
          res = rd + ea;
1152
          SET_W_REG (code->dst.reg, res);
1153
          goto just_flags_inc16;
1154
 
1155
        case O (O_DEC, SL):
1156
          rd = GET_L_REG (code->dst.reg);
1157
          ea = -code->src.literal;
1158
          res = rd + ea;
1159
          SET_L_REG (code->dst.reg, res);
1160
          goto just_flags_inc32;
1161
 
1162
 
1163
        case O (O_INC, SB):
1164
          rd = GET_B_REG (code->src.reg);
1165
          ea = 1;
1166
          res = rd + ea;
1167
          SET_B_REG (code->src.reg, res);
1168
          goto just_flags_inc8;
1169
 
1170
        case O (O_INC, SW):
1171
          rd = GET_W_REG (code->dst.reg);
1172
          ea = code->src.literal;
1173
          res = rd + ea;
1174
          SET_W_REG (code->dst.reg, res);
1175
          goto just_flags_inc16;
1176
 
1177
        case O (O_INC, SL):
1178
          rd = GET_L_REG (code->dst.reg);
1179
          ea = code->src.literal;
1180
          res = rd + ea;
1181
          SET_L_REG (code->dst.reg, res);
1182
          goto just_flags_inc32;
1183
 
1184
 
1185
#define GET_CCR(x) BUILDSR();x = cpu.ccr
1186
 
1187
        case O (O_ANDC, SB):
1188
          GET_CCR (rd);
1189
          ea = code->src.literal;
1190
          res = rd & ea;
1191
          goto setc;
1192
 
1193
        case O (O_ORC, SB):
1194
          GET_CCR (rd);
1195
          ea = code->src.literal;
1196
          res = rd | ea;
1197
          goto setc;
1198
 
1199
        case O (O_XORC, SB):
1200
          GET_CCR (rd);
1201
          ea = code->src.literal;
1202
          res = rd ^ ea;
1203
          goto setc;
1204
 
1205
 
1206
        case O (O_BRA, SB):
1207
          if (1)
1208
            goto condtrue;
1209
          goto next;
1210
 
1211
        case O (O_BRN, SB):
1212
          if (0)
1213
            goto condtrue;
1214
          goto next;
1215
 
1216
        case O (O_BHI, SB):
1217
          if ((C || Z) == 0)
1218
            goto condtrue;
1219
          goto next;
1220
 
1221
 
1222
        case O (O_BLS, SB):
1223
          if ((C || Z))
1224
            goto condtrue;
1225
          goto next;
1226
 
1227
        case O (O_BCS, SB):
1228
          if ((C == 1))
1229
            goto condtrue;
1230
          goto next;
1231
 
1232
        case O (O_BCC, SB):
1233
          if ((C == 0))
1234
            goto condtrue;
1235
          goto next;
1236
 
1237
        case O (O_BEQ, SB):
1238
          if (Z)
1239
            goto condtrue;
1240
          goto next;
1241
        case O (O_BGT, SB):
1242
          if (((Z || (N ^ V)) == 0))
1243
            goto condtrue;
1244
          goto next;
1245
 
1246
 
1247
        case O (O_BLE, SB):
1248
          if (((Z || (N ^ V)) == 1))
1249
            goto condtrue;
1250
          goto next;
1251
 
1252
        case O (O_BGE, SB):
1253
          if ((N ^ V) == 0)
1254
            goto condtrue;
1255
          goto next;
1256
        case O (O_BLT, SB):
1257
          if ((N ^ V))
1258
            goto condtrue;
1259
          goto next;
1260
        case O (O_BMI, SB):
1261
          if ((N))
1262
            goto condtrue;
1263
          goto next;
1264
        case O (O_BNE, SB):
1265
          if ((Z == 0))
1266
            goto condtrue;
1267
          goto next;
1268
 
1269
        case O (O_BPL, SB):
1270
          if (N == 0)
1271
            goto condtrue;
1272
          goto next;
1273
        case O (O_BVC, SB):
1274
          if ((V == 0))
1275
            goto condtrue;
1276
          goto next;
1277
        case O (O_BVS, SB):
1278
          if ((V == 1))
1279
            goto condtrue;
1280
          goto next;
1281
 
1282
        case O (O_SYSCALL, SB):
1283
          {
1284
            char c = cpu.regs[2];
1285
            sim_callback->write_stdout (sim_callback, &c, 1);
1286
          }
1287
          goto next;
1288
 
1289
          ONOT (O_NOT, rd = ~rd; v = 0;);
1290
          OSHIFTS (O_SHLL,
1291
                   c = rd & hm; v = 0; rd <<= 1,
1292
                   c = rd & (hm >> 1); v = 0; rd <<= 2);
1293
          OSHIFTS (O_SHLR,
1294
                   c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1295
                   c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1296
          OSHIFTS (O_SHAL,
1297
                   c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1298
                   c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1299
          OSHIFTS (O_SHAR,
1300
                   t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1301
                   t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1302
          OSHIFTS (O_ROTL,
1303
                   c = rd & hm; v = 0; rd <<= 1; rd |= C,
1304
                   c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1305
          OSHIFTS (O_ROTR,
1306
                   c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1307
                   c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1308
          OSHIFTS (O_ROTXL,
1309
                   t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1310
                   t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1311
          OSHIFTS (O_ROTXR,
1312
                   t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1313
                   t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1314
 
1315
        case O (O_JMP, SB):
1316
          {
1317
            pc = fetch (&code->src);
1318
            goto end;
1319
 
1320
          }
1321
 
1322
        case O (O_JSR, SB):
1323
          {
1324
            int tmp;
1325
            pc = fetch (&code->src);
1326
          call:
1327
            tmp = cpu.regs[7];
1328
 
1329
            if (h8300hmode)
1330
              {
1331
                tmp -= 4;
1332
                SET_MEMORY_L (tmp, code->next_pc);
1333
              }
1334
            else
1335
              {
1336
                tmp -= 2;
1337
                SET_MEMORY_W (tmp, code->next_pc);
1338
              }
1339
            cpu.regs[7] = tmp;
1340
 
1341
            goto end;
1342
          }
1343
        case O (O_BSR, SB):
1344
          pc = code->src.literal;
1345
          goto call;
1346
 
1347
        case O (O_RTS, SN):
1348
          {
1349
            int tmp;
1350
 
1351
            tmp = cpu.regs[7];
1352
 
1353
            if (h8300hmode)
1354
              {
1355
                pc = GET_MEMORY_L (tmp);
1356
                tmp += 4;
1357
              }
1358
            else
1359
              {
1360
                pc = GET_MEMORY_W (tmp);
1361
                tmp += 2;
1362
              }
1363
 
1364
            cpu.regs[7] = tmp;
1365
            goto end;
1366
          }
1367
 
1368
        case O (O_ILL, SB):
1369
          cpu.state = SIM_STATE_STOPPED;
1370
          cpu.exception = SIGILL;
1371
          goto end;
1372
        case O (O_SLEEP, SN):
1373
          /* The format of r0 is defined by devo/include/wait.h.  */
1374
#if 0 /* FIXME: Ugh.  A breakpoint is the sleep insn.  */
1375
          if (WIFEXITED (cpu.regs[0]))
1376
            {
1377
              cpu.state = SIM_STATE_EXITED;
1378
              cpu.exception = WEXITSTATUS (cpu.regs[0]);
1379
            }
1380
          else if (WIFSTOPPED (cpu.regs[0]))
1381
            {
1382
              cpu.state = SIM_STATE_STOPPED;
1383
              cpu.exception = WSTOPSIG (cpu.regs[0]);
1384
            }
1385
          else
1386
            {
1387
              cpu.state = SIM_STATE_SIGNALLED;
1388
              cpu.exception = WTERMSIG (cpu.regs[0]);
1389
            }
1390
#else
1391
          /* FIXME: Doesn't this break for breakpoints when r0
1392
             contains just the right (er, wrong) value?  */
1393
          cpu.state = SIM_STATE_STOPPED;
1394
          if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0]))
1395
            cpu.exception = SIGILL;
1396
          else
1397
            cpu.exception = SIGTRAP;
1398
#endif
1399
          goto end;
1400
        case O (O_BPT, SN):
1401
          cpu.state = SIM_STATE_STOPPED;
1402
          cpu.exception = SIGTRAP;
1403
          goto end;
1404
 
1405
          OBITOP (O_BNOT, 1, 1, ea ^= m);
1406
          OBITOP (O_BTST, 1, 0, nz = ea & m);
1407
          OBITOP (O_BCLR, 1, 1, ea &= ~m);
1408
          OBITOP (O_BSET, 1, 1, ea |= m);
1409
          OBITOP (O_BLD, 1, 0, c = ea & m);
1410
          OBITOP (O_BILD, 1, 0, c = !(ea & m));
1411
          OBITOP (O_BST, 1, 1, ea &= ~m;
1412
                  if (C) ea |= m);
1413
          OBITOP (O_BIST, 1, 1, ea &= ~m;
1414
                  if (!C) ea |= m);
1415
          OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1416
          OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1417
          OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1418
          OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1419
          OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1420
          OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1421
 
1422
 
1423
#define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1424
 
1425
        case O (O_MULS, SB):
1426
          MOP (1, 1);
1427
          break;
1428
        case O (O_MULS, SW):
1429
          MOP (0, 1);
1430
          break;
1431
        case O (O_MULU, SB):
1432
          MOP (1, 0);
1433
          break;
1434
        case O (O_MULU, SW):
1435
          MOP (0, 0);
1436
          break;
1437
 
1438
 
1439
        case O (O_DIVU, SB):
1440
          {
1441
            rd = GET_W_REG (code->dst.reg);
1442
            ea = GET_B_REG (code->src.reg);
1443
            if (ea)
1444
              {
1445
                tmp = (unsigned)rd % ea;
1446
                rd = (unsigned)rd / ea;
1447
              }
1448
            SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1449
            n = ea & 0x80;
1450
            nz = ea & 0xff;
1451
 
1452
            goto next;
1453
          }
1454
        case O (O_DIVU, SW):
1455
          {
1456
            rd = GET_L_REG (code->dst.reg);
1457
            ea = GET_W_REG (code->src.reg);
1458
            n = ea & 0x8000;
1459
            nz = ea & 0xffff;
1460
            if (ea)
1461
              {
1462
                tmp = (unsigned)rd % ea;
1463
                rd = (unsigned)rd / ea;
1464
              }
1465
            SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1466
            goto next;
1467
          }
1468
 
1469
        case O (O_DIVS, SB):
1470
          {
1471
 
1472
            rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1473
            ea = SEXTCHAR (GET_B_REG (code->src.reg));
1474
            if (ea)
1475
              {
1476
                tmp = (int) rd % (int) ea;
1477
                rd = (int) rd / (int) ea;
1478
                n = rd & 0x8000;
1479
                nz = 1;
1480
              }
1481
            else
1482
              nz = 0;
1483
            SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1484
            goto next;
1485
          }
1486
        case O (O_DIVS, SW):
1487
          {
1488
            rd = GET_L_REG (code->dst.reg);
1489
            ea = SEXTSHORT (GET_W_REG (code->src.reg));
1490
            if (ea)
1491
              {
1492
                tmp = (int) rd % (int) ea;
1493
                rd = (int) rd / (int) ea;
1494
                n = rd & 0x80000000;
1495
                nz = 1;
1496
              }
1497
            else
1498
              nz = 0;
1499
            SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1500
            goto next;
1501
          }
1502
        case O (O_EXTS, SW):
1503
          rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst.  */
1504
          ea = rd & 0x80 ? -256 : 0;
1505
          res = rd + ea;
1506
          goto log16;
1507
        case O (O_EXTS, SL):
1508
          rd = GET_W_REG (code->src.reg) & 0xffff;
1509
          ea = rd & 0x8000 ? -65536 : 0;
1510
          res = rd + ea;
1511
          goto log32;
1512
        case O (O_EXTU, SW):
1513
          rd = GET_B_REG (code->src.reg + 8) & 0xff;
1514
          ea = 0;
1515
          res = rd + ea;
1516
          goto log16;
1517
        case O (O_EXTU, SL):
1518
          rd = GET_W_REG (code->src.reg) & 0xffff;
1519
          ea = 0;
1520
          res = rd + ea;
1521
          goto log32;
1522
 
1523
        case O (O_NOP, SN):
1524
          goto next;
1525
 
1526
        case O (O_STM, SL):
1527
          {
1528
            int nregs, firstreg, i;
1529
 
1530
            nregs = GET_MEMORY_B (pc + 1);
1531
            nregs >>= 4;
1532
            nregs &= 0xf;
1533
            firstreg = GET_MEMORY_B (pc + 3);
1534
            firstreg &= 0xf;
1535
            for (i = firstreg; i <= firstreg + nregs; i++)
1536
              {
1537
                cpu.regs[7] -= 4;
1538
                SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1539
              }
1540
          }
1541
          goto next;
1542
 
1543
        case O (O_LDM, SL):
1544
          {
1545
            int nregs, firstreg, i;
1546
 
1547
            nregs = GET_MEMORY_B (pc + 1);
1548
            nregs >>= 4;
1549
            nregs &= 0xf;
1550
            firstreg = GET_MEMORY_B (pc + 3);
1551
            firstreg &= 0xf;
1552
            for (i = firstreg; i >= firstreg - nregs; i--)
1553
              {
1554
                cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1555
                cpu.regs[7] += 4;
1556
              }
1557
          }
1558
          goto next;
1559
 
1560
        default:
1561
          cpu.state = SIM_STATE_STOPPED;
1562
          cpu.exception = SIGILL;
1563
          goto end;
1564
 
1565
        }
1566
      abort ();
1567
 
1568
    setc:
1569
      cpu.ccr = res;
1570
      GETSR ();
1571
      goto next;
1572
 
1573
    condtrue:
1574
      /* When a branch works */
1575
      pc = code->src.literal;
1576
      goto end;
1577
 
1578
      /* Set the cond codes from res */
1579
    bitop:
1580
 
1581
      /* Set the flags after an 8 bit inc/dec operation */
1582
    just_flags_inc8:
1583
      n = res & 0x80;
1584
      nz = res & 0xff;
1585
      v = (rd & 0x7f) == 0x7f;
1586
      goto next;
1587
 
1588
 
1589
      /* Set the flags after an 16 bit inc/dec operation */
1590
    just_flags_inc16:
1591
      n = res & 0x8000;
1592
      nz = res & 0xffff;
1593
      v = (rd & 0x7fff) == 0x7fff;
1594
      goto next;
1595
 
1596
 
1597
      /* Set the flags after an 32 bit inc/dec operation */
1598
    just_flags_inc32:
1599
      n = res & 0x80000000;
1600
      nz = res & 0xffffffff;
1601
      v = (rd & 0x7fffffff) == 0x7fffffff;
1602
      goto next;
1603
 
1604
 
1605
    shift8:
1606
      /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1607
      n = (rd & 0x80);
1608
      nz = rd & 0xff;
1609
      SET_B_REG (code->src.reg, rd);
1610
      goto next;
1611
 
1612
    shift16:
1613
      /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1614
      n = (rd & 0x8000);
1615
      nz = rd & 0xffff;
1616
      SET_W_REG (code->src.reg, rd);
1617
      goto next;
1618
 
1619
    shift32:
1620
      /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1621
      n = (rd & 0x80000000);
1622
      nz = rd & 0xffffffff;
1623
      SET_L_REG (code->src.reg, rd);
1624
      goto next;
1625
 
1626
    log32:
1627
      store (&code->dst, res);
1628
    just_flags_log32:
1629
      /* flags after a 32bit logical operation */
1630
      n = res & 0x80000000;
1631
      nz = res & 0xffffffff;
1632
      v = 0;
1633
      goto next;
1634
 
1635
    log16:
1636
      store (&code->dst, res);
1637
    just_flags_log16:
1638
      /* flags after a 16bit logical operation */
1639
      n = res & 0x8000;
1640
      nz = res & 0xffff;
1641
      v = 0;
1642
      goto next;
1643
 
1644
 
1645
    log8:
1646
      store (&code->dst, res);
1647
    just_flags_log8:
1648
      n = res & 0x80;
1649
      nz = res & 0xff;
1650
      v = 0;
1651
      goto next;
1652
 
1653
    alu8:
1654
      SET_B_REG (code->dst.reg, res);
1655
    just_flags_alu8:
1656
      n = res & 0x80;
1657
      nz = res & 0xff;
1658
      c = (res & 0x100);
1659
      switch (code->opcode / 4)
1660
        {
1661
        case O_ADD:
1662
          v = ((rd & 0x80) == (ea & 0x80)
1663
               && (rd & 0x80) != (res & 0x80));
1664
          break;
1665
        case O_SUB:
1666
        case O_CMP:
1667
          v = ((rd & 0x80) != (-ea & 0x80)
1668
               && (rd & 0x80) != (res & 0x80));
1669
          break;
1670
        case O_NEG:
1671
          v = (rd == 0x80);
1672
          break;
1673
        }
1674
      goto next;
1675
 
1676
    alu16:
1677
      SET_W_REG (code->dst.reg, res);
1678
    just_flags_alu16:
1679
      n = res & 0x8000;
1680
      nz = res & 0xffff;
1681
      c = (res & 0x10000);
1682
      switch (code->opcode / 4)
1683
        {
1684
        case O_ADD:
1685
          v = ((rd & 0x8000) == (ea & 0x8000)
1686
               && (rd & 0x8000) != (res & 0x8000));
1687
          break;
1688
        case O_SUB:
1689
        case O_CMP:
1690
          v = ((rd & 0x8000) != (-ea & 0x8000)
1691
               && (rd & 0x8000) != (res & 0x8000));
1692
          break;
1693
        case O_NEG:
1694
          v = (rd == 0x8000);
1695
          break;
1696
        }
1697
      goto next;
1698
 
1699
    alu32:
1700
      SET_L_REG (code->dst.reg, res);
1701
    just_flags_alu32:
1702
      n = res & 0x80000000;
1703
      nz = res & 0xffffffff;
1704
      switch (code->opcode / 4)
1705
        {
1706
        case O_ADD:
1707
          v = ((rd & 0x80000000) == (ea & 0x80000000)
1708
               && (rd & 0x80000000) != (res & 0x80000000));
1709
          c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1710
          break;
1711
        case O_SUB:
1712
        case O_CMP:
1713
          v = ((rd & 0x80000000) != (-ea & 0x80000000)
1714
               && (rd & 0x80000000) != (res & 0x80000000));
1715
          c = (unsigned) rd < (unsigned) -ea;
1716
          break;
1717
        case O_NEG:
1718
          v = (rd == 0x80000000);
1719
          c = res != 0;
1720
          break;
1721
        }
1722
      goto next;
1723
 
1724
    next:;
1725
      pc = code->next_pc;
1726
 
1727
    end:
1728
      ;
1729
      /*      if (cpu.regs[8] ) abort(); */
1730
 
1731
      if (--poll_count < 0)
1732
        {
1733
          poll_count = POLL_QUIT_INTERVAL;
1734
          if ((*sim_callback->poll_quit) != NULL
1735
              && (*sim_callback->poll_quit) (sim_callback))
1736
            sim_stop (sd);
1737
        }
1738
 
1739
    }
1740
  while (cpu.state == SIM_STATE_RUNNING);
1741
  cpu.ticks += get_now () - tick_start;
1742
  cpu.cycles += cycles;
1743
  cpu.insts += insts;
1744
 
1745
  cpu.pc = pc;
1746
  BUILDSR ();
1747
  cpu.mask = oldmask;
1748
  signal (SIGINT, prev);
1749
}
1750
 
1751
int
1752
sim_trace (sd)
1753
     SIM_DESC sd;
1754
{
1755
  /* FIXME: unfinished */
1756
  abort ();
1757
}
1758
 
1759
int
1760
sim_write (sd, addr, buffer, size)
1761
     SIM_DESC sd;
1762
     SIM_ADDR addr;
1763
     unsigned char *buffer;
1764
     int size;
1765
{
1766
  int i;
1767
 
1768
  init_pointers ();
1769
  if (addr < 0)
1770
    return 0;
1771
  for (i = 0; i < size; i++)
1772
    {
1773
      if (addr < memory_size)
1774
        {
1775
          cpu.memory[addr + i] = buffer[i];
1776
          cpu.cache_idx[addr + i] = 0;
1777
        }
1778
      else
1779
        cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1780
    }
1781
  return size;
1782
}
1783
 
1784
int
1785
sim_read (sd, addr, buffer, size)
1786
     SIM_DESC sd;
1787
     SIM_ADDR addr;
1788
     unsigned char *buffer;
1789
     int size;
1790
{
1791
  init_pointers ();
1792
  if (addr < 0)
1793
    return 0;
1794
  if (addr < memory_size)
1795
    memcpy (buffer, cpu.memory + addr, size);
1796
  else
1797
    memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1798
  return size;
1799
}
1800
 
1801
 
1802
#define R0_REGNUM       0
1803
#define R1_REGNUM       1
1804
#define R2_REGNUM       2
1805
#define R3_REGNUM       3
1806
#define R4_REGNUM       4
1807
#define R5_REGNUM       5
1808
#define R6_REGNUM       6
1809
#define R7_REGNUM       7
1810
 
1811
#define SP_REGNUM       R7_REGNUM       /* Contains address of top of stack */
1812
#define FP_REGNUM       R6_REGNUM       /* Contains address of executing
1813
                                           * stack frame */
1814
 
1815
#define CCR_REGNUM      8       /* Contains processor status */
1816
#define PC_REGNUM       9       /* Contains program counter */
1817
 
1818
#define CYCLE_REGNUM    10
1819
#define INST_REGNUM     11
1820
#define TICK_REGNUM     12
1821
 
1822
 
1823
int
1824
sim_store_register (sd, rn, value, length)
1825
     SIM_DESC sd;
1826
     int rn;
1827
     unsigned char *value;
1828
     int length;
1829
{
1830
  int longval;
1831
  int shortval;
1832
  int intval;
1833
  longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1834
  shortval = (value[0] << 8) | (value[1]);
1835
  intval = h8300hmode ? longval : shortval;
1836
 
1837
  init_pointers ();
1838
  switch (rn)
1839
    {
1840
    case PC_REGNUM:
1841
      cpu.pc = intval;
1842
      break;
1843
    default:
1844
      abort ();
1845
    case R0_REGNUM:
1846
    case R1_REGNUM:
1847
    case R2_REGNUM:
1848
    case R3_REGNUM:
1849
    case R4_REGNUM:
1850
    case R5_REGNUM:
1851
    case R6_REGNUM:
1852
    case R7_REGNUM:
1853
      cpu.regs[rn] = intval;
1854
      break;
1855
    case CCR_REGNUM:
1856
      cpu.ccr = intval;
1857
      break;
1858
    case CYCLE_REGNUM:
1859
      cpu.cycles = longval;
1860
      break;
1861
 
1862
    case INST_REGNUM:
1863
      cpu.insts = longval;
1864
      break;
1865
 
1866
    case TICK_REGNUM:
1867
      cpu.ticks = longval;
1868
      break;
1869
    }
1870
  return -1;
1871
}
1872
 
1873
int
1874
sim_fetch_register (sd, rn, buf, length)
1875
     SIM_DESC sd;
1876
     int rn;
1877
     unsigned char *buf;
1878
     int length;
1879
{
1880
  int v;
1881
  int longreg = 0;
1882
 
1883
  init_pointers ();
1884
 
1885
  switch (rn)
1886
    {
1887
    default:
1888
      abort ();
1889
    case 8:
1890
      v = cpu.ccr;
1891
      break;
1892
    case 9:
1893
      v = cpu.pc;
1894
      break;
1895
    case R0_REGNUM:
1896
    case R1_REGNUM:
1897
    case R2_REGNUM:
1898
    case R3_REGNUM:
1899
    case R4_REGNUM:
1900
    case R5_REGNUM:
1901
    case R6_REGNUM:
1902
    case R7_REGNUM:
1903
      v = cpu.regs[rn];
1904
      break;
1905
    case 10:
1906
      v = cpu.cycles;
1907
      longreg = 1;
1908
      break;
1909
    case 11:
1910
      v = cpu.ticks;
1911
      longreg = 1;
1912
      break;
1913
    case 12:
1914
      v = cpu.insts;
1915
      longreg = 1;
1916
      break;
1917
    }
1918
  if (h8300hmode || longreg)
1919
    {
1920
      buf[0] = v >> 24;
1921
      buf[1] = v >> 16;
1922
      buf[2] = v >> 8;
1923
      buf[3] = v >> 0;
1924
    }
1925
  else
1926
    {
1927
      buf[0] = v >> 8;
1928
      buf[1] = v;
1929
    }
1930
  return -1;
1931
}
1932
 
1933
void
1934
sim_stop_reason (sd, reason, sigrc)
1935
     SIM_DESC sd;
1936
     enum sim_stop *reason;
1937
     int *sigrc;
1938
{
1939
#if 0 /* FIXME: This should work but we can't use it.
1940
         grep for SLEEP above.  */
1941
  switch (cpu.state)
1942
    {
1943
    case SIM_STATE_EXITED : *reason = sim_exited; break;
1944
    case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1945
    case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1946
    default : abort ();
1947
    }
1948
#else
1949
  *reason = sim_stopped;
1950
#endif
1951
  *sigrc = cpu.exception;
1952
}
1953
 
1954
/* FIXME: Rename to sim_set_mem_size.  */
1955
 
1956
void
1957
sim_size (n)
1958
     int n;
1959
{
1960
  /* Memory size is fixed.  */
1961
}
1962
 
1963
void
1964
sim_set_simcache_size (n)
1965
{
1966
  if (cpu.cache)
1967
    free (cpu.cache);
1968
  if (n < 2)
1969
    n = 2;
1970
  cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1971
  memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1972
  cpu.csize = n;
1973
}
1974
 
1975
 
1976
void
1977
sim_info (sd, verbose)
1978
     SIM_DESC sd;
1979
     int verbose;
1980
{
1981
  double timetaken = (double) cpu.ticks / (double) now_persec ();
1982
  double virttime = cpu.cycles / 10.0e6;
1983
 
1984
  (*sim_callback->printf_filtered) (sim_callback,
1985
                                    "\n\n#instructions executed  %10d\n",
1986
                                    cpu.insts);
1987
  (*sim_callback->printf_filtered) (sim_callback,
1988
                                    "#cycles (v approximate) %10d\n",
1989
                                    cpu.cycles);
1990
  (*sim_callback->printf_filtered) (sim_callback,
1991
                                    "#real time taken        %10.4f\n",
1992
                                    timetaken);
1993
  (*sim_callback->printf_filtered) (sim_callback,
1994
                                    "#virtual time taked     %10.4f\n",
1995
                                    virttime);
1996
  if (timetaken != 0.0)
1997
    (*sim_callback->printf_filtered) (sim_callback,
1998
                                      "#simulation ratio       %10.4f\n",
1999
                                      virttime / timetaken);
2000
  (*sim_callback->printf_filtered) (sim_callback,
2001
                                    "#compiles               %10d\n",
2002
                                    cpu.compiles);
2003
  (*sim_callback->printf_filtered) (sim_callback,
2004
                                    "#cache size             %10d\n",
2005
                                    cpu.csize);
2006
 
2007
#ifdef ADEBUG
2008
  /* This to be conditional on `what' (aka `verbose'),
2009
     however it was never passed as non-zero.  */
2010
  if (1)
2011
    {
2012
      int i;
2013
      for (i = 0; i < O_LAST; i++)
2014
        {
2015
          if (cpu.stats[i])
2016
            (*sim_callback->printf_filtered) (sim_callback,
2017
                                              "%d: %d\n", i, cpu.stats[i]);
2018
        }
2019
    }
2020
#endif
2021
}
2022
 
2023
/* Indicate whether the cpu is an h8/300 or h8/300h.
2024
   FLAG is non-zero for the h8/300h.  */
2025
 
2026
void
2027
set_h8300h (flag)
2028
     int flag;
2029
{
2030
  /* FIXME: Much of the code in sim_load can be moved to sim_open.
2031
     This function being replaced by a sim_open:ARGV configuration
2032
     option */
2033
  h8300hmode = flag;
2034
}
2035
 
2036
SIM_DESC
2037
sim_open (kind, ptr, abfd, argv)
2038
     SIM_OPEN_KIND kind;
2039
     struct host_callback_struct *ptr;
2040
     struct _bfd *abfd;
2041
     char **argv;
2042
{
2043
  /* FIXME: Much of the code in sim_load can be moved here */
2044
 
2045
  sim_kind = kind;
2046
  myname = argv[0];
2047
  sim_callback = ptr;
2048
  /* fudge our descriptor */
2049
  return (SIM_DESC) 1;
2050
}
2051
 
2052
void
2053
sim_close (sd, quitting)
2054
     SIM_DESC sd;
2055
     int quitting;
2056
{
2057
  /* nothing to do */
2058
}
2059
 
2060
/* Called by gdb to load a program into memory.  */
2061
 
2062
SIM_RC
2063
sim_load (sd, prog, abfd, from_tty)
2064
     SIM_DESC sd;
2065
     char *prog;
2066
     bfd *abfd;
2067
     int from_tty;
2068
{
2069
  bfd *prog_bfd;
2070
 
2071
  /* FIXME: The code below that sets a specific variant of the h8/300
2072
     being simulated should be moved to sim_open(). */
2073
 
2074
  /* See if the file is for the h8/300 or h8/300h.  */
2075
  /* ??? This may not be the most efficient way.  The z8k simulator
2076
     does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO).  */
2077
  if (abfd != NULL)
2078
    prog_bfd = abfd;
2079
  else
2080
    prog_bfd = bfd_openr (prog, "coff-h8300");
2081
  if (prog_bfd != NULL)
2082
    {
2083
      /* Set the cpu type.  We ignore failure from bfd_check_format
2084
         and bfd_openr as sim_load_file checks too.  */
2085
      if (bfd_check_format (prog_bfd, bfd_object))
2086
        {
2087
          unsigned long mach = bfd_get_mach (prog_bfd);
2088
          set_h8300h (mach == bfd_mach_h8300h
2089
                      || mach == bfd_mach_h8300s);
2090
        }
2091
    }
2092
 
2093
  /* If we're using gdb attached to the simulator, then we have to
2094
     reallocate memory for the simulator.
2095
 
2096
     When gdb first starts, it calls fetch_registers (among other
2097
     functions), which in turn calls init_pointers, which allocates
2098
     simulator memory.
2099
 
2100
     The problem is when we do that, we don't know whether we're
2101
     debugging an h8/300 or h8/300h program.
2102
 
2103
     This is the first point at which we can make that determination,
2104
     so we just reallocate memory now; this will also allow us to handle
2105
     switching between h8/300 and h8/300h programs without exiting
2106
     gdb.  */
2107
  if (h8300hmode)
2108
    memory_size = H8300H_MSIZE;
2109
  else
2110
    memory_size = H8300_MSIZE;
2111
 
2112
  if (cpu.memory)
2113
    free (cpu.memory);
2114
  if (cpu.cache_idx)
2115
    free (cpu.cache_idx);
2116
  if (cpu.eightbit)
2117
    free (cpu.eightbit);
2118
 
2119
  cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2120
  cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2121
  cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2122
 
2123
  /* `msize' must be a power of two */
2124
  if ((memory_size & (memory_size - 1)) != 0)
2125
    abort ();
2126
  cpu.mask = memory_size - 1;
2127
 
2128
  if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2129
                     sim_kind == SIM_OPEN_DEBUG,
2130
                     0, sim_write)
2131
      == NULL)
2132
    {
2133
      /* Close the bfd if we opened it.  */
2134
      if (abfd == NULL && prog_bfd != NULL)
2135
        bfd_close (prog_bfd);
2136
      return SIM_RC_FAIL;
2137
    }
2138
 
2139
  /* Close the bfd if we opened it.  */
2140
  if (abfd == NULL && prog_bfd != NULL)
2141
    bfd_close (prog_bfd);
2142
  return SIM_RC_OK;
2143
}
2144
 
2145
SIM_RC
2146
sim_create_inferior (sd, abfd, argv, env)
2147
     SIM_DESC sd;
2148
     struct _bfd *abfd;
2149
     char **argv;
2150
     char **env;
2151
{
2152
  if (abfd != NULL)
2153
    cpu.pc = bfd_get_start_address (abfd);
2154
  else
2155
    cpu.pc = 0;
2156
  return SIM_RC_OK;
2157
}
2158
 
2159
void
2160
sim_do_command (sd, cmd)
2161
     SIM_DESC sd;
2162
     char *cmd;
2163
{
2164
  (*sim_callback->printf_filtered) (sim_callback,
2165
                                    "This simulator does not accept any commands.\n");
2166
}
2167
 
2168
void
2169
sim_set_callbacks (ptr)
2170
     struct host_callback_struct *ptr;
2171
{
2172
  sim_callback = ptr;
2173
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.