OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [oc/] [gdb-5.0/] [sim/] [i960/] [decode.h] - Blame information for rev 1771

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 106 markom 
/* Decode header for i960base.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Simulators.
8 
 
9 
This program is free software; you can redistribute it and/or modify
10 
it under the terms of the GNU General Public License as published by
11 
the Free Software Foundation; either version 2, or (at your option)
12 
any later version.
13 
 
14 
This program is distributed in the hope that it will be useful,
15 
but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
GNU General Public License for more details.
18 
 
19 
You should have received a copy of the GNU General Public License along
20 
with this program; if not, write to the Free Software Foundation, Inc.,
21 
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 
 
23 
*/
24 
 
25 
#ifndef I960BASE_DECODE_H
26 
#define I960BASE_DECODE_H
27 
 
28 
extern const IDESC *i960base_decode (SIM_CPU *, IADDR,
29 
                                  CGEN_INSN_INT,
30 
                                  ARGBUF *);
31 
extern void i960base_init_idesc_table (SIM_CPU *);
32 
extern void i960base_sem_init_idesc_table (SIM_CPU *);
33 
extern void i960base_semf_init_idesc_table (SIM_CPU *);
34 
 
35 
/* Enum declaration for instructions in cpu family i960base.  */
36 
typedef enum i960base_insn_type {
37 
  I960BASE_INSN_X_INVALID, I960BASE_INSN_X_AFTER, I960BASE_INSN_X_BEFORE, I960BASE_INSN_X_CTI_CHAIN
38 
 , I960BASE_INSN_X_CHAIN, I960BASE_INSN_X_BEGIN, I960BASE_INSN_MULO, I960BASE_INSN_MULO1
39 
 , I960BASE_INSN_MULO2, I960BASE_INSN_MULO3, I960BASE_INSN_REMO, I960BASE_INSN_REMO1
40 
 , I960BASE_INSN_REMO2, I960BASE_INSN_REMO3, I960BASE_INSN_DIVO, I960BASE_INSN_DIVO1
41 
 , I960BASE_INSN_DIVO2, I960BASE_INSN_DIVO3, I960BASE_INSN_REMI, I960BASE_INSN_REMI1
42 
 , I960BASE_INSN_REMI2, I960BASE_INSN_REMI3, I960BASE_INSN_DIVI, I960BASE_INSN_DIVI1
43 
 , I960BASE_INSN_DIVI2, I960BASE_INSN_DIVI3, I960BASE_INSN_ADDO, I960BASE_INSN_ADDO1
44 
 , I960BASE_INSN_ADDO2, I960BASE_INSN_ADDO3, I960BASE_INSN_SUBO, I960BASE_INSN_SUBO1
45 
 , I960BASE_INSN_SUBO2, I960BASE_INSN_SUBO3, I960BASE_INSN_NOTBIT, I960BASE_INSN_NOTBIT1
46 
 , I960BASE_INSN_NOTBIT2, I960BASE_INSN_NOTBIT3, I960BASE_INSN_AND, I960BASE_INSN_AND1
47 
 , I960BASE_INSN_AND2, I960BASE_INSN_AND3, I960BASE_INSN_ANDNOT, I960BASE_INSN_ANDNOT1
48 
 , I960BASE_INSN_ANDNOT2, I960BASE_INSN_ANDNOT3, I960BASE_INSN_SETBIT, I960BASE_INSN_SETBIT1
49 
 , I960BASE_INSN_SETBIT2, I960BASE_INSN_SETBIT3, I960BASE_INSN_NOTAND, I960BASE_INSN_NOTAND1
50 
 , I960BASE_INSN_NOTAND2, I960BASE_INSN_NOTAND3, I960BASE_INSN_XOR, I960BASE_INSN_XOR1
51 
 , I960BASE_INSN_XOR2, I960BASE_INSN_XOR3, I960BASE_INSN_OR, I960BASE_INSN_OR1
52 
 , I960BASE_INSN_OR2, I960BASE_INSN_OR3, I960BASE_INSN_NOR, I960BASE_INSN_NOR1
53 
 , I960BASE_INSN_NOR2, I960BASE_INSN_NOR3, I960BASE_INSN_XNOR, I960BASE_INSN_XNOR1
54 
 , I960BASE_INSN_XNOR2, I960BASE_INSN_XNOR3, I960BASE_INSN_NOT, I960BASE_INSN_NOT1
55 
 , I960BASE_INSN_NOT2, I960BASE_INSN_NOT3, I960BASE_INSN_ORNOT, I960BASE_INSN_ORNOT1
56 
 , I960BASE_INSN_ORNOT2, I960BASE_INSN_ORNOT3, I960BASE_INSN_CLRBIT, I960BASE_INSN_CLRBIT1
57 
 , I960BASE_INSN_CLRBIT2, I960BASE_INSN_CLRBIT3, I960BASE_INSN_SHLO, I960BASE_INSN_SHLO1
58 
 , I960BASE_INSN_SHLO2, I960BASE_INSN_SHLO3, I960BASE_INSN_SHRO, I960BASE_INSN_SHRO1
59 
 , I960BASE_INSN_SHRO2, I960BASE_INSN_SHRO3, I960BASE_INSN_SHLI, I960BASE_INSN_SHLI1
60 
 , I960BASE_INSN_SHLI2, I960BASE_INSN_SHLI3, I960BASE_INSN_SHRI, I960BASE_INSN_SHRI1
61 
 , I960BASE_INSN_SHRI2, I960BASE_INSN_SHRI3, I960BASE_INSN_EMUL, I960BASE_INSN_EMUL1
62 
 , I960BASE_INSN_EMUL2, I960BASE_INSN_EMUL3, I960BASE_INSN_MOV, I960BASE_INSN_MOV1
63 
 , I960BASE_INSN_MOVL, I960BASE_INSN_MOVL1, I960BASE_INSN_MOVT, I960BASE_INSN_MOVT1
64 
 , I960BASE_INSN_MOVQ, I960BASE_INSN_MOVQ1, I960BASE_INSN_MODPC, I960BASE_INSN_MODAC
65 
 , I960BASE_INSN_LDA_OFFSET, I960BASE_INSN_LDA_INDIRECT_OFFSET, I960BASE_INSN_LDA_INDIRECT, I960BASE_INSN_LDA_INDIRECT_INDEX
66 
 , I960BASE_INSN_LDA_DISP, I960BASE_INSN_LDA_INDIRECT_DISP, I960BASE_INSN_LDA_INDEX_DISP, I960BASE_INSN_LDA_INDIRECT_INDEX_DISP
67 
 , I960BASE_INSN_LD_OFFSET, I960BASE_INSN_LD_INDIRECT_OFFSET, I960BASE_INSN_LD_INDIRECT, I960BASE_INSN_LD_INDIRECT_INDEX
68 
 , I960BASE_INSN_LD_DISP, I960BASE_INSN_LD_INDIRECT_DISP, I960BASE_INSN_LD_INDEX_DISP, I960BASE_INSN_LD_INDIRECT_INDEX_DISP
69 
 , I960BASE_INSN_LDOB_OFFSET, I960BASE_INSN_LDOB_INDIRECT_OFFSET, I960BASE_INSN_LDOB_INDIRECT, I960BASE_INSN_LDOB_INDIRECT_INDEX
70 
 , I960BASE_INSN_LDOB_DISP, I960BASE_INSN_LDOB_INDIRECT_DISP, I960BASE_INSN_LDOB_INDEX_DISP, I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP
71 
 , I960BASE_INSN_LDOS_OFFSET, I960BASE_INSN_LDOS_INDIRECT_OFFSET, I960BASE_INSN_LDOS_INDIRECT, I960BASE_INSN_LDOS_INDIRECT_INDEX
72 
 , I960BASE_INSN_LDOS_DISP, I960BASE_INSN_LDOS_INDIRECT_DISP, I960BASE_INSN_LDOS_INDEX_DISP, I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP
73 
 , I960BASE_INSN_LDIB_OFFSET, I960BASE_INSN_LDIB_INDIRECT_OFFSET, I960BASE_INSN_LDIB_INDIRECT, I960BASE_INSN_LDIB_INDIRECT_INDEX
74 
 , I960BASE_INSN_LDIB_DISP, I960BASE_INSN_LDIB_INDIRECT_DISP, I960BASE_INSN_LDIB_INDEX_DISP, I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP
75 
 , I960BASE_INSN_LDIS_OFFSET, I960BASE_INSN_LDIS_INDIRECT_OFFSET, I960BASE_INSN_LDIS_INDIRECT, I960BASE_INSN_LDIS_INDIRECT_INDEX
76 
 , I960BASE_INSN_LDIS_DISP, I960BASE_INSN_LDIS_INDIRECT_DISP, I960BASE_INSN_LDIS_INDEX_DISP, I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP
77 
 , I960BASE_INSN_LDL_OFFSET, I960BASE_INSN_LDL_INDIRECT_OFFSET, I960BASE_INSN_LDL_INDIRECT, I960BASE_INSN_LDL_INDIRECT_INDEX
78 
 , I960BASE_INSN_LDL_DISP, I960BASE_INSN_LDL_INDIRECT_DISP, I960BASE_INSN_LDL_INDEX_DISP, I960BASE_INSN_LDL_INDIRECT_INDEX_DISP
79 
 , I960BASE_INSN_LDT_OFFSET, I960BASE_INSN_LDT_INDIRECT_OFFSET, I960BASE_INSN_LDT_INDIRECT, I960BASE_INSN_LDT_INDIRECT_INDEX
80 
 , I960BASE_INSN_LDT_DISP, I960BASE_INSN_LDT_INDIRECT_DISP, I960BASE_INSN_LDT_INDEX_DISP, I960BASE_INSN_LDT_INDIRECT_INDEX_DISP
81 
 , I960BASE_INSN_LDQ_OFFSET, I960BASE_INSN_LDQ_INDIRECT_OFFSET, I960BASE_INSN_LDQ_INDIRECT, I960BASE_INSN_LDQ_INDIRECT_INDEX
82 
 , I960BASE_INSN_LDQ_DISP, I960BASE_INSN_LDQ_INDIRECT_DISP, I960BASE_INSN_LDQ_INDEX_DISP, I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP
83 
 , I960BASE_INSN_ST_OFFSET, I960BASE_INSN_ST_INDIRECT_OFFSET, I960BASE_INSN_ST_INDIRECT, I960BASE_INSN_ST_INDIRECT_INDEX
84 
 , I960BASE_INSN_ST_DISP, I960BASE_INSN_ST_INDIRECT_DISP, I960BASE_INSN_ST_INDEX_DISP, I960BASE_INSN_ST_INDIRECT_INDEX_DISP
85 
 , I960BASE_INSN_STOB_OFFSET, I960BASE_INSN_STOB_INDIRECT_OFFSET, I960BASE_INSN_STOB_INDIRECT, I960BASE_INSN_STOB_INDIRECT_INDEX
86 
 , I960BASE_INSN_STOB_DISP, I960BASE_INSN_STOB_INDIRECT_DISP, I960BASE_INSN_STOB_INDEX_DISP, I960BASE_INSN_STOB_INDIRECT_INDEX_DISP
87 
 , I960BASE_INSN_STOS_OFFSET, I960BASE_INSN_STOS_INDIRECT_OFFSET, I960BASE_INSN_STOS_INDIRECT, I960BASE_INSN_STOS_INDIRECT_INDEX
88 
 , I960BASE_INSN_STOS_DISP, I960BASE_INSN_STOS_INDIRECT_DISP, I960BASE_INSN_STOS_INDEX_DISP, I960BASE_INSN_STOS_INDIRECT_INDEX_DISP
89 
 , I960BASE_INSN_STL_OFFSET, I960BASE_INSN_STL_INDIRECT_OFFSET, I960BASE_INSN_STL_INDIRECT, I960BASE_INSN_STL_INDIRECT_INDEX
90 
 , I960BASE_INSN_STL_DISP, I960BASE_INSN_STL_INDIRECT_DISP, I960BASE_INSN_STL_INDEX_DISP, I960BASE_INSN_STL_INDIRECT_INDEX_DISP
91 
 , I960BASE_INSN_STT_OFFSET, I960BASE_INSN_STT_INDIRECT_OFFSET, I960BASE_INSN_STT_INDIRECT, I960BASE_INSN_STT_INDIRECT_INDEX
92 
 , I960BASE_INSN_STT_DISP, I960BASE_INSN_STT_INDIRECT_DISP, I960BASE_INSN_STT_INDEX_DISP, I960BASE_INSN_STT_INDIRECT_INDEX_DISP
93 
 , I960BASE_INSN_STQ_OFFSET, I960BASE_INSN_STQ_INDIRECT_OFFSET, I960BASE_INSN_STQ_INDIRECT, I960BASE_INSN_STQ_INDIRECT_INDEX
94 
 , I960BASE_INSN_STQ_DISP, I960BASE_INSN_STQ_INDIRECT_DISP, I960BASE_INSN_STQ_INDEX_DISP, I960BASE_INSN_STQ_INDIRECT_INDEX_DISP
95 
 , I960BASE_INSN_CMPOBE_REG, I960BASE_INSN_CMPOBE_LIT, I960BASE_INSN_CMPOBNE_REG, I960BASE_INSN_CMPOBNE_LIT
96 
 , I960BASE_INSN_CMPOBL_REG, I960BASE_INSN_CMPOBL_LIT, I960BASE_INSN_CMPOBLE_REG, I960BASE_INSN_CMPOBLE_LIT
97 
 , I960BASE_INSN_CMPOBG_REG, I960BASE_INSN_CMPOBG_LIT, I960BASE_INSN_CMPOBGE_REG, I960BASE_INSN_CMPOBGE_LIT
98 
 , I960BASE_INSN_CMPIBE_REG, I960BASE_INSN_CMPIBE_LIT, I960BASE_INSN_CMPIBNE_REG, I960BASE_INSN_CMPIBNE_LIT
99 
 , I960BASE_INSN_CMPIBL_REG, I960BASE_INSN_CMPIBL_LIT, I960BASE_INSN_CMPIBLE_REG, I960BASE_INSN_CMPIBLE_LIT
100 
 , I960BASE_INSN_CMPIBG_REG, I960BASE_INSN_CMPIBG_LIT, I960BASE_INSN_CMPIBGE_REG, I960BASE_INSN_CMPIBGE_LIT
101 
 , I960BASE_INSN_BBC_REG, I960BASE_INSN_BBC_LIT, I960BASE_INSN_BBS_REG, I960BASE_INSN_BBS_LIT
102 
 , I960BASE_INSN_CMPI, I960BASE_INSN_CMPI1, I960BASE_INSN_CMPI2, I960BASE_INSN_CMPI3
103 
 , I960BASE_INSN_CMPO, I960BASE_INSN_CMPO1, I960BASE_INSN_CMPO2, I960BASE_INSN_CMPO3
104 
 , I960BASE_INSN_TESTNO_REG, I960BASE_INSN_TESTG_REG, I960BASE_INSN_TESTE_REG, I960BASE_INSN_TESTGE_REG
105 
 , I960BASE_INSN_TESTL_REG, I960BASE_INSN_TESTNE_REG, I960BASE_INSN_TESTLE_REG, I960BASE_INSN_TESTO_REG
106 
 , I960BASE_INSN_BNO, I960BASE_INSN_BG, I960BASE_INSN_BE, I960BASE_INSN_BGE
107 
 , I960BASE_INSN_BL, I960BASE_INSN_BNE, I960BASE_INSN_BLE, I960BASE_INSN_BO
108 
 , I960BASE_INSN_B, I960BASE_INSN_BX_INDIRECT_OFFSET, I960BASE_INSN_BX_INDIRECT, I960BASE_INSN_BX_INDIRECT_INDEX
109 
 , I960BASE_INSN_BX_DISP, I960BASE_INSN_BX_INDIRECT_DISP, I960BASE_INSN_CALLX_DISP, I960BASE_INSN_CALLX_INDIRECT
110 
 , I960BASE_INSN_CALLX_INDIRECT_OFFSET, I960BASE_INSN_RET, I960BASE_INSN_CALLS, I960BASE_INSN_FMARK
111 
 , I960BASE_INSN_FLUSHREG, I960BASE_INSN_MAX
112 
} I960BASE_INSN_TYPE;
113 
 
114 
/* Enum declaration for semantic formats in cpu family i960base.  */
115 
typedef enum i960base_sfmt_type {
116 
  I960BASE_SFMT_EMPTY, I960BASE_SFMT_MULO, I960BASE_SFMT_MULO1, I960BASE_SFMT_MULO2
117 
 , I960BASE_SFMT_MULO3, I960BASE_SFMT_NOTBIT, I960BASE_SFMT_NOTBIT1, I960BASE_SFMT_NOTBIT2
118 
 , I960BASE_SFMT_NOTBIT3, I960BASE_SFMT_NOT, I960BASE_SFMT_NOT1, I960BASE_SFMT_SHLO
119 
 , I960BASE_SFMT_SHLO1, I960BASE_SFMT_SHLO2, I960BASE_SFMT_SHLO3, I960BASE_SFMT_EMUL
120 
 , I960BASE_SFMT_EMUL1, I960BASE_SFMT_EMUL2, I960BASE_SFMT_EMUL3, I960BASE_SFMT_MOVL
121 
 , I960BASE_SFMT_MOVL1, I960BASE_SFMT_MOVT, I960BASE_SFMT_MOVT1, I960BASE_SFMT_MOVQ
122 
 , I960BASE_SFMT_MOVQ1, I960BASE_SFMT_MODPC, I960BASE_SFMT_LDA_OFFSET, I960BASE_SFMT_LDA_INDIRECT_OFFSET
123 
 , I960BASE_SFMT_LDA_INDIRECT, I960BASE_SFMT_LDA_INDIRECT_INDEX, I960BASE_SFMT_LDA_DISP, I960BASE_SFMT_LDA_INDIRECT_DISP
124 
 , I960BASE_SFMT_LDA_INDEX_DISP, I960BASE_SFMT_LDA_INDIRECT_INDEX_DISP, I960BASE_SFMT_LD_OFFSET, I960BASE_SFMT_LD_INDIRECT_OFFSET
125 
 , I960BASE_SFMT_LD_INDIRECT, I960BASE_SFMT_LD_INDIRECT_INDEX, I960BASE_SFMT_LD_DISP, I960BASE_SFMT_LD_INDIRECT_DISP
126 
 , I960BASE_SFMT_LD_INDEX_DISP, I960BASE_SFMT_LD_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDL_OFFSET, I960BASE_SFMT_LDL_INDIRECT_OFFSET
127 
 , I960BASE_SFMT_LDL_INDIRECT, I960BASE_SFMT_LDL_INDIRECT_INDEX, I960BASE_SFMT_LDL_DISP, I960BASE_SFMT_LDL_INDIRECT_DISP
128 
 , I960BASE_SFMT_LDL_INDEX_DISP, I960BASE_SFMT_LDL_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDT_OFFSET, I960BASE_SFMT_LDT_INDIRECT_OFFSET
129 
 , I960BASE_SFMT_LDT_INDIRECT, I960BASE_SFMT_LDT_INDIRECT_INDEX, I960BASE_SFMT_LDT_DISP, I960BASE_SFMT_LDT_INDIRECT_DISP
130 
 , I960BASE_SFMT_LDT_INDEX_DISP, I960BASE_SFMT_LDT_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDQ_OFFSET, I960BASE_SFMT_LDQ_INDIRECT_OFFSET
131 
 , I960BASE_SFMT_LDQ_INDIRECT, I960BASE_SFMT_LDQ_INDIRECT_INDEX, I960BASE_SFMT_LDQ_DISP, I960BASE_SFMT_LDQ_INDIRECT_DISP
132 
 , I960BASE_SFMT_LDQ_INDEX_DISP, I960BASE_SFMT_LDQ_INDIRECT_INDEX_DISP, I960BASE_SFMT_ST_OFFSET, I960BASE_SFMT_ST_INDIRECT_OFFSET
133 
 , I960BASE_SFMT_ST_INDIRECT, I960BASE_SFMT_ST_INDIRECT_INDEX, I960BASE_SFMT_ST_DISP, I960BASE_SFMT_ST_INDIRECT_DISP
134 
 , I960BASE_SFMT_ST_INDEX_DISP, I960BASE_SFMT_ST_INDIRECT_INDEX_DISP, I960BASE_SFMT_STL_OFFSET, I960BASE_SFMT_STL_INDIRECT_OFFSET
135 
 , I960BASE_SFMT_STL_INDIRECT, I960BASE_SFMT_STL_INDIRECT_INDEX, I960BASE_SFMT_STL_DISP, I960BASE_SFMT_STL_INDIRECT_DISP
136 
 , I960BASE_SFMT_STL_INDEX_DISP, I960BASE_SFMT_STL_INDIRECT_INDEX_DISP, I960BASE_SFMT_STT_OFFSET, I960BASE_SFMT_STT_INDIRECT_OFFSET
137 
 , I960BASE_SFMT_STT_INDIRECT, I960BASE_SFMT_STT_INDIRECT_INDEX, I960BASE_SFMT_STT_DISP, I960BASE_SFMT_STT_INDIRECT_DISP
138 
 , I960BASE_SFMT_STT_INDEX_DISP, I960BASE_SFMT_STT_INDIRECT_INDEX_DISP, I960BASE_SFMT_STQ_OFFSET, I960BASE_SFMT_STQ_INDIRECT_OFFSET
139 
 , I960BASE_SFMT_STQ_INDIRECT, I960BASE_SFMT_STQ_INDIRECT_INDEX, I960BASE_SFMT_STQ_DISP, I960BASE_SFMT_STQ_INDIRECT_DISP
140 
 , I960BASE_SFMT_STQ_INDEX_DISP, I960BASE_SFMT_STQ_INDIRECT_INDEX_DISP, I960BASE_SFMT_CMPOBE_REG, I960BASE_SFMT_CMPOBE_LIT
141 
 , I960BASE_SFMT_CMPOBL_REG, I960BASE_SFMT_CMPOBL_LIT, I960BASE_SFMT_BBC_REG, I960BASE_SFMT_BBC_LIT
142 
 , I960BASE_SFMT_CMPI, I960BASE_SFMT_CMPI1, I960BASE_SFMT_CMPI2, I960BASE_SFMT_CMPI3
143 
 , I960BASE_SFMT_CMPO, I960BASE_SFMT_CMPO1, I960BASE_SFMT_CMPO2, I960BASE_SFMT_CMPO3
144 
 , I960BASE_SFMT_TESTNO_REG, I960BASE_SFMT_BNO, I960BASE_SFMT_B, I960BASE_SFMT_BX_INDIRECT_OFFSET
145 
 , I960BASE_SFMT_BX_INDIRECT, I960BASE_SFMT_BX_INDIRECT_INDEX, I960BASE_SFMT_BX_DISP, I960BASE_SFMT_BX_INDIRECT_DISP
146 
 , I960BASE_SFMT_CALLX_DISP, I960BASE_SFMT_CALLX_INDIRECT, I960BASE_SFMT_CALLX_INDIRECT_OFFSET, I960BASE_SFMT_RET
147 
 , I960BASE_SFMT_CALLS, I960BASE_SFMT_FMARK, I960BASE_SFMT_FLUSHREG
148 
} I960BASE_SFMT_TYPE;
149 
 
150 
/* Function unit handlers (user written).  */
151 
 
152 
extern int i960base_model_i960KA_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
153 
extern int i960base_model_i960CA_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
154 
 
155 
/* Profiling before/after handlers (user written) */
156 
 
157 
extern void i960base_model_insn_before (SIM_CPU *, int /*first_p*/);
158 
extern void i960base_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
159 
 
160 
#endif /* I960BASE_DECODE_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.