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[/] [or1k/] [branches/] [oc/] [gdb-5.0/] [sim/] [mn10300/] [am33.igen] - Blame information for rev 1765

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Line No. Rev Author Line
1 106 markom 
// Helper:
2 
//
3 
// Given an extended register number, translate it into an index into the
4 
// register array.  This is necessary as the upper 8 extended registers are
5 
// actually synonyms for the d0-d3/a0-a3 registers.
6 
//
7 
//
8 
 
9 
:function:::int:translate_rreg:int rreg
10 
{
11 
 
12 
  /* The higher register numbers actually correspond to the
13 
     basic machine's address and data registers.  */
14 
  if (rreg > 7 && rreg < 12)
15 
    return REG_A0 + rreg - 8;
16 
  else if (rreg > 11 && rreg < 16)
17 
    return REG_D0 + rreg - 12;
18 
  else
19 
    return REG_E0 + rreg;
20 
}
21 
 
22 
:function:::int:translate_xreg:int xreg
23 
{
24 
  switch (xreg)
25 
    {
26 
    case 0:
27 
      return REG_SP;
28 
    case 1:
29 
      return REG_MDRQ;
30 
    case 2:
31 
      return REG_MCRH;
32 
    case 3:
33 
      return REG_MCRL;
34 
    case 4:
35 
      return REG_MCVF;
36 
    default:
37 
      abort ();
38 
    }
39 
}
40 
 
41 
// 1111 0000 0010 00An; mov USP,An
42 
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
43 
"mov"
44 
*am33
45 
{
46 
  PC = cia;
47 
  State.regs[REG_A0 + AN0] = State.regs[REG_USP];
48 
}
49 
 
50 
 
51 
// 1111 0000 0010 01An; mov SSP,An
52 
8.0xf0+4.0x2,01,2.AN0:D0n:::mov
53 
"mov"
54 
*am33
55 
{
56 
  PC = cia;
57 
  State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
58 
}
59 
 
60 
 
61 
// 1111 0000 0010 10An; mov MSP,An
62 
8.0xf0+4.0x2,10,2.AN0:D0o:::mov
63 
"mov"
64 
*am33
65 
{
66 
  PC = cia;
67 
  State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
68 
}
69 
 
70 
 
71 
// 1111 0000 0010 11An; mov PC,An
72 
8.0xf0+4.0x2,11,2.AN0:D0p:::mov
73 
"mov"
74 
*am33
75 
{
76 
  PC = cia;
77 
  State.regs[REG_A0 + AN0] = PC;
78 
}
79 
 
80 
 
81 
// 1111 0000 0011 Am00; mov Am,USP
82 
8.0xf0+4.0x3,2.AM1,00:D0q:::mov
83 
"mov"
84 
*am33
85 
{
86 
  PC = cia;
87 
  State.regs[REG_USP] = State.regs[REG_A0 + AM1];
88 
}
89 
 
90 
// 1111 0000 0011 Am01; mov Am,SSP
91 
8.0xf0+4.0x3,2.AM1,01:D0r:::mov
92 
"mov"
93 
*am33
94 
{
95 
  PC = cia;
96 
  State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
97 
}
98 
 
99 
// 1111 0000 0011 Am10; mov Am,MSP
100 
8.0xf0+4.0x3,2.AM1,10:D0s:::mov
101 
"mov"
102 
*am33
103 
{
104 
  PC = cia;
105 
  State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
106 
}
107 
 
108 
 
109 
// 1111 0000 1110 imm4; syscall
110 
8.0xf0+4.0xe,IMM4:D0t:::syscall
111 
"syscall"
112 
*am33
113 
{
114 
  unsigned int sp, next_pc;
115 
 
116 
  PC = cia;
117 
  sp = State.regs[REG_SP];
118 
  next_pc = State.regs[REG_PC] + 2;
119 
  store_word (sp - 4, next_pc);
120 
  store_word (sp - 8, PSW);
121 
  State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
122 
  nia = PC;
123 
}
124 
 
125 
 
126 
// 1111 0010 1110 11Dn; mov EPSW,Dn
127 
8.0xf2+4.0xe,11,2.DN0:D0u:::mov
128 
"mov"
129 
*am33
130 
{
131 
  PC = cia;
132 
  State.regs[REG_D0 + DN0] = PSW;
133 
}
134 
 
135 
 
136 
// 1111 0010 1111 Dm01; mov Dm,EPSW
137 
8.0xf2+4.0xf,2.DM1,01:D0v:::mov
138 
"mov"
139 
*am33
140 
{
141 
  PC = cia;
142 
  PSW = State.regs[REG_D0 + DM1];
143 
}
144 
 
145 
// 1111 0101 00Am Rn; mov Am,Rn
146 
8.0xf5+00,2.AM1,4.RN0:D0w:::mov
147 
"mov"
148 
*am33
149 
{
150 
  int destreg = translate_rreg (SD_, RN0);
151 
 
152 
  PC = cia;
153 
  State.regs[destreg] = State.regs[REG_A0 + AM1];
154 
}
155 
 
156 
// 1111 0101 01Dm Rn; mov Dm,Rn
157 
8.0xf5+01,2.DM1,4.RN0:D0x:::mov
158 
"mov"
159 
*am33
160 
{
161 
  int destreg = translate_rreg (SD_, RN0);
162 
 
163 
  PC = cia;
164 
  State.regs[destreg] = State.regs[REG_D0 + DM1];
165 
}
166 
 
167 
// 1111 0101 10Rm An; mov Rm,An
168 
8.0xf5+10,4.RM1,2.AN0:D0y:::mov
169 
"mov"
170 
*am33
171 
{
172 
  int destreg = translate_rreg (SD_, RM1);
173 
 
174 
  PC = cia;
175 
  State.regs[REG_A0 + AN0] = State.regs[destreg];
176 
}
177 
 
178 
// 1111 0101 11Rm Dn; mov Rm,Dn
179 
8.0xf5+11,4.RM1,2.DN0:D0z:::mov
180 
"mov"
181 
*am33
182 
{
183 
  int destreg = translate_rreg (SD_, RM1);
184 
 
185 
  PC = cia;
186 
  State.regs[REG_D0 + DN0] = State.regs[destreg];
187 
}
188 
 
189 
 
190 
// 1111 1000 1100 1110 regs....; movm (USP),regs
191 
8.0xf8+8.0xce+8.REGS:D1a:::movm
192 
"movm"
193 
*am33
194 
{
195 
  unsigned long usp = State.regs[REG_USP];
196 
  unsigned long mask;
197 
 
198 
  PC = cia;
199 
  mask = REGS;
200 
 
201 
  if (mask & 0x8)
202 
    {
203 
      usp += 4;
204 
      State.regs[REG_LAR] = load_word (usp);
205 
      usp += 4;
206 
      State.regs[REG_LIR] = load_word (usp);
207 
      usp += 4;
208 
      State.regs[REG_MDR] = load_word (usp);
209 
      usp += 4;
210 
      State.regs[REG_A0 + 1] = load_word (usp);
211 
      usp += 4;
212 
      State.regs[REG_A0] = load_word (usp);
213 
      usp += 4;
214 
      State.regs[REG_D0 + 1] = load_word (usp);
215 
      usp += 4;
216 
      State.regs[REG_D0] = load_word (usp);
217 
      usp += 4;
218 
    }
219 
 
220 
  if (mask & 0x10)
221 
    {
222 
      State.regs[REG_A0 + 3] = load_word (usp);
223 
      usp += 4;
224 
    }
225 
 
226 
  if (mask & 0x20)
227 
    {
228 
      State.regs[REG_A0 + 2] = load_word (usp);
229 
      usp += 4;
230 
    }
231 
 
232 
  if (mask & 0x40)
233 
    {
234 
      State.regs[REG_D0 + 3] = load_word (usp);
235 
      usp += 4;
236 
    }
237 
 
238 
  if (mask & 0x80)
239 
    {
240 
      State.regs[REG_D0 + 2] = load_word (usp);
241 
      usp += 4;
242 
    }
243 
 
244 
  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
245 
    {
246 
      if (mask & 0x1)
247 
        {
248 
          /* Need to restore MDQR, MCRH, MCRL, and MCVF */
249 
          usp += 16;
250 
          State.regs[REG_E0 + 1] = load_word (usp);
251 
          usp += 4;
252 
          State.regs[REG_E0 + 0] = load_word (usp);
253 
          usp += 4;
254 
        }
255 
 
256 
      if (mask & 0x2)
257 
        {
258 
          State.regs[REG_E0 + 7] = load_word (usp);
259 
          usp += 4;
260 
          State.regs[REG_E0 + 6] = load_word (usp);
261 
          usp += 4;
262 
          State.regs[REG_E0 + 5] = load_word (usp);
263 
          usp += 4;
264 
          State.regs[REG_E0 + 4] = load_word (usp);
265 
          usp += 4;
266 
        }
267 
 
268 
      if (mask & 0x4)
269 
        {
270 
          State.regs[REG_E0 + 3] = load_word (usp);
271 
          usp += 4;
272 
          State.regs[REG_E0 + 2] = load_word (usp);
273 
          usp += 4;
274 
        }
275 
    }
276 
 
277 
  /* And make sure to update the stack pointer.  */
278 
  State.regs[REG_USP] = usp;
279 
}
280 
 
281 
// 1111 1000 1100 1111 regs....; movm (USP),regs
282 
8.0xf8+8.0xcf+8.REGS:D1b:::movm
283 
"movm"
284 
*am33
285 
{
286 
  unsigned long usp = State.regs[REG_USP];
287 
  unsigned long mask;
288 
 
289 
  if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
290 
    {
291 
      if (mask & 0x4)
292 
        {
293 
          usp -= 4;
294 
          store_word (usp, State.regs[REG_E0 + 2]);
295 
          usp -= 4;
296 
          store_word (usp, State.regs[REG_E0 + 3]);
297 
        }
298 
 
299 
      if (mask & 0x2)
300 
        {
301 
          usp -= 4;
302 
          store_word (usp, State.regs[REG_E0 + 4]);
303 
          usp -= 4;
304 
          store_word (usp, State.regs[REG_E0 + 5]);
305 
          usp -= 4;
306 
          store_word (usp, State.regs[REG_E0 + 6]);
307 
          usp -= 4;
308 
          store_word (usp, State.regs[REG_E0 + 7]);
309 
        }
310 
 
311 
      if (mask & 0x1)
312 
        {
313 
          usp -= 4;
314 
          store_word (usp, State.regs[REG_E0 + 0]);
315 
          usp -= 4;
316 
          store_word (usp, State.regs[REG_E0 + 1]);
317 
          usp -= 16;
318 
          /* Need to save MDQR, MCRH, MCRL, and MCVF */
319 
        }
320 
    }
321 
 
322 
  if (mask & 0x80)
323 
    {
324 
      usp -= 4;
325 
      store_word (usp, State.regs[REG_D0 + 2]);
326 
    }
327 
 
328 
  if (mask & 0x40)
329 
    {
330 
      usp -= 4;
331 
      store_word (usp, State.regs[REG_D0 + 3]);
332 
    }
333 
 
334 
  if (mask & 0x20)
335 
    {
336 
      usp -= 4;
337 
      store_word (usp, State.regs[REG_A0 + 2]);
338 
    }
339 
 
340 
  if (mask & 0x10)
341 
    {
342 
      usp -= 4;
343 
      store_word (usp, State.regs[REG_A0 + 3]);
344 
    }
345 
 
346 
  if (mask & 0x8)
347 
    {
348 
      usp -= 4;
349 
      store_word (usp, State.regs[REG_D0]);
350 
      usp -= 4;
351 
      store_word (usp, State.regs[REG_D0 + 1]);
352 
      usp -= 4;
353 
      store_word (usp, State.regs[REG_A0]);
354 
      usp -= 4;
355 
      store_word (usp, State.regs[REG_A0 + 1]);
356 
      usp -= 4;
357 
      store_word (usp, State.regs[REG_MDR]);
358 
      usp -= 4;
359 
      store_word (usp, State.regs[REG_LIR]);
360 
      usp -= 4;
361 
      store_word (usp, State.regs[REG_LAR]);
362 
      usp -= 4;
363 
    }
364 
 
365 
  /* And make sure to update the stack pointer.  */
366 
  State.regs[REG_USP] = usp;
367 
}
368 
 
369 
// 1111 1100 1111 1100 imm32...; and imm32,EPSW
370 
8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
371 
"and"
372 
*am33
373 
{
374 
  PC = cia;
375 
  PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
376 
}
377 
 
378 
// 1111 1100 1111 1101 imm32...; or imm32,EPSW
379 
8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
380 
"or"
381 
*am33
382 
{
383 
  PC = cia;
384 
  PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
385 
}
386 
 
387 
// 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
388 
8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
389 
"mov"
390 
*am33
391 
{
392 
  int srcreg, dstreg;
393 
 
394 
  PC = cia;
395 
 
396 
  srcreg = translate_rreg (SD_, RM2);
397 
  dstreg = translate_rreg (SD_, RN0);
398 
  State.regs[dstreg] = State.regs[srcreg];
399 
}
400 
 
401 
// 1111 1001 0001 1000 Rn Rn; ext Rn
402 
8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
403 
"mov"
404 
*am33
405 
{
406 
  int srcreg;
407 
 
408 
  PC = cia;
409 
  srcreg = translate_rreg (SD_, RN0);
410 
  if (State.regs[srcreg] & 0x80000000)
411 
    State.regs[REG_MDR] = -1;
412 
  else
413 
    State.regs[REG_MDR] = 0;
414 
}
415 
 
416 
// 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
417 
8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
418 
"extb"
419 
*am33
420 
{
421 
  int srcreg, dstreg;
422 
 
423 
  PC = cia;
424 
  srcreg = translate_rreg (SD_, RM2);
425 
  dstreg = translate_rreg (SD_, RN0);
426 
  State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
427 
}
428 
 
429 
// 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
430 
8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
431 
"extbu"
432 
*am33
433 
{
434 
  int srcreg, dstreg;
435 
 
436 
  PC = cia;
437 
  srcreg = translate_rreg (SD_, RM2);
438 
  dstreg = translate_rreg (SD_, RN0);
439 
  State.regs[dstreg] = State.regs[srcreg] & 0xff;
440 
}
441 
 
442 
// 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
443 
8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
444 
"exth"
445 
*am33
446 
{
447 
  int srcreg, dstreg;
448 
 
449 
  PC = cia;
450 
  srcreg = translate_rreg (SD_, RM2);
451 
  dstreg = translate_rreg (SD_, RN0);
452 
  State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
453 
}
454 
 
455 
// 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
456 
8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
457 
"exthu"
458 
*am33
459 
{
460 
  int srcreg, dstreg;
461 
 
462 
  PC = cia;
463 
  srcreg = translate_rreg (SD_, RM2);
464 
  dstreg = translate_rreg (SD_, RN0);
465 
  State.regs[dstreg] = State.regs[srcreg] & 0xffff;
466 
}
467 
 
468 
// 1111 1001 0110 1000 Rn Rn; clr Rn
469 
8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
470 
"clr"
471 
*am33
472 
{
473 
  int dstreg;
474 
 
475 
  PC = cia;
476 
  dstreg = translate_rreg (SD_, RN0);
477 
  State.regs[dstreg] = 0;
478 
  PSW |= PSW_Z;
479 
  PSW &= ~(PSW_V | PSW_C | PSW_N);
480 
}
481 
 
482 
// 1111 1001 0111 1000 Rm Rn; add Rm,Rn
483 
8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
484 
"add"
485 
*am33
486 
{
487 
  int srcreg, dstreg;
488 
 
489 
  PC = cia;
490 
  srcreg = translate_rreg (SD_, RM2);
491 
  dstreg = translate_rreg (SD_, RN0);
492 
  genericAdd (State.regs[srcreg], dstreg);
493 
}
494 
 
495 
// 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
496 
8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
497 
"addc"
498 
*am33
499 
{
500 
  int srcreg, dstreg;
501 
  int z, c, n, v;
502 
  unsigned long reg1, reg2, sum;
503 
 
504 
  PC = cia;
505 
  srcreg = translate_rreg (SD_, RM2);
506 
  dstreg = translate_rreg (SD_, RN0);
507 
 
508 
  reg1 = State.regs[srcreg];
509 
  reg2 = State.regs[dstreg];
510 
  sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
511 
  State.regs[dstreg] = sum;
512 
 
513 
  z = ((PSW & PSW_Z) != 0) && (sum == 0);
514 
  n = (sum & 0x80000000);
515 
  c = (sum < reg1) || (sum < reg2);
516 
  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
517 
       && (reg2 & 0x80000000) != (sum & 0x80000000));
518 
 
519 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
520 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
521 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
522 
}
523 
 
524 
// 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
525 
8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
526 
"sub"
527 
*am33
528 
{
529 
  int srcreg, dstreg;
530 
 
531 
  PC = cia;
532 
  srcreg = translate_rreg (SD_, RM2);
533 
  dstreg = translate_rreg (SD_, RN0);
534 
  genericSub (State.regs[srcreg], dstreg);
535 
}
536 
 
537 
// 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
538 
8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
539 
"subc"
540 
*am33
541 
{
542 
  int srcreg, dstreg;
543 
  int z, c, n, v;
544 
  unsigned long reg1, reg2, difference;
545 
 
546 
  PC = cia;
547 
  srcreg = translate_rreg (SD_, RM2);
548 
  dstreg = translate_rreg (SD_, RN0);
549 
 
550 
  reg1 = State.regs[srcreg];
551 
  reg2 = State.regs[dstreg];
552 
  difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
553 
  State.regs[dstreg] = difference;
554 
 
555 
  z = ((PSW & PSW_Z) != 0) && (difference == 0);
556 
  n = (difference & 0x80000000);
557 
  c = (reg1 > reg2);
558 
  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
559 
       && (reg2 & 0x80000000) != (difference & 0x80000000));
560 
 
561 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
562 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
563 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
564 
}
565 
 
566 
// 1111 1001 1011 1000 Rn Rn; inc Rn
567 
8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
568 
"inc"
569 
*am33
570 
{
571 
  int dstreg;
572 
 
573 
  PC = cia;
574 
  dstreg = translate_rreg (SD_, RN0);
575 
  genericAdd (1, dstreg);
576 
}
577 
 
578 
// 1111 1001 1101 1000 Rn Rn; inc Rn
579 
8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
580 
"inc4"
581 
*am33
582 
{
583 
  int dstreg;
584 
 
585 
  PC = cia;
586 
  dstreg = translate_rreg (SD_, RN0);
587 
  genericAdd (4, dstreg);
588 
}
589 
 
590 
// 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
591 
8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
592 
"cmp"
593 
*am33
594 
{
595 
  int srcreg1, srcreg2;
596 
 
597 
  PC = cia;
598 
  srcreg1 = translate_rreg (SD_, RN0);
599 
  srcreg2 = translate_rreg (SD_, RM2);
600 
  genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
601 
}
602 
 
603 
// 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
604 
8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
605 
"mov"
606 
*am33
607 
{
608 
  int dstreg, srcreg;
609 
 
610 
  PC = cia;
611 
  dstreg = translate_rreg (SD_, RN0);
612 
  srcreg = translate_xreg (SD_, XRM2);
613 
 
614 
  State.regs[dstreg] = State.regs[srcreg];
615 
}
616 
 
617 
// 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
618 
8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
619 
"mov"
620 
*am33
621 
{
622 
  int srcreg, dstreg;
623 
 
624 
  PC = cia;
625 
  srcreg = translate_rreg (SD_, RM2);
626 
  dstreg = translate_xreg (SD_, XRN0);
627 
 
628 
  State.regs[dstreg] = State.regs[srcreg];
629 
}
630 
 
631 
// 1111 1001 0000 1001 Rm Rn; and Rm,Rn
632 
8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
633 
"and"
634 
*am33
635 
{
636 
  int srcreg, dstreg;
637 
  int z, n;
638 
 
639 
  PC = cia;
640 
 
641 
  srcreg = translate_rreg (SD_, RM2);
642 
  dstreg = translate_rreg (SD_, RN0);
643 
 
644 
  State.regs[dstreg] &= State.regs[srcreg];
645 
  z = (State.regs[dstreg] == 0);
646 
  n = (State.regs[dstreg] & 0x80000000) != 0;
647 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
648 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
649 
}
650 
 
651 
// 1111 1001 0001 1001 Rm Rn; or Rm,Rn
652 
8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
653 
"or"
654 
*am33
655 
{
656 
  int srcreg, dstreg;
657 
  int z, n;
658 
 
659 
  PC = cia;
660 
  srcreg = translate_rreg (SD_, RM2);
661 
  dstreg = translate_rreg (SD_, RN0);
662 
 
663 
  State.regs[dstreg] |= State.regs[srcreg];
664 
  z = (State.regs[dstreg] == 0);
665 
  n = (State.regs[dstreg] & 0x80000000) != 0;
666 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
667 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
668 
}
669 
 
670 
// 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
671 
8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
672 
"xor"
673 
*am33
674 
{
675 
  int srcreg, dstreg;
676 
  int z, n;
677 
 
678 
  PC = cia;
679 
  srcreg = translate_rreg (SD_, RM2);
680 
  dstreg = translate_rreg (SD_, RN0);
681 
 
682 
  State.regs[dstreg] ^= State.regs[srcreg];
683 
  z = (State.regs[dstreg] == 0);
684 
  n = (State.regs[dstreg] & 0x80000000) != 0;
685 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
686 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
687 
}
688 
 
689 
// 1111 1001 0011 1001 Rn Rn; not Rn
690 
8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
691 
"not"
692 
*am33
693 
{
694 
  int dstreg;
695 
  int z, n;
696 
 
697 
  PC = cia;
698 
  dstreg = translate_rreg (SD_, RN0);
699 
 
700 
  State.regs[dstreg] = ~State.regs[dstreg];
701 
  z = (State.regs[dstreg] == 0);
702 
  n = (State.regs[dstreg] & 0x80000000) != 0;
703 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
704 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
705 
}
706 
 
707 
// 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
708 
8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
709 
"asr"
710 
*am33
711 
{
712 
  int srcreg, dstreg;
713 
  long temp;
714 
  int c, z, n;
715 
 
716 
  PC = cia;
717 
  srcreg = translate_rreg (SD_, RM2);
718 
  dstreg = translate_rreg (SD_, RN0);
719 
 
720 
  temp = State.regs[dstreg];
721 
  c = temp & 1;
722 
  temp >>= State.regs[srcreg];
723 
  State.regs[dstreg] = temp;
724 
  z = (State.regs[dstreg] == 0);
725 
  n = (State.regs[dstreg] & 0x80000000) != 0;
726 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
727 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
728 
}
729 
 
730 
// 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
731 
8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
732 
"lsr"
733 
*am33
734 
{
735 
  int srcreg, dstreg;
736 
  int z, n, c;
737 
 
738 
  PC = cia;
739 
 
740 
  srcreg = translate_rreg (SD_, RM2);
741 
  dstreg = translate_rreg (SD_, RN0);
742 
 
743 
  c = State.regs[dstreg] & 1;
744 
  State.regs[dstreg] >>= State.regs[srcreg];
745 
  z = (State.regs[dstreg] == 0);
746 
  n = (State.regs[dstreg] & 0x80000000) != 0;
747 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
748 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
749 
}
750 
 
751 
// 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
752 
8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
753 
"asl"
754 
*am33
755 
{
756 
  int srcreg, dstreg;
757 
  int z, n;
758 
 
759 
  PC = cia;
760 
  srcreg = translate_rreg (SD_, RM2);
761 
  dstreg = translate_rreg (SD_, RN0);
762 
 
763 
  State.regs[dstreg] <<= State.regs[srcreg];
764 
  z = (State.regs[dstreg] == 0);
765 
  n = (State.regs[dstreg] & 0x80000000) != 0;
766 
  PSW &= ~(PSW_Z | PSW_N);
767 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
768 
}
769 
 
770 
// 1111 1001 0111 1001 Rn Rn; asl2 Rn
771 
8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
772 
"asl2"
773 
*am33
774 
{
775 
  int dstreg;
776 
  int n, z;
777 
 
778 
  PC = cia;
779 
  dstreg = translate_rreg (SD_, RN0);
780 
 
781 
  State.regs[dstreg] <<= 2;
782 
  z = (State.regs[dstreg] == 0);
783 
  n = (State.regs[dstreg] & 0x80000000) != 0;
784 
  PSW &= ~(PSW_Z | PSW_N);
785 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
786 
}
787 
 
788 
// 1111 1001 1000 1001 Rn Rn; ror Rn
789 
8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
790 
"ror"
791 
*am33
792 
{
793 
  int dstreg;
794 
  int c, n, z;
795 
  unsigned long value;
796 
 
797 
  PC = cia;
798 
  dstreg = translate_rreg (SD_, RN0);
799 
 
800 
  value = State.regs[dstreg];
801 
  c = (value & 0x1);
802 
 
803 
  value >>= 1;
804 
  value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
805 
  State.regs[dstreg] = value;
806 
  z = (value == 0);
807 
  n = (value & 0x80000000) != 0;
808 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
809 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
810 
}
811 
 
812 
// 1111 1001 1001 1001 Rn Rn; rol Rn
813 
8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
814 
"rol"
815 
*am33
816 
{
817 
  int dstreg;
818 
  int c, n, z;
819 
  unsigned long value;
820 
 
821 
  PC = cia;
822 
  dstreg = translate_rreg (SD_, RN0);
823 
 
824 
  value = State.regs[dstreg];
825 
  c = (value & 0x80000000) ? 1 : 0;
826 
 
827 
  value <<= 1;
828 
  value |= ((PSW & PSW_C) != 0);
829 
  State.regs[dstreg] = value;
830 
  z = (value == 0);
831 
  n = (value & 0x80000000) != 0;
832 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
833 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
834 
}
835 
 
836 
// 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
837 
8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
838 
"mul"
839 
*am33
840 
{
841 
  int srcreg, dstreg;
842 
  unsigned long long temp;
843 
  int n, z;
844 
 
845 
  PC = cia;
846 
  srcreg = translate_rreg (SD_, RM2);
847 
  dstreg = translate_rreg (SD_, RN0);
848 
 
849 
  temp = ((signed64)(signed32)State.regs[dstreg]
850 
          *  (signed64)(signed32)State.regs[srcreg]);
851 
  State.regs[dstreg] = temp & 0xffffffff;
852 
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
853 
  z = (State.regs[dstreg] == 0);
854 
  n = (State.regs[dstreg] & 0x80000000) != 0;
855 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
856 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
857 
}
858 
 
859 
// 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
860 
8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
861 
"mulu"
862 
*am33
863 
{
864 
  int srcreg, dstreg;
865 
  unsigned long long temp;
866 
  int n, z;
867 
 
868 
  PC = cia;
869 
  srcreg = translate_rreg (SD_, RM2);
870 
  dstreg = translate_rreg (SD_, RN0);
871 
 
872 
  temp = ((unsigned64)State.regs[dstreg]
873 
          * (unsigned64)State.regs[srcreg]);
874 
  State.regs[dstreg] = temp & 0xffffffff;
875 
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
876 
  z = (State.regs[dstreg] == 0);
877 
  n = (State.regs[dstreg] & 0x80000000) != 0;
878 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
879 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
880 
}
881 
 
882 
// 1111 1001 1100 1001 Rm Rn; div Rm,Rn
883 
8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
884 
"div"
885 
*am33
886 
{
887 
  int srcreg, dstreg;
888 
  long long temp;
889 
  int n, z;
890 
 
891 
  PC = cia;
892 
  srcreg = translate_rreg (SD_, RM2);
893 
  dstreg = translate_rreg (SD_, RN0);
894 
 
895 
  temp = State.regs[REG_MDR];
896 
  temp <<= 32;
897 
  temp |= State.regs[dstreg];
898 
  State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
899 
  temp /= (signed32)State.regs[srcreg];
900 
  State.regs[dstreg] = temp & 0xffffffff;
901 
  z = (State.regs[dstreg] == 0);
902 
  n = (State.regs[dstreg] & 0x80000000) != 0;
903 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
904 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
905 
}
906 
 
907 
// 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
908 
8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
909 
"divu"
910 
*am33
911 
{
912 
  int srcreg, dstreg;
913 
  unsigned long long temp;
914 
  int n, z;
915 
 
916 
  PC = cia;
917 
  srcreg = translate_rreg (SD_, RM2);
918 
  dstreg = translate_rreg (SD_, RN0);
919 
 
920 
  temp = State.regs[REG_MDR];
921 
  temp <<= 32;
922 
  temp |= State.regs[dstreg];
923 
  State.regs[REG_MDR] = temp % State.regs[srcreg];
924 
  temp /= State.regs[srcreg];
925 
  State.regs[dstreg] = temp & 0xffffffff;
926 
  z = (State.regs[dstreg] == 0);
927 
  n = (State.regs[dstreg] & 0x80000000) != 0;
928 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
929 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
930 
}
931 
 
932 
 
933 
// 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
934 
8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
935 
"mov"
936 
*am33
937 
{
938 
  int srcreg, dstreg;
939 
 
940 
  PC = cia;
941 
  srcreg = translate_rreg (SD_, RM0);
942 
  dstreg = translate_rreg (SD_, RN2);
943 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
944 
}
945 
 
946 
// 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
947 
8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
948 
"mov"
949 
*am33
950 
{
951 
  int srcreg, dstreg;
952 
 
953 
  PC = cia;
954 
  srcreg = translate_rreg (SD_, RM2);
955 
  dstreg = translate_rreg (SD_, RN0);
956 
  store_word (State.regs[dstreg], State.regs[srcreg]);
957 
}
958 
 
959 
// 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
960 
8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
961 
"movbu"
962 
*am33
963 
{
964 
  int srcreg, dstreg;
965 
 
966 
  PC = cia;
967 
  srcreg = translate_rreg (SD_, RM0);
968 
  dstreg = translate_rreg (SD_, RN2);
969 
  State.regs[dstreg] = load_byte (State.regs[srcreg]);
970 
}
971 
 
972 
// 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
973 
8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
974 
"movbu"
975 
*am33
976 
{
977 
  int srcreg, dstreg;
978 
 
979 
  PC = cia;
980 
  srcreg = translate_rreg (SD_, RM2);
981 
  dstreg = translate_rreg (SD_, RN0);
982 
  store_byte (State.regs[dstreg], State.regs[srcreg]);
983 
}
984 
 
985 
// 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
986 
8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
987 
"movhu"
988 
*am33
989 
{
990 
  int srcreg, dstreg;
991 
 
992 
  PC = cia;
993 
  srcreg = translate_rreg (SD_, RM0);
994 
  dstreg = translate_rreg (SD_, RN2);
995 
  State.regs[dstreg] = load_half (State.regs[srcreg]);
996 
}
997 
 
998 
// 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
999 
8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1000 
"movhu"
1001 
*am33
1002 
{
1003 
  int srcreg, dstreg;
1004 
 
1005 
  PC = cia;
1006 
  srcreg = translate_rreg (SD_, RM2);
1007 
  dstreg = translate_rreg (SD_, RN0);
1008 
  store_half (State.regs[dstreg], State.regs[srcreg]);
1009 
}
1010 
 
1011 
// 1111 1001 0110 1010 Rm Rn; mov (Rm+),Rn
1012 
8.0xf9+8.0x6a+4.RN2,4.RM0!RN2:D1y:::mov
1013 
"mov"
1014 
*am33
1015 
{
1016 
  int srcreg, dstreg;
1017 
 
1018 
  PC = cia;
1019 
  srcreg = translate_rreg (SD_, RM0);
1020 
  dstreg = translate_rreg (SD_, RN2);
1021 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
1022 
  State.regs[srcreg] += 4;
1023 
}
1024 
 
1025 
// 1111 1001 0111 1010 Rm Rn; mov Rm,(Rn+)
1026 
8.0xf9+8.0x7a+4.RM2,4.RN0:D1z:::mov
1027 
"mov"
1028 
*am33
1029 
{
1030 
  int srcreg, dstreg;
1031 
 
1032 
  PC = cia;
1033 
  srcreg = translate_rreg (SD_, RM2);
1034 
  dstreg = translate_rreg (SD_, RN0);
1035 
  store_word (State.regs[dstreg], State.regs[srcreg]);
1036 
  State.regs[dstreg] += 4;
1037 
}
1038 
 
1039 
// 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1040 
8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1041 
"mov"
1042 
*am33
1043 
{
1044 
  int dstreg;
1045 
 
1046 
  PC = cia;
1047 
  dstreg = translate_rreg (SD_, RN2);
1048 
  State.regs[dstreg] = load_word (State.regs[REG_SP]);
1049 
}
1050 
 
1051 
// 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1052 
8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1053 
"mov"
1054 
*am33
1055 
{
1056 
  int srcreg;
1057 
 
1058 
  PC = cia;
1059 
  srcreg = translate_rreg (SD_, RM2);
1060 
  store_word (State.regs[REG_SP], State.regs[srcreg]);
1061 
}
1062 
 
1063 
// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1064 
8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1065 
"movbu"
1066 
*am33
1067 
{
1068 
  int dstreg;
1069 
 
1070 
  PC = cia;
1071 
  dstreg = translate_rreg (SD_, RN2);
1072 
  State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1073 
}
1074 
 
1075 
// 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1076 
8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1077 
"movbu"
1078 
*am33
1079 
{
1080 
  int srcreg;
1081 
 
1082 
  PC = cia;
1083 
  srcreg = translate_rreg (SD_, RM2);
1084 
  store_byte (State.regs[REG_SP], State.regs[srcreg]);
1085 
}
1086 
 
1087 
// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1088 
8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1089 
"movhu"
1090 
*am33
1091 
{
1092 
  int dstreg;
1093 
 
1094 
  PC = cia;
1095 
  dstreg = translate_rreg (SD_, RN2);
1096 
  State.regs[dstreg] = load_half (State.regs[REG_SP]);
1097 
}
1098 
 
1099 
// 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1100 
8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1101 
"movhu"
1102 
*am33
1103 
{
1104 
  int srcreg;
1105 
 
1106 
  PC = cia;
1107 
  srcreg = translate_rreg (SD_, RM2);
1108 
  store_half (State.regs[REG_SP], State.regs[srcreg]);
1109 
}
1110 
 
1111 
// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
1112 
8.0xf9+8.0xea+4.RN2,4.RM0!RN2:D1y:::movhu
1113 
"movhu"
1114 
*am33
1115 
{
1116 
  int srcreg, dstreg;
1117 
 
1118 
  PC = cia;
1119 
  srcreg = translate_rreg (SD_, RM0);
1120 
  dstreg = translate_rreg (SD_, RN2);
1121 
  State.regs[dstreg] = load_half (State.regs[srcreg]);
1122 
  State.regs[srcreg] += 2;
1123 
}
1124 
 
1125 
// 1111 1001 1111 1010 Rm Rn; movhu Rm,(Rn+)
1126 
8.0xf9+8.0xfa+4.RM2,4.RN0:D1z:::movhu
1127 
"movhu"
1128 
*am33
1129 
{
1130 
  int srcreg, dstreg;
1131 
 
1132 
  PC = cia;
1133 
  srcreg = translate_rreg (SD_, RM2);
1134 
  dstreg = translate_rreg (SD_, RN0);
1135 
  store_half (State.regs[dstreg], State.regs[srcreg]);
1136 
  State.regs[dstreg] += 2;
1137 
}
1138 
 
1139 
 
1140 
// 1111 1001 0000 1011 Rm Rn; mac Rm,Rn
1141 
8.0xf9+8.0x0b+4.RM2,4.RN0:D1:::mac
1142 
"mac"
1143 
*am33
1144 
{
1145 
  int srcreg1, srcreg2;
1146 
  long long temp, sum;
1147 
  int c, v;
1148 
 
1149 
  PC = cia;
1150 
  srcreg1 = translate_rreg (SD_, RM2);
1151 
  srcreg2 = translate_rreg (SD_, RN0);
1152 
 
1153 
  temp = ((signed64)(signed32)State.regs[srcreg2]
1154 
          * (signed64)(signed32)State.regs[srcreg1]);
1155 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1156 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1157 
  State.regs[REG_MCRL] = sum;
1158 
  temp >>= 32;
1159 
  temp &= 0xffffffff;
1160 
  sum = State.regs[REG_MCRH] + temp + c;
1161 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1162 
        && (temp & 0x80000000) != (sum & 0x80000000));
1163 
  State.regs[REG_MCRH] = sum;
1164 
  if (v)
1165 
    State.regs[REG_MCVF] = 1;
1166 
}
1167 
 
1168 
// 1111 1001 0001 1011 Rm Rn; macu Rm,Rn
1169 
8.0xf9+8.0x1b+4.RM2,4.RN0:D1:::macu
1170 
"macu"
1171 
*am33
1172 
{
1173 
  int srcreg1, srcreg2;
1174 
  unsigned long long temp, sum;
1175 
  int c, v;
1176 
 
1177 
  PC = cia;
1178 
  srcreg1 = translate_rreg (SD_, RM2);
1179 
  srcreg2 = translate_rreg (SD_, RN0);
1180 
 
1181 
  temp = ((unsigned64)State.regs[srcreg2]
1182 
          * (unsigned64)State.regs[srcreg1]);
1183 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1184 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1185 
  State.regs[REG_MCRL] = sum;
1186 
  temp >>= 32;
1187 
  temp &= 0xffffffff;
1188 
  sum = State.regs[REG_MCRH] + temp + c;
1189 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1190 
        && (temp & 0x80000000) != (sum & 0x80000000));
1191 
  State.regs[REG_MCRH] = sum;
1192 
  if (v)
1193 
    State.regs[REG_MCVF] = 1;
1194 
}
1195 
 
1196 
// 1111 1001 0010 1011 Rm Rn; macb Rm,Rn
1197 
8.0xf9+8.0x2b+4.RM2,4.RN0:D1:::macb
1198 
"macb"
1199 
*am33
1200 
{
1201 
  int srcreg1, srcreg2;
1202 
  long temp, sum;
1203 
  int v;
1204 
 
1205 
  PC = cia;
1206 
  srcreg1 = translate_rreg (SD_, RM2);
1207 
  srcreg2 = translate_rreg (SD_, RN0);
1208 
 
1209 
  temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
1210 
          * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
1211 
  sum = State.regs[REG_MCRL] + temp;
1212 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1213 
        && (temp & 0x80000000) != (sum & 0x80000000));
1214 
  State.regs[REG_MCRL] = sum;
1215 
  if (v)
1216 
    State.regs[REG_MCVF] = 1;
1217 
}
1218 
 
1219 
// 1111 1001 0011 1011 Rm Rn; macbu Rm,Rn
1220 
8.0xf9+8.0x3b+4.RM2,4.RN0:D1:::macbu
1221 
"macbu"
1222 
*am33
1223 
{
1224 
  int srcreg1, srcreg2;
1225 
  long long temp, sum;
1226 
  int v;
1227 
 
1228 
  PC = cia;
1229 
  srcreg1 = translate_rreg (SD_, RM2);
1230 
  srcreg2 = translate_rreg (SD_, RN0);
1231 
 
1232 
  temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
1233 
          * (unsigned32)(State.regs[srcreg1] & 0xff));
1234 
  sum = State.regs[REG_MCRL] + temp;
1235 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1236 
        && (temp & 0x80000000) != (sum & 0x80000000));
1237 
  State.regs[REG_MCRL] = sum;
1238 
  if (v)
1239 
    State.regs[REG_MCVF] = 1;
1240 
}
1241 
 
1242 
// 1111 1001 0100 1011 Rm Rn; mach Rm,Rn
1243 
8.0xf9+8.0x4b+4.RM2,4.RN0:D1:::mach
1244 
"mach"
1245 
*am33
1246 
{
1247 
  int srcreg1, srcreg2;
1248 
  long long temp, sum;
1249 
  int c, v;
1250 
 
1251 
  PC = cia;
1252 
  srcreg1 = translate_rreg (SD_, RM2);
1253 
  srcreg2 = translate_rreg (SD_, RN0);
1254 
 
1255 
  temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
1256 
          * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
1257 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1258 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1259 
  State.regs[REG_MCRL] = sum;
1260 
  temp >>= 32;
1261 
  temp &= 0xffffffff;
1262 
  sum = State.regs[REG_MCRH] + temp + c;
1263 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1264 
        && (temp & 0x80000000) != (sum & 0x80000000));
1265 
  State.regs[REG_MCRH] = sum;
1266 
  if (v)
1267 
    State.regs[REG_MCVF] = 1;
1268 
}
1269 
 
1270 
// 1111 1001 0101 1011 Rm Rn; machu Rm,Rn
1271 
8.0xf9+8.0x5b+4.RM2,4.RN0:D1:::machu
1272 
"machu"
1273 
*am33
1274 
{
1275 
  int srcreg1, srcreg2;
1276 
  long long temp, sum;
1277 
  int c, v;
1278 
 
1279 
  PC = cia;
1280 
  srcreg1 = translate_rreg (SD_, RM2);
1281 
  srcreg2 = translate_rreg (SD_, RN0);
1282 
 
1283 
  temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
1284 
          * (unsigned64)(State.regs[srcreg1] & 0xffff));
1285 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
1286 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
1287 
  State.regs[REG_MCRL] = sum;
1288 
  temp >>= 32;
1289 
  temp &= 0xffffffff;
1290 
  sum = State.regs[REG_MCRH] + temp + c;
1291 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
1292 
        && (temp & 0x80000000) != (sum & 0x80000000));
1293 
  State.regs[REG_MCRH] = sum;
1294 
  if (v)
1295 
    State.regs[REG_MCVF] = 1;
1296 
}
1297 
 
1298 
// 1111 1001 0110 1011 Rm Rn; dmach Rm,Rn
1299 
8.0xf9+8.0x6b+4.RM2,4.RN0:D1:::dmach
1300 
"dmach"
1301 
*am33
1302 
{
1303 
  int srcreg1, srcreg2;
1304 
  long temp, temp2, sum;
1305 
  int v;
1306 
 
1307 
  PC = cia;
1308 
  srcreg1 = translate_rreg (SD_, RM2);
1309 
  srcreg2 = translate_rreg (SD_, RN0);
1310 
 
1311 
  temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
1312 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
1313 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
1314 
           * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
1315 
  sum = temp + temp2 + State.regs[REG_MCRL];
1316 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1317 
        && (temp & 0x80000000) != (sum & 0x80000000));
1318 
  State.regs[REG_MCRL] = sum;
1319 
  if (v)
1320 
    State.regs[REG_MCVF] = 1;
1321 
}
1322 
 
1323 
// 1111 1001 0111 1011 Rm Rn; dmachu Rm,Rn
1324 
8.0xf9+8.0x7b+4.RM2,4.RN0:D1:::dmachu
1325 
"dmachu"
1326 
*am33
1327 
{
1328 
  int srcreg1, srcreg2;
1329 
  unsigned long temp, temp2, sum;
1330 
  int v;
1331 
 
1332 
  PC = cia;
1333 
  srcreg1 = translate_rreg (SD_, RM2);
1334 
  srcreg2 = translate_rreg (SD_, RN0);
1335 
 
1336 
  temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
1337 
          * (unsigned32)(State.regs[srcreg1] & 0xffff));
1338 
  temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
1339 
           * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
1340 
  sum = temp + temp2 + State.regs[REG_MCRL];
1341 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
1342 
        && (temp & 0x80000000) != (sum & 0x80000000));
1343 
  State.regs[REG_MCRL] = sum;
1344 
  if (v)
1345 
    State.regs[REG_MCVF] = 1;
1346 
}
1347 
 
1348 
// 1111 1001 1000 1011 Rm Rn; dmulh Rm,Rn
1349 
8.0xf9+8.0x8b+4.RM2,4.RN0:D1:::dmulh
1350 
"dmulh"
1351 
*am33
1352 
{
1353 
  int srcreg, dstreg;
1354 
  long temp;
1355 
 
1356 
  PC = cia;
1357 
  srcreg = translate_rreg (SD_, RM2);
1358 
  dstreg = translate_rreg (SD_, RN0);
1359 
 
1360 
  temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
1361 
          * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
1362 
  State.regs[REG_MDRQ] = temp;
1363 
  temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
1364 
          * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
1365 
  State.regs[dstreg] = temp;
1366 
}
1367 
 
1368 
// 1111 1001 1001 1011 Rm Rn; dmulhu Rm,Rn
1369 
8.0xf9+8.0x9b+4.RM2,4.RN0:D1:::dumachu
1370 
"dmachu"
1371 
*am33
1372 
{
1373 
  int srcreg, dstreg;
1374 
  unsigned long temp;
1375 
 
1376 
  PC = cia;
1377 
  srcreg = translate_rreg (SD_, RM2);
1378 
  dstreg = translate_rreg (SD_, RN0);
1379 
 
1380 
  temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
1381 
          * (unsigned32)(State.regs[srcreg] & 0xffff));
1382 
  State.regs[REG_MDRQ] = temp;
1383 
  temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
1384 
          * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
1385 
  State.regs[dstreg] = temp;
1386 
}
1387 
 
1388 
// 1111 1001 1010 1011 Rm Rn; sat16 Rm,Rn
1389 
8.0xf9+8.0xab+4.RM2,4.RN0:D1:::sat16
1390 
"sat16"
1391 
*am33
1392 
{
1393 
  int srcreg, dstreg;
1394 
  int value, z, n;
1395 
 
1396 
  PC = cia;
1397 
  srcreg = translate_rreg (SD_, RM2);
1398 
  dstreg = translate_rreg (SD_, RN0);
1399 
 
1400 
  value = State.regs[srcreg];
1401 
 
1402 
  if (value >= 0x7fff)
1403 
    State.regs[dstreg] = 0x7fff;
1404 
  else if (value <= 0xffff8000)
1405 
    State.regs[dstreg] = 0xffff8000;
1406 
  else
1407 
    State.regs[dstreg] = value;
1408 
 
1409 
  n = (State.regs[dstreg] & 0x8000) != 0;
1410 
  z = (State.regs[dstreg] == 0);
1411 
  PSW &= ~(PSW_Z | PSW_N);
1412 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1413 
}
1414 
 
1415 
// 1111 1001 1011 1011 Rm Rn; mcste Rm,Rn
1416 
8.0xf9+8.0xbb+4.RM2,4.RN0:D1:::mcste
1417 
"mcste"
1418 
*am33
1419 
{
1420 
  int srcreg, dstreg;
1421 
 
1422 
  PC = cia;
1423 
  srcreg = translate_rreg (SD_, RM2);
1424 
  dstreg = translate_rreg (SD_, RN0);
1425 
 
1426 
  PSW &= ~(PSW_V | PSW_C);
1427 
  PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
1428 
 
1429 
  /* 32bit saturation.  */
1430 
  if (State.regs[srcreg] == 0x20)
1431 
    {
1432 
      long long tmp;
1433 
 
1434 
      tmp = State.regs[REG_MCRH];
1435 
      tmp <<= 32;
1436 
      tmp += State.regs[REG_MCRL];
1437 
 
1438 
      if (tmp > 0x7fffffff)
1439 
        State.regs[dstreg] = 0x7fffffff;
1440 
      else if (tmp < 0xffffffff80000000LL)
1441 
        State.regs[dstreg] = 0x80000000;
1442 
      else
1443 
        State.regs[dstreg] = tmp;
1444 
    }
1445 
  /* 16bit saturation */
1446 
  else if (State.regs[srcreg] == 0x10)
1447 
    {
1448 
      long long tmp;
1449 
 
1450 
      tmp = State.regs[REG_MCRH];
1451 
      tmp <<= 32;
1452 
      tmp += State.regs[REG_MCRL];
1453 
 
1454 
      if (tmp > 0x7fff)
1455 
        State.regs[dstreg] = 0x7fff;
1456 
      else if (tmp < 0xffffffffffff8000LL)
1457 
        State.regs[dstreg] = 0x8000;
1458 
      else
1459 
        State.regs[dstreg] = tmp;
1460 
    }
1461 
  /* 8 bit saturation */
1462 
  else if (State.regs[srcreg] == 0x8)
1463 
    {
1464 
      long long tmp;
1465 
 
1466 
      tmp = State.regs[REG_MCRH];
1467 
      tmp <<= 32;
1468 
      tmp += State.regs[REG_MCRL];
1469 
 
1470 
      if (tmp > 0x7f)
1471 
        State.regs[dstreg] = 0x7f;
1472 
      else if (tmp < 0xffffffffffffff80LL)
1473 
        State.regs[dstreg] = 0x80;
1474 
      else
1475 
        State.regs[dstreg] = tmp;
1476 
    }
1477 
  /* 9 bit saturation */
1478 
  else if (State.regs[srcreg] == 0x9)
1479 
    {
1480 
      long long tmp;
1481 
 
1482 
      tmp = State.regs[REG_MCRH];
1483 
      tmp <<= 32;
1484 
      tmp += State.regs[REG_MCRL];
1485 
 
1486 
      if (tmp > 0x80)
1487 
        State.regs[dstreg] = 0x80;
1488 
      else if (tmp < 0xffffffffffffff81LL)
1489 
        State.regs[dstreg] = 0x81;
1490 
      else
1491 
        State.regs[dstreg] = tmp;
1492 
    }
1493 
  /* 9 bit saturation */
1494 
  else if (State.regs[srcreg] == 0x30)
1495 
    {
1496 
      long long tmp;
1497 
 
1498 
      tmp = State.regs[REG_MCRH];
1499 
      tmp <<= 32;
1500 
      tmp += State.regs[REG_MCRL];
1501 
 
1502 
      if (tmp > 0x7fffffffffffLL)
1503 
        tmp = 0x7fffffffffffLL;
1504 
      else if (tmp < 0xffff800000000000LL)
1505 
        tmp = 0xffff800000000000LL;
1506 
 
1507 
      tmp >>= 16;
1508 
      State.regs[dstreg] = tmp;
1509 
    }
1510 
}
1511 
 
1512 
// 1111 1001 1100 1011 Rm Rn; swap Rm,Rn
1513 
8.0xf9+8.0xcb+4.RM2,4.RN0:D1:::swap
1514 
"swap"
1515 
*am33
1516 
{
1517 
  int srcreg, dstreg;
1518 
 
1519 
  PC = cia;
1520 
  srcreg = translate_rreg (SD_, RM2);
1521 
  dstreg = translate_rreg (SD_, RN0);
1522 
 
1523 
  State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
1524 
                        | (((State.regs[srcreg] >> 8) & 0xff) << 16)
1525 
                        | (((State.regs[srcreg] >> 16) & 0xff) << 8)
1526 
                        | ((State.regs[srcreg] >> 24) & 0xff));
1527 
}
1528 
 
1529 
// 1111 1101 1101 1011 Rm Rn; swaph Rm,Rn
1530 
8.0xf9+8.0xdb+4.RM2,4.RN0:D1:::swaph
1531 
"swaph"
1532 
*am33
1533 
{
1534 
  int srcreg, dstreg;
1535 
 
1536 
  PC = cia;
1537 
  srcreg = translate_rreg (SD_, RM2);
1538 
  dstreg = translate_rreg (SD_, RN0);
1539 
 
1540 
  State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
1541 
                        | ((State.regs[srcreg] >> 8) & 0xff)
1542 
                        | (((State.regs[srcreg] >> 16) & 0xff) << 24)
1543 
                        | (((State.regs[srcreg] >> 24) & 0xff) << 16));
1544 
}
1545 
 
1546 
// 1111 1001 1110 1011 Rm Rn; swhw Rm,Rn
1547 
8.0xf9+8.0xeb+4.RM2,4.RN0:D1:::swhw
1548 
"swhw"
1549 
*am33
1550 
{
1551 
  int srcreg, dstreg;
1552 
 
1553 
  PC = cia;
1554 
  srcreg = translate_rreg (SD_, RM2);
1555 
  dstreg = translate_rreg (SD_, RN0);
1556 
 
1557 
  State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
1558 
                        | ((State.regs[srcreg] >> 16) & 0xffff));
1559 
}
1560 
 
1561 
// 1111 1001 1111 1011 Rm Rn; bsch Rm,Rn
1562 
8.0xf9+8.0xfb+4.RM2,4.RN0:D1:::bsch
1563 
"bsch"
1564 
*am33
1565 
{
1566 
  int temp, c, i;
1567 
  int srcreg, dstreg;
1568 
  int start;
1569 
 
1570 
  PC = cia;
1571 
  srcreg = translate_rreg (SD_, RM2);
1572 
  dstreg = translate_rreg (SD_, RN0);
1573 
 
1574 
  temp = State.regs[srcreg];
1575 
  start = (State.regs[dstreg] & 0x1f) - 1;
1576 
  if (start == -1)
1577 
    start = 31;
1578 
 
1579 
  for (i = start; i >= 0; i--)
1580 
    {
1581 
      if (temp & (1 << i))
1582 
        {
1583 
          c = 1;
1584 
          State.regs[dstreg] = i;
1585 
          break;
1586 
        }
1587 
    }
1588 
 
1589 
  if (i < 0)
1590 
    {
1591 
      c = 0;
1592 
      State.regs[dstreg] = 0;
1593 
    }
1594 
  PSW &= ~(PSW_C);
1595 
  PSW |= (c ? PSW_C : 0);
1596 
}
1597 
 
1598 
 
1599 
// 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1600 
8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1601 
"mov"
1602 
*am33
1603 
{
1604 
  int dstreg;
1605 
 
1606 
  PC = cia;
1607 
  dstreg = translate_rreg (SD_, RN0);
1608 
  State.regs[dstreg] = EXTEND8 (IMM8);
1609 
}
1610 
 
1611 
// 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1612 
8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1613 
"movu"
1614 
*am33
1615 
{
1616 
  int dstreg;
1617 
 
1618 
  PC = cia;
1619 
  dstreg = translate_rreg (SD_, RN0);
1620 
  State.regs[dstreg] = IMM8 & 0xff;
1621 
}
1622 
 
1623 
// 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1624 
8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1625 
"add"
1626 
*am33
1627 
{
1628 
  int dstreg;
1629 
 
1630 
  PC = cia;
1631 
  dstreg = translate_rreg (SD_, RN0);
1632 
  genericAdd (EXTEND8 (IMM8), dstreg);
1633 
}
1634 
 
1635 
// 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1636 
8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1637 
"addc"
1638 
*am33
1639 
{
1640 
  int dstreg, imm;
1641 
  int z, c, n, v;
1642 
  unsigned long reg1, reg2, sum;
1643 
 
1644 
  PC = cia;
1645 
  dstreg = translate_rreg (SD_, RN0);
1646 
 
1647 
  imm = EXTEND8 (IMM8);
1648 
  reg2 = State.regs[dstreg];
1649 
  sum = imm + reg2 + ((PSW & PSW_C) != 0);
1650 
  State.regs[dstreg] = sum;
1651 
 
1652 
  z = ((PSW & PSW_Z) != 0) && (sum == 0);
1653 
  n = (sum & 0x80000000);
1654 
  c = (sum < imm) || (sum < reg2);
1655 
  v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1656 
       && (reg2 & 0x80000000) != (sum & 0x80000000));
1657 
 
1658 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1659 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1660 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1661 
}
1662 
 
1663 
// 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1664 
8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1665 
"sub"
1666 
*am33
1667 
{
1668 
  int dstreg;
1669 
 
1670 
  PC = cia;
1671 
  dstreg = translate_rreg (SD_, RN0);
1672 
 
1673 
  genericSub (EXTEND8 (IMM8), dstreg);
1674 
}
1675 
 
1676 
// 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1677 
8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1678 
"subc"
1679 
*am33
1680 
{
1681 
  int imm, dstreg;
1682 
  int z, c, n, v;
1683 
  unsigned long reg1, reg2, difference;
1684 
 
1685 
  PC = cia;
1686 
  dstreg = translate_rreg (SD_, RN0);
1687 
 
1688 
  imm = EXTEND8 (IMM8);
1689 
  reg2 = State.regs[dstreg];
1690 
  difference = reg2 - imm - ((PSW & PSW_C) != 0);
1691 
  State.regs[dstreg] = difference;
1692 
 
1693 
  z = ((PSW & PSW_Z) != 0) && (difference == 0);
1694 
  n = (difference & 0x80000000);
1695 
  c = (imm > reg2);
1696 
  v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1697 
       && (reg2 & 0x80000000) != (difference & 0x80000000));
1698 
 
1699 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1700 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1701 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1702 
}
1703 
 
1704 
// 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1705 
8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1706 
"cmp"
1707 
*am33
1708 
{
1709 
  int srcreg;
1710 
 
1711 
  PC = cia;
1712 
  srcreg = translate_rreg (SD_, RN0);
1713 
  genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1714 
}
1715 
 
1716 
// 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1717 
8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1718 
"mov"
1719 
*am33
1720 
{
1721 
  int dstreg;
1722 
 
1723 
  PC = cia;
1724 
  dstreg = translate_xreg (SD_, XRN0);
1725 
 
1726 
  State.regs[dstreg] = IMM8;
1727 
}
1728 
 
1729 
// 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1730 
8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1731 
"and"
1732 
*am33
1733 
{
1734 
  int dstreg;
1735 
  int z, n;
1736 
 
1737 
  PC = cia;
1738 
  dstreg = translate_rreg (SD_, RN0);
1739 
 
1740 
  State.regs[dstreg] &= (IMM8 & 0xff);
1741 
  z = (State.regs[dstreg] == 0);
1742 
  n = (State.regs[dstreg] & 0x80000000) != 0;
1743 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1744 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1745 
}
1746 
 
1747 
// 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1748 
8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1749 
"or"
1750 
*am33
1751 
{
1752 
  int dstreg;
1753 
  int z, n;
1754 
 
1755 
  PC = cia;
1756 
  dstreg = translate_rreg (SD_, RN0);
1757 
 
1758 
  State.regs[dstreg] |= (IMM8 & 0xff);
1759 
  z = (State.regs[dstreg] == 0);
1760 
  n = (State.regs[dstreg] & 0x80000000) != 0;
1761 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1762 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1763 
}
1764 
 
1765 
// 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1766 
8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1767 
"xor"
1768 
*am33
1769 
{
1770 
  int dstreg;
1771 
  int z, n;
1772 
 
1773 
  PC = cia;
1774 
  dstreg = translate_rreg (SD_, RN0);
1775 
 
1776 
  State.regs[dstreg] ^= (IMM8 & 0xff);
1777 
  z = (State.regs[dstreg] == 0);
1778 
  n = (State.regs[dstreg] & 0x80000000) != 0;
1779 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1780 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1781 
}
1782 
 
1783 
// 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1784 
8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1785 
"asr"
1786 
*am33
1787 
{
1788 
  int dstreg;
1789 
  long temp;
1790 
  int c, z, n;
1791 
 
1792 
  PC = cia;
1793 
  dstreg = translate_rreg (SD_, RN0);
1794 
 
1795 
  temp = State.regs[dstreg];
1796 
  c = temp & 1;
1797 
  temp >>= (IMM8 & 0xff);
1798 
  State.regs[dstreg] = temp;
1799 
  z = (State.regs[dstreg] == 0);
1800 
  n = (State.regs[dstreg] & 0x80000000) != 0;
1801 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
1802 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1803 
}
1804 
 
1805 
// 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1806 
8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1807 
"lsr"
1808 
*am33
1809 
{
1810 
  int dstreg;
1811 
  int z, n, c;
1812 
 
1813 
  PC = cia;
1814 
  dstreg = translate_rreg (SD_, RN0);
1815 
 
1816 
  c = State.regs[dstreg] & 1;
1817 
  State.regs[dstreg] >>= (IMM8 & 0xff);
1818 
  z = (State.regs[dstreg] == 0);
1819 
  n = (State.regs[dstreg] & 0x80000000) != 0;
1820 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
1821 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1822 
}
1823 
 
1824 
// 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1825 
8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1826 
"asl"
1827 
*am33
1828 
{
1829 
  int srcreg, dstreg;
1830 
  int z, n;
1831 
 
1832 
  PC = cia;
1833 
  dstreg = translate_rreg (SD_, RN0);
1834 
 
1835 
  State.regs[dstreg] <<= (IMM8 & 0xff);
1836 
  z = (State.regs[dstreg] == 0);
1837 
  n = (State.regs[dstreg] & 0x80000000) != 0;
1838 
  PSW &= ~(PSW_Z | PSW_N);
1839 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1840 
}
1841 
 
1842 
// 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1843 
8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1844 
"mul"
1845 
*am33
1846 
{
1847 
  int dstreg;
1848 
  unsigned long long temp;
1849 
  int z, n;
1850 
 
1851 
  PC = cia;
1852 
  dstreg = translate_rreg (SD_, RN0);
1853 
 
1854 
  temp = ((signed64)(signed32)State.regs[dstreg]
1855 
          *  (signed64)(signed32)EXTEND8 (IMM8));
1856 
  State.regs[dstreg] = temp & 0xffffffff;
1857 
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1858 
  z = (State.regs[dstreg] == 0);
1859 
  n = (State.regs[dstreg] & 0x80000000) != 0;
1860 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1861 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1862 
}
1863 
 
1864 
// 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1865 
8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1866 
"mulu"
1867 
*am33
1868 
{
1869 
  int dstreg;
1870 
  unsigned long long temp;
1871 
  int z, n;
1872 
 
1873 
  PC = cia;
1874 
  dstreg = translate_rreg (SD_, RN0);
1875 
 
1876 
  temp = ((unsigned64)State.regs[dstreg]
1877 
          * (unsigned64)(IMM8 & 0xff));
1878 
  State.regs[dstreg] = temp & 0xffffffff;
1879 
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1880 
  z = (State.regs[dstreg] == 0);
1881 
  n = (State.regs[dstreg] & 0x80000000) != 0;
1882 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1883 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1884 
}
1885 
 
1886 
// 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1887 
8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1888 
"btst"
1889 
*am33
1890 
{
1891 
  int srcreg;
1892 
 
1893 
  PC = cia;
1894 
  srcreg = translate_rreg (SD_, RM0);
1895 
  genericBtst(IMM8, State.regs[srcreg]);
1896 
}
1897 
 
1898 
// 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1899 
8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1900 
"mov"
1901 
*am33
1902 
{
1903 
  int srcreg, dstreg;
1904 
 
1905 
  PC = cia;
1906 
  srcreg = translate_rreg (SD_, RM0);
1907 
  dstreg = translate_rreg (SD_, RN2);
1908 
  State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1909 
}
1910 
 
1911 
// 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1912 
8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1913 
"mov"
1914 
*am33
1915 
{
1916 
  int srcreg, dstreg;
1917 
 
1918 
  PC = cia;
1919 
  srcreg = translate_rreg (SD_, RM2);
1920 
  dstreg = translate_rreg (SD_, RN0);
1921 
  store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1922 
}
1923 
 
1924 
// 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1925 
8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1926 
"movbu"
1927 
*am33
1928 
{
1929 
  int srcreg, dstreg;
1930 
 
1931 
  PC = cia;
1932 
  srcreg = translate_rreg (SD_, RM0);
1933 
  dstreg = translate_rreg (SD_, RN2);
1934 
  State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
1935 
}
1936 
 
1937 
// 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
1938 
8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
1939 
"movbu"
1940 
*am33
1941 
{
1942 
  int srcreg, dstreg;
1943 
 
1944 
  PC = cia;
1945 
  srcreg = translate_rreg (SD_, RM2);
1946 
  dstreg = translate_rreg (SD_, RN0);
1947 
  store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1948 
}
1949 
 
1950 
// 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
1951 
8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
1952 
"movhu"
1953 
*am33
1954 
{
1955 
  int srcreg, dstreg;
1956 
 
1957 
  PC = cia;
1958 
  srcreg = translate_rreg (SD_, RM0);
1959 
  dstreg = translate_rreg (SD_, RN2);
1960 
  State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
1961 
}
1962 
 
1963 
// 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
1964 
8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
1965 
"movhu"
1966 
*am33
1967 
{
1968 
  int srcreg, dstreg;
1969 
 
1970 
  PC = cia;
1971 
  srcreg = translate_rreg (SD_, RM2);
1972 
  dstreg = translate_rreg (SD_, RN0);
1973 
  store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1974 
}
1975 
 
1976 
// 1111 1011 0110 1010 Rn Rm IMM8; mov (d8,Rm+),Rn
1977 
8.0xfb+8.0x6a+4.RN2,4.RM0!RN2+8.IMM8:D2y:::mov
1978 
"mov"
1979 
*am33
1980 
{
1981 
  int srcreg, dstreg;
1982 
 
1983 
  PC = cia;
1984 
  srcreg = translate_rreg (SD_, RM0);
1985 
  dstreg = translate_rreg (SD_, RN2);
1986 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
1987 
  State.regs[srcreg] += EXTEND8 (IMM8);
1988 
}
1989 
 
1990 
// 1111 1011 0111 1010 Rn Rm IMM8; mov Rm,(d8,Rn+)
1991 
8.0xfb+8.0x7a+4.RM2,4.RN0+8.IMM8:D2z:::mov
1992 
"mov"
1993 
*am33
1994 
{
1995 
  int srcreg, dstreg;
1996 
 
1997 
  PC = cia;
1998 
  srcreg = translate_rreg (SD_, RM2);
1999 
  dstreg = translate_rreg (SD_, RN0);
2000 
  store_word (State.regs[dstreg], State.regs[srcreg]);
2001 
  State.regs[dstreg] += EXTEND8 (IMM8);
2002 
}
2003 
 
2004 
 
2005 
// 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2006 
8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2007 
"mov"
2008 
*am33
2009 
{
2010 
  int dstreg;
2011 
 
2012 
  PC = cia;
2013 
  dstreg = translate_rreg (SD_, RN2);
2014 
  State.regs[dstreg] = load_word (State.regs[REG_SP] + IMM8);
2015 
}
2016 
 
2017 
// 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2018 
8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2019 
"mov"
2020 
*am33
2021 
{
2022 
  int srcreg;
2023 
 
2024 
  PC = cia;
2025 
  srcreg = translate_rreg (SD_, RM2);
2026 
  store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2027 
}
2028 
 
2029 
// 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2030 
8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2031 
"movbu"
2032 
*am33
2033 
{
2034 
  int dstreg;
2035 
 
2036 
  PC = cia;
2037 
  dstreg = translate_rreg (SD_, RN2);
2038 
  State.regs[dstreg] = load_byte (State.regs[REG_SP] + IMM8);
2039 
}
2040 
 
2041 
// 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2042 
8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2043 
"movbu"
2044 
*am33
2045 
{
2046 
  int srcreg;
2047 
 
2048 
  PC = cia;
2049 
  srcreg = translate_rreg (SD_, RM2);
2050 
  store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2051 
}
2052 
 
2053 
// 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2054 
8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2055 
"movhu"
2056 
*am33
2057 
{
2058 
  int dstreg;
2059 
 
2060 
  PC = cia;
2061 
  dstreg = translate_rreg (SD_, RN2);
2062 
  State.regs[dstreg] = load_half (State.regs[REG_SP] + IMM8);
2063 
}
2064 
 
2065 
// 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2066 
8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2067 
"movhu"
2068 
*am33
2069 
{
2070 
  int srcreg;
2071 
 
2072 
  PC = cia;
2073 
  srcreg = translate_rreg (SD_, RM2);
2074 
  store_half (State.regs[REG_SP] + IMM8, State.regs[srcreg]);
2075 
}
2076 
 
2077 
// 1111 1011 1110 1010 Rn Rm IMM8; movhu (d8,Rm+),Rn
2078 
8.0xfb+8.0xea+4.RN2,4.RM0!RN2+8.IMM8:D2y:::movhu
2079 
"movhu"
2080 
*am33
2081 
{
2082 
  int srcreg, dstreg;
2083 
 
2084 
  PC = cia;
2085 
  srcreg = translate_rreg (SD_, RM0);
2086 
  dstreg = translate_rreg (SD_, RN2);
2087 
  State.regs[dstreg] = load_half (State.regs[srcreg]);
2088 
  State.regs[srcreg] += EXTEND8 (IMM8);
2089 
}
2090 
 
2091 
// 1111 1011 1111 1010 Rn Rm IMM8; movhu Rm,(d8,Rn+)
2092 
8.0xfb+8.0xfa+4.RM2,4.RN0+8.IMM8:D2z:::movhu
2093 
"movhu"
2094 
*am33
2095 
{
2096 
  int srcreg, dstreg;
2097 
 
2098 
  PC = cia;
2099 
  srcreg = translate_rreg (SD_, RM2);
2100 
  dstreg = translate_rreg (SD_, RN0);
2101 
  store_half (State.regs[dstreg], State.regs[srcreg]);
2102 
  State.regs[dstreg] += EXTEND8 (IMM8);
2103 
}
2104 
 
2105 
 
2106 
// 1111 1011 0000 1011 Rn Rn IMM8; mac imm8,Rn
2107 
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
2108 
"mac"
2109 
*am33
2110 
{
2111 
  int srcreg;
2112 
  long long temp, sum;
2113 
  int c, v;
2114 
 
2115 
  PC = cia;
2116 
  srcreg = translate_rreg (SD_, RN2);
2117 
 
2118 
  temp = ((signed64)(signed32)EXTEND8 (IMM8)
2119 
          * (signed64)(signed32)State.regs[srcreg]);
2120 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2121 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2122 
  State.regs[REG_MCRL] = sum;
2123 
  temp >>= 32;
2124 
  temp &= 0xffffffff;
2125 
  sum = State.regs[REG_MCRH] + temp + c;
2126 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2127 
        && (temp & 0x80000000) != (sum & 0x80000000));
2128 
  State.regs[REG_MCRH] = sum;
2129 
  if (v)
2130 
    State.regs[REG_MCVF] = 1;
2131 
}
2132 
 
2133 
// 1111 1011 0001 1011 Rn Rn IMM8; macu imm8,Rn
2134 
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
2135 
"macu"
2136 
*am33
2137 
{
2138 
  int srcreg;
2139 
  long long temp, sum;
2140 
  int c, v;
2141 
 
2142 
  PC = cia;
2143 
  srcreg = translate_rreg (SD_, RN2);
2144 
 
2145 
  temp = ((unsigned64) (IMM8)
2146 
          * (unsigned64)State.regs[srcreg]);
2147 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2148 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2149 
  State.regs[REG_MCRL] = sum;
2150 
  temp >>= 32;
2151 
  temp &= 0xffffffff;
2152 
  sum = State.regs[REG_MCRH] + temp + c;
2153 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2154 
        && (temp & 0x80000000) != (sum & 0x80000000));
2155 
  State.regs[REG_MCRH] = sum;
2156 
  if (v)
2157 
    State.regs[REG_MCVF] = 1;
2158 
}
2159 
 
2160 
// 1111 1011 0010 1011 Rn Rn IMM8; macb imm8,Rn
2161 
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
2162 
"macb"
2163 
*am33
2164 
{
2165 
  int srcreg;
2166 
  long long temp, sum;
2167 
  int c, v;
2168 
 
2169 
  PC = cia;
2170 
  srcreg = translate_rreg (SD_, RN2);
2171 
 
2172 
  temp = ((signed64)(signed8)EXTEND8 (IMM8)
2173 
          * (signed64)(signed8)State.regs[srcreg] & 0xff);
2174 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2175 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2176 
  State.regs[REG_MCRL] = sum;
2177 
  temp >>= 32;
2178 
  temp &= 0xffffffff;
2179 
  sum = State.regs[REG_MCRH] + temp + c;
2180 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2181 
        && (temp & 0x80000000) != (sum & 0x80000000));
2182 
  State.regs[REG_MCRH] = sum;
2183 
  if (v)
2184 
    State.regs[REG_MCVF] = 1;
2185 
}
2186 
 
2187 
// 1111 1011 0011 1011 Rn Rn IMM8; macbu imm8,Rn
2188 
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
2189 
"macbu"
2190 
*am33
2191 
{
2192 
  int srcreg;
2193 
  long long temp, sum;
2194 
  int c, v;
2195 
 
2196 
  PC = cia;
2197 
  srcreg = translate_rreg (SD_, RN2);
2198 
 
2199 
  temp = ((unsigned64) (IMM8)
2200 
          * (unsigned64)State.regs[srcreg] & 0xff);
2201 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2202 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2203 
  State.regs[REG_MCRL] = sum;
2204 
  temp >>= 32;
2205 
  temp &= 0xffffffff;
2206 
  sum = State.regs[REG_MCRH] + temp + c;
2207 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2208 
        && (temp & 0x80000000) != (sum & 0x80000000));
2209 
  State.regs[REG_MCRH] = sum;
2210 
  if (v)
2211 
    State.regs[REG_MCVF] = 1;
2212 
}
2213 
 
2214 
// 1111 1011 0100 1011 Rn Rn IMM8; mach imm8,Rn
2215 
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
2216 
"mach"
2217 
*am33
2218 
{
2219 
  int srcreg;
2220 
  long long temp, sum;
2221 
  int c, v;
2222 
 
2223 
  PC = cia;
2224 
  srcreg = translate_rreg (SD_, RN2);
2225 
 
2226 
  temp = ((signed64)(signed16)EXTEND8 (IMM8)
2227 
          * (signed64)(signed16)State.regs[srcreg] & 0xffff);
2228 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2229 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2230 
  State.regs[REG_MCRL] = sum;
2231 
  temp >>= 32;
2232 
  temp &= 0xffffffff;
2233 
  sum = State.regs[REG_MCRH] + temp + c;
2234 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2235 
        && (temp & 0x80000000) != (sum & 0x80000000));
2236 
  State.regs[REG_MCRH] = sum;
2237 
  if (v)
2238 
    State.regs[REG_MCVF] = 1;
2239 
}
2240 
 
2241 
// 1111 1011 0101 1011 Rn Rn IMM8; machu imm8,Rn
2242 
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
2243 
"machu"
2244 
*am33
2245 
{
2246 
  int srcreg;
2247 
  long long temp, sum;
2248 
  int c, v;
2249 
 
2250 
  PC = cia;
2251 
  srcreg = translate_rreg (SD_, RN2);
2252 
 
2253 
  temp = ((unsigned64) (IMM8)
2254 
          * (unsigned64)State.regs[srcreg] & 0xffff);
2255 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
2256 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
2257 
  State.regs[REG_MCRL] = sum;
2258 
  temp >>= 32;
2259 
  temp &= 0xffffffff;
2260 
  sum = State.regs[REG_MCRH] + temp + c;
2261 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
2262 
        && (temp & 0x80000000) != (sum & 0x80000000));
2263 
  State.regs[REG_MCRH] = sum;
2264 
  if (v)
2265 
    State.regs[REG_MCVF] = 1;
2266 
}
2267 
 
2268 
// 1111 1011 1011 1011 Rn Rn IMM8; mcste imm8,Rn
2269 
8.0xfb+8.0xbb+4.RN2,4.RN0=RN2+8.IMM8:D2:::mcste
2270 
"mcste"
2271 
*am33
2272 
{
2273 
  int dstreg;
2274 
 
2275 
  PC = cia;
2276 
  dstreg = translate_rreg (SD_, RN0);
2277 
 
2278 
  PSW &= ~(PSW_V | PSW_C);
2279 
  PSW |= (State.regs[REG_MCVF] ? PSW_V : 0);
2280 
 
2281 
  /* 32bit saturation.  */
2282 
  if (IMM8 == 0x20)
2283 
    {
2284 
      long long tmp;
2285 
 
2286 
      tmp = State.regs[REG_MCRH];
2287 
      tmp <<= 32;
2288 
      tmp += State.regs[REG_MCRL];
2289 
 
2290 
      if (tmp > 0x7fffffff)
2291 
        State.regs[dstreg] = 0x7fffffff;
2292 
      else if (tmp < 0xffffffff80000000LL)
2293 
        State.regs[dstreg] = 0x80000000;
2294 
      else
2295 
        State.regs[dstreg] = tmp;
2296 
    }
2297 
  /* 16bit saturation */
2298 
  else if (IMM8 == 0x10)
2299 
    {
2300 
      long long tmp;
2301 
 
2302 
      tmp = State.regs[REG_MCRH];
2303 
      tmp <<= 32;
2304 
      tmp += State.regs[REG_MCRL];
2305 
 
2306 
      if (tmp > 0x7fff)
2307 
        State.regs[dstreg] = 0x7fff;
2308 
      else if (tmp < 0xffffffffffff8000LL)
2309 
        State.regs[dstreg] = 0x8000;
2310 
      else
2311 
        State.regs[dstreg] = tmp;
2312 
    }
2313 
  /* 8 bit saturation */
2314 
  else if (IMM8 == 0x8)
2315 
    {
2316 
      long long tmp;
2317 
 
2318 
      tmp = State.regs[REG_MCRH];
2319 
      tmp <<= 32;
2320 
      tmp += State.regs[REG_MCRL];
2321 
 
2322 
      if (tmp > 0x7f)
2323 
        State.regs[dstreg] = 0x7f;
2324 
      else if (tmp < 0xffffffffffffff80LL)
2325 
        State.regs[dstreg] = 0x80;
2326 
      else
2327 
        State.regs[dstreg] = tmp;
2328 
    }
2329 
  /* 9 bit saturation */
2330 
  else if (IMM8 == 0x9)
2331 
    {
2332 
      long long tmp;
2333 
 
2334 
      tmp = State.regs[REG_MCRH];
2335 
      tmp <<= 32;
2336 
      tmp += State.regs[REG_MCRL];
2337 
 
2338 
      if (tmp > 0x80)
2339 
        State.regs[dstreg] = 0x80;
2340 
      else if (tmp < 0xffffffffffffff81LL)
2341 
        State.regs[dstreg] = 0x81;
2342 
      else
2343 
        State.regs[dstreg] = tmp;
2344 
    }
2345 
  /* 9 bit saturation */
2346 
  else if (IMM8 == 0x30)
2347 
    {
2348 
      long long tmp;
2349 
 
2350 
      tmp = State.regs[REG_MCRH];
2351 
      tmp <<= 32;
2352 
      tmp += State.regs[REG_MCRL];
2353 
 
2354 
      if (tmp > 0x7fffffffffffLL)
2355 
        tmp = 0x7fffffffffffLL;
2356 
      else if (tmp < 0xffff800000000000LL)
2357 
        tmp = 0xffff800000000000LL;
2358 
 
2359 
      tmp >>= 16;
2360 
      State.regs[dstreg] = tmp;
2361 
    }
2362 
}
2363 
 
2364 
// 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2365 
8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2366 
"add"
2367 
*am33
2368 
{
2369 
  int z, c, n, v;
2370 
  unsigned long sum, source1, source2;
2371 
  int srcreg1, srcreg2, dstreg;
2372 
 
2373 
  PC = cia;
2374 
  srcreg1 = translate_rreg (SD_, RM2);
2375 
  srcreg2 = translate_rreg (SD_, RN0);
2376 
  dstreg = translate_rreg (SD_, RD0);
2377 
 
2378 
  source1 = State.regs[srcreg1];
2379 
  source2 = State.regs[srcreg2];
2380 
  sum = source1 + source2;
2381 
  State.regs[dstreg] = sum;
2382 
 
2383 
  z = (sum == 0);
2384 
  n = (sum & 0x80000000);
2385 
  c = (sum < source1) || (sum < source2);
2386 
  v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2387 
       && (source1 & 0x80000000) != (sum & 0x80000000));
2388 
 
2389 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2390 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2391 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2392 
}
2393 
 
2394 
// 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2395 
8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2396 
"addc"
2397 
*am33
2398 
{
2399 
  int z, c, n, v;
2400 
  unsigned long sum, source1, source2;
2401 
  int srcreg1, srcreg2, dstreg;
2402 
 
2403 
  PC = cia;
2404 
  srcreg1 = translate_rreg (SD_, RM2);
2405 
  srcreg2 = translate_rreg (SD_, RN0);
2406 
  dstreg = translate_rreg (SD_, RD0);
2407 
 
2408 
  source1 = State.regs[srcreg1];
2409 
  source2 = State.regs[srcreg2];
2410 
  sum = source1 + source2 + ((PSW & PSW_C) != 0);
2411 
  State.regs[dstreg] = sum;
2412 
 
2413 
  z = ((PSW & PSW_Z) != 0) && (sum == 0);
2414 
  n = (sum & 0x80000000);
2415 
  c = (sum < source1) || (sum < source2);
2416 
  v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2417 
       && (source1 & 0x80000000) != (sum & 0x80000000));
2418 
 
2419 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2420 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2421 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2422 
}
2423 
 
2424 
// 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2425 
8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2426 
"sub"
2427 
*am33
2428 
{
2429 
  int z, c, n, v;
2430 
  unsigned long difference, source1, source2;
2431 
  int srcreg1, srcreg2, dstreg;
2432 
 
2433 
  PC = cia;
2434 
  srcreg1 = translate_rreg (SD_, RM2);
2435 
  srcreg2 = translate_rreg (SD_, RN0);
2436 
  dstreg = translate_rreg (SD_, RD0);
2437 
 
2438 
  source1 = State.regs[srcreg1];
2439 
  source2 = State.regs[srcreg2];
2440 
  difference = source2 - source1;
2441 
  State.regs[dstreg] = difference;
2442 
 
2443 
  z = (difference == 0);
2444 
  n = (difference & 0x80000000);
2445 
  c = (source1 > source1);
2446 
  v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2447 
       && (source1 & 0x80000000) != (difference & 0x80000000));
2448 
 
2449 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2450 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2451 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2452 
}
2453 
 
2454 
// 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2455 
8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2456 
"subc"
2457 
*am33
2458 
{
2459 
  int z, c, n, v;
2460 
  unsigned long difference, source1, source2;
2461 
  int srcreg1, srcreg2, dstreg;
2462 
 
2463 
  PC = cia;
2464 
  srcreg1 = translate_rreg (SD_, RM2);
2465 
  srcreg2 = translate_rreg (SD_, RN0);
2466 
  dstreg = translate_rreg (SD_, RD0);
2467 
 
2468 
  source1 = State.regs[srcreg1];
2469 
  source2 = State.regs[srcreg2];
2470 
  difference = source2 - source1 - ((PSW & PSW_C) != 0);
2471 
  State.regs[dstreg] = difference;
2472 
 
2473 
  z = ((PSW & PSW_Z) != 0) && (difference == 0);
2474 
  n = (difference & 0x80000000);
2475 
  c = (source1 > source2);
2476 
  v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2477 
       && (source1 & 0x80000000) != (difference & 0x80000000));
2478 
 
2479 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2480 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2481 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2482 
}
2483 
 
2484 
// 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2485 
8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2486 
"and"
2487 
*am33
2488 
{
2489 
  int z, n;
2490 
  int srcreg1, srcreg2, dstreg;
2491 
 
2492 
  PC = cia;
2493 
  srcreg1 = translate_rreg (SD_, RM2);
2494 
  srcreg2 = translate_rreg (SD_, RN0);
2495 
  dstreg = translate_rreg (SD_, RD0);
2496 
 
2497 
  State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2498 
 
2499 
  z = (State.regs[dstreg] == 0);
2500 
  n = (State.regs[dstreg] & 0x80000000);
2501 
 
2502 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2503 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2504 
}
2505 
 
2506 
// 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2507 
8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2508 
"or"
2509 
*am33
2510 
{
2511 
  int z, n;
2512 
  int srcreg1, srcreg2, dstreg;
2513 
 
2514 
  PC = cia;
2515 
  srcreg1 = translate_rreg (SD_, RM2);
2516 
  srcreg2 = translate_rreg (SD_, RN0);
2517 
  dstreg = translate_rreg (SD_, RD0);
2518 
 
2519 
  State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2520 
 
2521 
  z = (State.regs[dstreg] == 0);
2522 
  n = (State.regs[dstreg] & 0x80000000);
2523 
 
2524 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2525 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2526 
}
2527 
 
2528 
// 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2529 
8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2530 
"xor"
2531 
*am33
2532 
{
2533 
  int z, n;
2534 
  int srcreg1, srcreg2, dstreg;
2535 
 
2536 
  PC = cia;
2537 
  srcreg1 = translate_rreg (SD_, RM2);
2538 
  srcreg2 = translate_rreg (SD_, RN0);
2539 
  dstreg = translate_rreg (SD_, RD0);
2540 
 
2541 
  State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2542 
 
2543 
  z = (State.regs[dstreg] == 0);
2544 
  n = (State.regs[dstreg] & 0x80000000);
2545 
 
2546 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2547 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2548 
}
2549 
 
2550 
// 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2551 
8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2552 
"asr"
2553 
*am33
2554 
{
2555 
  int z, c, n;
2556 
  long temp;
2557 
  int srcreg1, srcreg2, dstreg;
2558 
 
2559 
  PC = cia;
2560 
  srcreg1 = translate_rreg (SD_, RM2);
2561 
  srcreg2 = translate_rreg (SD_, RN0);
2562 
  dstreg = translate_rreg (SD_, RD0);
2563 
 
2564 
  temp = State.regs[srcreg2];
2565 
  c = temp & 1;
2566 
  temp >>= State.regs[srcreg1];
2567 
  State.regs[dstreg] = temp;
2568 
 
2569 
  z = (State.regs[dstreg] == 0);
2570 
  n = (State.regs[dstreg] & 0x80000000);
2571 
 
2572 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
2573 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2574 
}
2575 
 
2576 
// 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2577 
8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2578 
"lsr"
2579 
*am33
2580 
{
2581 
  int z, c, n;
2582 
  int srcreg1, srcreg2, dstreg;
2583 
 
2584 
  PC = cia;
2585 
  srcreg1 = translate_rreg (SD_, RM2);
2586 
  srcreg2 = translate_rreg (SD_, RN0);
2587 
  dstreg = translate_rreg (SD_, RD0);
2588 
 
2589 
  c = State.regs[srcreg2] & 1;
2590 
  State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2591 
 
2592 
  z = (State.regs[dstreg] == 0);
2593 
  n = (State.regs[dstreg] & 0x80000000);
2594 
 
2595 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
2596 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2597 
}
2598 
 
2599 
// 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2600 
8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2601 
"asl"
2602 
*am33
2603 
{
2604 
  int z, n;
2605 
  int srcreg1, srcreg2, dstreg;
2606 
 
2607 
  PC = cia;
2608 
  srcreg1 = translate_rreg (SD_, RM2);
2609 
  srcreg2 = translate_rreg (SD_, RN0);
2610 
  dstreg = translate_rreg (SD_, RD0);
2611 
 
2612 
  State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];
2613 
 
2614 
  z = (State.regs[dstreg] == 0);
2615 
  n = (State.regs[dstreg] & 0x80000000);
2616 
 
2617 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
2618 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2619 
}
2620 
 
2621 
// 1111 1011 1010 1101 Rm Rn Rd1 Rd2; mul Rm,Rn,Rd1,Rd2
2622 
8.0xfb+8.0xad+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mul
2623 
"mul"
2624 
*am33
2625 
{
2626 
  int srcreg1, srcreg2, dstreg1, dstreg2;
2627 
  signed long long temp;
2628 
  int n, z;
2629 
 
2630 
  PC = cia;
2631 
  srcreg1 = translate_rreg (SD_, RM2);
2632 
  srcreg2 = translate_rreg (SD_, RN0);
2633 
  dstreg1 = translate_rreg (SD_, RD0);
2634 
  dstreg2 = translate_rreg (SD_, RD2);
2635 
 
2636 
  temp = ((signed64)(signed32)State.regs[srcreg1]
2637 
          *  (signed64)(signed32)State.regs[srcreg2]);
2638 
  State.regs[dstreg2] = temp & 0xffffffff;
2639 
  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2640 
 
2641 
  z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2642 
  n = (State.regs[dstreg1] & 0x80000000);
2643 
 
2644 
  PSW &= ~(PSW_Z | PSW_N);
2645 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2646 
}
2647 
 
2648 
// 1111 1011 1011 1101 Rm Rn Rd1 Rd2; mulu Rm,Rn,Rd1,Rd2
2649 
8.0xfb+8.0xbd+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mulu
2650 
"mulu"
2651 
*am33
2652 
{
2653 
  int srcreg1, srcreg2, dstreg1, dstreg2;
2654 
  signed long long temp;
2655 
  int n, z;
2656 
 
2657 
  PC = cia;
2658 
  srcreg1 = translate_rreg (SD_, RM2);
2659 
  srcreg2 = translate_rreg (SD_, RN0);
2660 
  dstreg1 = translate_rreg (SD_, RD0);
2661 
  dstreg2 = translate_rreg (SD_, RD2);
2662 
 
2663 
  temp = ((unsigned64)State.regs[srcreg1]
2664 
          *  (unsigned64)State.regs[srcreg2]);
2665 
  State.regs[dstreg2] = temp & 0xffffffff;
2666 
  State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
2667 
 
2668 
  z = (State.regs[dstreg1] == 0) && (State.regs[dstreg2] == 0);
2669 
  n = (State.regs[dstreg1] & 0x80000000);
2670 
 
2671 
  PSW &= ~(PSW_Z | PSW_N);
2672 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2673 
}
2674 
 
2675 
// 1111 1011 0000 1110 Rn 0000 abs8 ; mov (abs8),Rn
2676 
8.0xfb+8.0x0e+4.RN2,4.0x0+8.IMM8:D2p:::mov
2677 
"mov"
2678 
*am33
2679 
{
2680 
  int dstreg;
2681 
 
2682 
  PC = cia;
2683 
  dstreg = translate_rreg (SD_, RN2);
2684 
  State.regs[dstreg] = load_word (IMM8);
2685 
}
2686 
 
2687 
// 1111 1011 0001 1110 Rm 0000 abs8 ; mov Rn,(abs8)
2688 
8.0xfb+8.0x1e+4.RM2,4.0x0+8.IMM8:D2q:::mov
2689 
"mov"
2690 
*am33
2691 
{
2692 
  int srcreg;
2693 
 
2694 
  PC = cia;
2695 
  srcreg = translate_rreg (SD_, RM2);
2696 
  store_word (IMM8, State.regs[srcreg]);
2697 
}
2698 
 
2699 
// 1111 1011 0010 1110 Rn 0000 abs8 ; movbu (abs8),Rn
2700 
8.0xfb+8.0x2e+4.RN2,4.0x0+8.IMM8:D2p:::movbu
2701 
"movbu"
2702 
*am33
2703 
{
2704 
  int dstreg;
2705 
 
2706 
  PC = cia;
2707 
  dstreg = translate_rreg (SD_, RN2);
2708 
  State.regs[dstreg] = load_byte (IMM8);
2709 
}
2710 
 
2711 
// 1111 1011 0011 1110 Rm 0000 abs8 ; movbu Rn,(abs8)
2712 
8.0xfb+8.0x3e+4.RM2,4.0x0+8.IMM8:D2q:::movbu
2713 
"movbu"
2714 
*am33
2715 
{
2716 
  int srcreg;
2717 
 
2718 
  PC = cia;
2719 
  srcreg = translate_rreg (SD_, RM2);
2720 
  store_byte (IMM8, State.regs[srcreg]);
2721 
}
2722 
 
2723 
// 1111 1011 0100 1110 Rn 0000 abs8 ; movhu (abs8),Rn
2724 
8.0xfb+8.0x4e+4.RN2,4.0x0+8.IMM8:D2p:::movhu
2725 
"movhu"
2726 
*am33
2727 
{
2728 
  int dstreg;
2729 
 
2730 
  PC = cia;
2731 
  dstreg = translate_rreg (SD_, RN2);
2732 
  State.regs[dstreg] = load_half (IMM8);
2733 
}
2734 
 
2735 
// 1111 1011 0101 1110 Rm 0000 abs8 ; movhu Rn,(abs8)
2736 
8.0xfb+8.0x5e+4.RM2,4.0x0+8.IMM8:D2q:::movhu
2737 
"movhu"
2738 
*am33
2739 
{
2740 
  int srcreg;
2741 
 
2742 
  PC = cia;
2743 
  srcreg = translate_rreg (SD_, RM2);
2744 
  store_half (IMM8, State.regs[srcreg]);
2745 
}
2746 
 
2747 
// 1111 1011 1000 1110 Ri Rm Rn; mov (Ri,Rm),Rn
2748 
8.0xfb+8.0x8e+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::mov
2749 
"mov"
2750 
*am33
2751 
{
2752 
  int srcreg1, srcreg2, dstreg;
2753 
 
2754 
  PC = cia;
2755 
  srcreg1 = translate_rreg (SD_, RM0);
2756 
  srcreg1 = translate_rreg (SD_, RI0);
2757 
  dstreg = translate_rreg (SD_, RN0);
2758 
  State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
2759 
}
2760 
 
2761 
// 1111 1011 1001 1110 Ri Rm Rn; mov Rn,(Ri,Rm)
2762 
8.0xfb+8.0x9e+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::mov
2763 
"mov"
2764 
*am33
2765 
{
2766 
  int srcreg, dstreg1, dstreg2;
2767 
 
2768 
  PC = cia;
2769 
  srcreg = translate_rreg (SD_, RM0);
2770 
  dstreg1 = translate_rreg (SD_, RI0);
2771 
  dstreg2 = translate_rreg (SD_, RN0);
2772 
  store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2773 
}
2774 
 
2775 
// 1111 1011 1010 1110 Ri Rm Rn; movbu (Ri,Rm),Rn
2776 
8.0xfb+8.0xae+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movbu
2777 
"movbu"
2778 
*am33
2779 
{
2780 
  int srcreg1, srcreg2, dstreg;
2781 
 
2782 
  PC = cia;
2783 
  srcreg1 = translate_rreg (SD_, RM0);
2784 
  srcreg1 = translate_rreg (SD_, RI0);
2785 
  dstreg = translate_rreg (SD_, RN0);
2786 
  State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
2787 
}
2788 
 
2789 
// 1111 1011 1011 1110 Ri Rm Rn; movbu Rn,(Ri,Rm)
2790 
8.0xfb+8.0xbe+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movbu
2791 
"movbu"
2792 
*am33
2793 
{
2794 
  int srcreg, dstreg1, dstreg2;
2795 
 
2796 
  PC = cia;
2797 
  srcreg = translate_rreg (SD_, RM0);
2798 
  dstreg1 = translate_rreg (SD_, RI0);
2799 
  dstreg2 = translate_rreg (SD_, RN0);
2800 
  store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2801 
}
2802 
 
2803 
// 1111 1011 1100 1110 Ri Rm Rn; movhu (Ri,Rm),Rn
2804 
8.0xfb+8.0xce+4.RI0,4.RM0+4.RN0,4.0x0:D2r:::movhu
2805 
"movhu"
2806 
*am33
2807 
{
2808 
  int srcreg1, srcreg2, dstreg;
2809 
 
2810 
  PC = cia;
2811 
  srcreg1 = translate_rreg (SD_, RM0);
2812 
  srcreg1 = translate_rreg (SD_, RI0);
2813 
  dstreg = translate_rreg (SD_, RN0);
2814 
  State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
2815 
}
2816 
 
2817 
// 1111 1011 1101 1110 Ri Rm Rn; movhu Rn,(Ri,Rm)
2818 
8.0xfb+8.0xde+4.RI0,4.RN0+4.RM0,4.0x0:D2s:::movhu
2819 
"movhu"
2820 
*am33
2821 
{
2822 
  int srcreg, dstreg1, dstreg2;
2823 
 
2824 
  PC = cia;
2825 
  srcreg = translate_rreg (SD_, RM0);
2826 
  dstreg1 = translate_rreg (SD_, RI0);
2827 
  dstreg2 = translate_rreg (SD_, RN0);
2828 
  store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
2829 
}
2830 
 
2831 
// 1111 1011 0000 1111 Rm Rn Rd1 Rd2; mac Rm,Rn,Rd1,Rd2
2832 
8.0xfb+8.0x0f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mac
2833 
"mac"
2834 
*am33
2835 
{
2836 
  int srcreg1, srcreg2, dstreg1, dstreg2;
2837 
  signed long long temp;
2838 
  unsigned long sum;
2839 
  int c, v;
2840 
 
2841 
  PC = cia;
2842 
  srcreg1 = translate_rreg (SD_, RM2);
2843 
  srcreg2 = translate_rreg (SD_, RN0);
2844 
  dstreg1 = translate_rreg (SD_, RD0);
2845 
  dstreg2 = translate_rreg (SD_, RD2);
2846 
 
2847 
  temp = ((signed64)(signed32)State.regs[srcreg1]
2848 
          *  (signed64)(signed32)State.regs[srcreg2]);
2849 
 
2850 
  sum = State.regs[dstreg2] + (temp & 0xffffffff);
2851 
  c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2852 
  State.regs[dstreg2] = sum;
2853 
  temp >>= 32;
2854 
  temp &= 0xffffffff;
2855 
  sum = State.regs[dstreg1] + temp + c;
2856 
  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2857 
        && (temp & 0x80000000) != (sum & 0x80000000));
2858 
  State.regs[dstreg1] = sum;
2859 
  if (v)
2860 
    {
2861 
      State.regs[REG_MCVF] = 1;
2862 
      PSW &= ~(PSW_V);
2863 
      PSW |= (( v ? PSW_V : 0));
2864 
    }
2865 
}
2866 
 
2867 
// 1111 1011 0001 1111 Rm Rn Rd1 Rd2; macu Rm,Rn,Rd1,Rd2
2868 
8.0xfb+8.0x1f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::macu
2869 
"macu"
2870 
*am33
2871 
{
2872 
  int srcreg1, srcreg2, dstreg1, dstreg2;
2873 
  signed long long temp;
2874 
  unsigned long sum;
2875 
  int c, v;
2876 
 
2877 
  PC = cia;
2878 
  srcreg1 = translate_rreg (SD_, RM2);
2879 
  srcreg2 = translate_rreg (SD_, RN0);
2880 
  dstreg1 = translate_rreg (SD_, RD0);
2881 
  dstreg2 = translate_rreg (SD_, RD2);
2882 
 
2883 
  temp = ((unsigned64)State.regs[srcreg1]
2884 
          * (unsigned64)State.regs[srcreg2]);
2885 
 
2886 
  sum = State.regs[dstreg2] + (temp & 0xffffffff);
2887 
  c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
2888 
  State.regs[dstreg2] = sum;
2889 
  temp >>= 32;
2890 
  temp &= 0xffffffff;
2891 
  sum = State.regs[dstreg1] + temp + c;
2892 
  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2893 
        && (temp & 0x80000000) != (sum & 0x80000000));
2894 
  State.regs[dstreg1] = sum;
2895 
  if (v)
2896 
    {
2897 
      State.regs[REG_MCVF] = 1;
2898 
      PSW &= ~(PSW_V);
2899 
      PSW |= (( v ? PSW_V : 0));
2900 
    }
2901 
}
2902 
 
2903 
// 1111 1011 0010 1111 Rm Rn Rd1; macb Rm,Rn,Rd1
2904 
8.0xfb+8.0x2f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macb
2905 
"macb"
2906 
*am33
2907 
{
2908 
  int srcreg1, srcreg2, dstreg;
2909 
  long temp, sum;
2910 
  int v;
2911 
 
2912 
  PC = cia;
2913 
  srcreg1 = translate_rreg (SD_, RM2);
2914 
  srcreg2 = translate_rreg (SD_, RN0);
2915 
  dstreg = translate_rreg (SD_, RD0);
2916 
 
2917 
  temp = ((signed32)(State.regs[srcreg2] & 0xff)
2918 
          * (signed32)(State.regs[srcreg1] & 0xff));
2919 
  sum = State.regs[dstreg] + temp;
2920 
  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2921 
        && (temp & 0x80000000) != (sum & 0x80000000));
2922 
  State.regs[dstreg] = sum;
2923 
  if (v)
2924 
    {
2925 
      State.regs[REG_MCVF] = 1;
2926 
      PSW &= ~(PSW_V);
2927 
      PSW |= ((v ? PSW_V : 0));
2928 
    }
2929 
}
2930 
 
2931 
// 1111 1011 0011 1111 Rm Rn Rd1; macbu Rm,Rn,Rd1
2932 
8.0xfb+8.0x3f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::macbu
2933 
"macbu"
2934 
*am33
2935 
{
2936 
  int srcreg1, srcreg2, dstreg;
2937 
  long temp, sum;
2938 
  int v;
2939 
 
2940 
  PC = cia;
2941 
  srcreg1 = translate_rreg (SD_, RM2);
2942 
  srcreg2 = translate_rreg (SD_, RN0);
2943 
  dstreg = translate_rreg (SD_, RD0);
2944 
 
2945 
  temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
2946 
          * (unsigned32)(State.regs[srcreg1] & 0xff));
2947 
  sum = State.regs[dstreg] + temp;
2948 
  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
2949 
        && (temp & 0x80000000) != (sum & 0x80000000));
2950 
  State.regs[dstreg] = sum;
2951 
  if (v)
2952 
    {
2953 
      State.regs[REG_MCVF] = 1;
2954 
      PSW &= ~(PSW_V);
2955 
      PSW |= ((v ? PSW_V : 0));
2956 
    }
2957 
}
2958 
 
2959 
// 1111 1011 0100 1111 Rm Rn Rd1; mach Rm,Rn,Rd1,Rd2
2960 
8.0xfb+8.0x4f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::mach
2961 
"mach"
2962 
*am33
2963 
{
2964 
  int srcreg1, srcreg2, dstreg1, dstreg2;
2965 
  long long temp, sum;
2966 
  int v;
2967 
 
2968 
  PC = cia;
2969 
  srcreg1 = translate_rreg (SD_, RM2);
2970 
  srcreg2 = translate_rreg (SD_, RN0);
2971 
  dstreg1 = translate_rreg (SD_, RD0);
2972 
  dstreg2 = translate_rreg (SD_, RD0);
2973 
 
2974 
  temp = ((signed32)(State.regs[srcreg2] & 0xffff)
2975 
          * (signed32)(State.regs[srcreg1] & 0xffff));
2976 
  State.regs[dstreg2] += (temp & 0xffffffff);
2977 
  sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
2978 
  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
2979 
        && (temp & 0x80000000) != (sum & 0x80000000));
2980 
  State.regs[dstreg1] = sum;
2981 
  if (v)
2982 
    {
2983 
      State.regs[REG_MCVF] = 1;
2984 
      PSW &= ~(PSW_V);
2985 
      PSW |= ((v ? PSW_V : 0));
2986 
    }
2987 
}
2988 
 
2989 
// 1111 1011 0101 1111 Rm Rn Rd1; machu Rm,Rn,Rd1,Rd2
2990 
8.0xfb+8.0x5f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::machu
2991 
"machu"
2992 
*am33
2993 
{
2994 
  int srcreg1, srcreg2, dstreg1, dstreg2;
2995 
  long long temp, sum;
2996 
  int v;
2997 
 
2998 
  PC = cia;
2999 
  srcreg1 = translate_rreg (SD_, RM2);
3000 
  srcreg2 = translate_rreg (SD_, RN0);
3001 
  dstreg1 = translate_rreg (SD_, RD0);
3002 
  dstreg2 = translate_rreg (SD_, RD0);
3003 
 
3004 
  temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3005 
          * (unsigned32)(State.regs[srcreg1] & 0xffff));
3006 
  State.regs[dstreg2] += (temp & 0xffffffff);
3007 
  sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
3008 
  v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
3009 
        && (temp & 0x80000000) != (sum & 0x80000000));
3010 
  State.regs[dstreg1] = sum;
3011 
  if (v)
3012 
    {
3013 
      State.regs[REG_MCVF] = 1;
3014 
      PSW &= ~(PSW_V);
3015 
      PSW |= ((v ? PSW_V : 0));
3016 
    }
3017 
}
3018 
 
3019 
// 1111 1011 0110 1111 Rm Rn Rd1; dmach Rm,Rn,Rd1
3020 
8.0xfb+8.0x6f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmach
3021 
"dmach"
3022 
*am33
3023 
{
3024 
  int srcreg1, srcreg2, dstreg;
3025 
  long temp, temp2, sum;
3026 
  int v;
3027 
 
3028 
  PC = cia;
3029 
  srcreg1 = translate_rreg (SD_, RM2);
3030 
  srcreg2 = translate_rreg (SD_, RN0);
3031 
  dstreg = translate_rreg (SD_, RD0);
3032 
 
3033 
  temp = ((signed32)(State.regs[srcreg2] & 0xffff)
3034 
          * (signed32)(State.regs[srcreg1] & 0xffff));
3035 
  temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3036 
           * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
3037 
  sum = temp + temp2 + State.regs[dstreg];
3038 
  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3039 
        && (temp & 0x80000000) != (sum & 0x80000000));
3040 
  State.regs[dstreg] = sum;
3041 
  if (v)
3042 
    {
3043 
      State.regs[REG_MCVF] = 1;
3044 
      PSW &= ~(PSW_V);
3045 
      PSW |= ((v ? PSW_V : 0));
3046 
    }
3047 
}
3048 
 
3049 
// 1111 1011 0111 1111 Rm Rn Rd1; dmachu Rm,Rn,Rd1
3050 
8.0xfb+8.0x7f+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::dmachu
3051 
"dmachu"
3052 
*am33
3053 
{
3054 
  int srcreg1, srcreg2, dstreg;
3055 
  long temp, temp2, sum;
3056 
  int v;
3057 
 
3058 
  PC = cia;
3059 
  srcreg1 = translate_rreg (SD_, RM2);
3060 
  srcreg2 = translate_rreg (SD_, RN0);
3061 
  dstreg = translate_rreg (SD_, RD0);
3062 
 
3063 
  temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
3064 
          * (unsigned32)(State.regs[srcreg1] & 0xffff));
3065 
  temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3066 
           * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
3067 
  sum = temp + temp2 + State.regs[dstreg];
3068 
  v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
3069 
        && (temp & 0x80000000) != (sum & 0x80000000));
3070 
  State.regs[dstreg] = sum;
3071 
  if (v)
3072 
    {
3073 
      State.regs[REG_MCVF] = 1;
3074 
      PSW &= ~(PSW_V);
3075 
      PSW |= ((v ? PSW_V : 0));
3076 
    }
3077 
}
3078 
 
3079 
// 1111 1011 1000 1111 Rm Rn Rd1 Rd2; dmulh Rm,Rn,Rd1,Rd2
3080 
8.0xfb+8.0x8f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulh
3081 
"dmulh"
3082 
*am33
3083 
{
3084 
  int srcreg1, srcreg2, dstreg1, dstreg2;
3085 
  signed long long temp;
3086 
 
3087 
  PC = cia;
3088 
  srcreg1 = translate_rreg (SD_, RM2);
3089 
  srcreg2 = translate_rreg (SD_, RN0);
3090 
  dstreg1 = translate_rreg (SD_, RD0);
3091 
  dstreg2 = translate_rreg (SD_, RD2);
3092 
 
3093 
  temp = ((signed32)(State.regs[srcreg1] & 0xffff)
3094 
          * (signed32)(State.regs[srcreg1] & 0xffff));
3095 
  State.regs[dstreg2] = temp;
3096 
  temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
3097 
          * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
3098 
  State.regs[dstreg1] = temp;
3099 
}
3100 
 
3101 
// 1111 1011 1001 1111 Rm Rn Rd1 Rd2; dmulhu Rm,Rn,Rd1,Rd2
3102 
8.0xfb+8.0x9f+4.RM2,4.RN0+4.RD0,4.RD2!RD0:D2c:::dmulhu
3103 
"dmulhu"
3104 
*am33
3105 
{
3106 
  int srcreg1, srcreg2, dstreg1, dstreg2;
3107 
  signed long long temp;
3108 
 
3109 
  PC = cia;
3110 
  srcreg1 = translate_rreg (SD_, RM2);
3111 
  srcreg2 = translate_rreg (SD_, RN0);
3112 
  dstreg1 = translate_rreg (SD_, RD0);
3113 
  dstreg2 = translate_rreg (SD_, RD2);
3114 
 
3115 
  temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
3116 
          * (unsigned32)(State.regs[srcreg1] & 0xffff));
3117 
  State.regs[dstreg2] = temp;
3118 
  temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
3119 
          * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
3120 
  State.regs[dstreg1] = temp;
3121 
}
3122 
 
3123 
// 1111 1011 1010 1111 Rm Rn; sat24 Rm,Rn
3124 
8.0xfb+8.0xaf+4.RM2,4.RN0+8.0x0:D2:::sat24
3125 
"sat24"
3126 
*am33
3127 
{
3128 
  int srcreg, dstreg;
3129 
  int value, n, z;
3130 
 
3131 
  PC = cia;
3132 
  srcreg = translate_rreg (SD_, RM2);
3133 
  dstreg = translate_rreg (SD_, RN0);
3134 
 
3135 
  value = State.regs[srcreg];
3136 
 
3137 
  if (value >= 0x7fffff)
3138 
    State.regs[dstreg] = 0x7fffff;
3139 
  else if (value <= 0xff800000)
3140 
    State.regs[dstreg] = 0xff800000;
3141 
  else
3142 
    State.regs[dstreg] = value;
3143 
 
3144 
  n = (State.regs[dstreg] & 0x800000) != 0;
3145 
  z = (State.regs[dstreg] == 0);
3146 
  PSW &= ~(PSW_Z | PSW_N);
3147 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3148 
}
3149 
 
3150 
// 1111 1011 1111 1111 Rm Rn Rd1; bsch Rm,Rn,Rd1
3151 
8.0xfb+8.0xff+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::bsch
3152 
"bsch"
3153 
*am33
3154 
{
3155 
  int temp, c, i;
3156 
  int srcreg1, srcreg2, dstreg;
3157 
  int start;
3158 
 
3159 
  PC = cia;
3160 
  srcreg1 = translate_rreg (SD_, RM2);
3161 
  srcreg2 = translate_rreg (SD_, RN0);
3162 
  dstreg = translate_rreg (SD_, RD0);
3163 
 
3164 
  temp = State.regs[srcreg1];
3165 
  start = (State.regs[srcreg2] & 0x1f) - 1;
3166 
  if (start == -1)
3167 
    start = 31;
3168 
 
3169 
  for (i = start; i >= 0; i--)
3170 
    {
3171 
      if (temp & (1 << i))
3172 
        {
3173 
          c = 1;
3174 
          State.regs[dstreg] = i;
3175 
          break;
3176 
        }
3177 
    }
3178 
 
3179 
  if (i < 0)
3180 
    {
3181 
      c = 0;
3182 
      State.regs[dstreg] = 0;
3183 
    }
3184 
  PSW &= ~(PSW_C);
3185 
  PSW |= (c ? PSW_C : 0);
3186 
}
3187 
 
3188 
// 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
3189 
8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
3190 
"mov"
3191 
*am33
3192 
{
3193 
  int dstreg;
3194 
 
3195 
  PC = cia;
3196 
  dstreg = translate_rreg (SD_, RN0);
3197 
  State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3198 
}
3199 
 
3200 
// 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
3201 
8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
3202 
"movu"
3203 
*am33
3204 
{
3205 
  int dstreg;
3206 
 
3207 
  PC = cia;
3208 
  dstreg = translate_rreg (SD_, RN0);
3209 
  State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3210 
}
3211 
 
3212 
// 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
3213 
8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
3214 
"add"
3215 
*am33
3216 
{
3217 
  int dstreg;
3218 
 
3219 
  PC = cia;
3220 
  dstreg = translate_rreg (SD_, RN0);
3221 
  genericAdd (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3222 
}
3223 
 
3224 
// 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
3225 
8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
3226 
"addc"
3227 
*am33
3228 
{
3229 
  int dstreg, z, n, c, v;
3230 
  unsigned long sum, imm, reg2;
3231 
 
3232 
  PC = cia;
3233 
  dstreg = translate_rreg (SD_, RN0);
3234 
 
3235 
  imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3236 
  reg2 = State.regs[dstreg];
3237 
  sum = imm + reg2 + ((PSW & PSW_C) != 0);
3238 
  State.regs[dstreg] = sum;
3239 
 
3240 
  z = ((PSW & PSW_Z) != 0) && (sum == 0);
3241 
  n = (sum & 0x80000000);
3242 
  c = (sum < imm) || (sum < reg2);
3243 
  v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3244 
       && (reg2 & 0x80000000) != (sum & 0x80000000));
3245 
 
3246 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3247 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3248 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3249 
}
3250 
 
3251 
// 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
3252 
8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
3253 
"sub"
3254 
*am33
3255 
{
3256 
  int dstreg;
3257 
 
3258 
  PC = cia;
3259 
  dstreg = translate_rreg (SD_, RN0);
3260 
  genericSub (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), dstreg);
3261 
}
3262 
 
3263 
// 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
3264 
8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
3265 
"subc"
3266 
*am33
3267 
{
3268 
  int dstreg, z, n, c, v;
3269 
  unsigned long difference, imm, reg2;
3270 
 
3271 
  PC = cia;
3272 
  dstreg = translate_rreg (SD_, RN0);
3273 
 
3274 
  imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3275 
  reg2 = State.regs[dstreg];
3276 
  difference = reg2 - imm - ((PSW & PSW_C) != 0);
3277 
  State.regs[dstreg] = difference;
3278 
 
3279 
  z = ((PSW & PSW_Z) != 0) && (difference == 0);
3280 
  n = (difference & 0x80000000);
3281 
  c = (imm > reg2);
3282 
  v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3283 
       && (reg2 & 0x80000000) != (difference & 0x80000000));
3284 
 
3285 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3286 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3287 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3288 
}
3289 
 
3290 
// 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
3291 
8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
3292 
"cmp"
3293 
*am33
3294 
{
3295 
  int srcreg;
3296 
 
3297 
  PC = cia;
3298 
  srcreg = translate_rreg (SD_, RN0);
3299 
  genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
3300 
}
3301 
 
3302 
// 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
3303 
8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
3304 
"mov"
3305 
*am33
3306 
{
3307 
  int dstreg;
3308 
 
3309 
  PC = cia;
3310 
  dstreg = translate_xreg (SD_, XRN0);
3311 
 
3312 
  State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
3313 
}
3314 
 
3315 
// 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3316 
8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
3317 
"and"
3318 
*am33
3319 
{
3320 
  int dstreg;
3321 
  int z,n;
3322 
 
3323 
  PC = cia;
3324 
  dstreg = translate_rreg (SD_, RN0);
3325 
 
3326 
  State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3327 
  z = (State.regs[dstreg] == 0);
3328 
  n = (State.regs[dstreg] & 0x80000000) != 0;
3329 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3330 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3331 
}
3332 
 
3333 
// 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3334 
8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
3335 
"or"
3336 
*am33
3337 
{
3338 
  int dstreg;
3339 
  int z,n;
3340 
 
3341 
  PC = cia;
3342 
  dstreg = translate_rreg (SD_, RN0);
3343 
 
3344 
  State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3345 
  z = (State.regs[dstreg] == 0);
3346 
  n = (State.regs[dstreg] & 0x80000000) != 0;
3347 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3348 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3349 
}
3350 
 
3351 
// 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3352 
8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
3353 
"xor"
3354 
*am33
3355 
{
3356 
  int dstreg;
3357 
  int z,n;
3358 
 
3359 
  PC = cia;
3360 
  dstreg = translate_rreg (SD_, RN0);
3361 
 
3362 
  State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
3363 
  z = (State.regs[dstreg] == 0);
3364 
  n = (State.regs[dstreg] & 0x80000000) != 0;
3365 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3366 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3367 
}
3368 
 
3369 
// 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3370 
8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
3371 
"asr"
3372 
*am33
3373 
{
3374 
  int dstreg;
3375 
  long temp;
3376 
  int c, z, n;
3377 
 
3378 
  PC = cia;
3379 
  dstreg = translate_rreg (SD_, RN0);
3380 
 
3381 
  temp = State.regs[dstreg];
3382 
  c = temp & 1;
3383 
  temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3384 
  State.regs[dstreg] = temp;
3385 
  z = (State.regs[dstreg] == 0);
3386 
  n = (State.regs[dstreg] & 0x80000000) != 0;
3387 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
3388 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3389 
}
3390 
 
3391 
 
3392 
// 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3393 
8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
3394 
"lsr"
3395 
*am33
3396 
{
3397 
  int dstreg;
3398 
  int z, n, c;
3399 
 
3400 
  PC = cia;
3401 
  dstreg = translate_rreg (SD_, RN0);
3402 
 
3403 
  c = State.regs[dstreg] & 1;
3404 
  State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
3405 
  z = (State.regs[dstreg] == 0);
3406 
  n = (State.regs[dstreg] & 0x80000000) != 0;
3407 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
3408 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3409 
}
3410 
 
3411 
// 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3412 
8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
3413 
"asl"
3414 
*am33
3415 
{
3416 
  int srcreg, dstreg;
3417 
  int z, n;
3418 
 
3419 
  PC = cia;
3420 
  dstreg = translate_rreg (SD_, RN0);
3421 
 
3422 
  State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
3423 
  z = (State.regs[dstreg] == 0);
3424 
  n = (State.regs[dstreg] & 0x80000000) != 0;
3425 
  PSW &= ~(PSW_Z | PSW_N);
3426 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3427 
}
3428 
 
3429 
// 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3430 
8.0xfd+8.0xa9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mul
3431 
"mul"
3432 
*am33
3433 
{
3434 
  int dstreg;
3435 
  unsigned long long temp;
3436 
  int z, n;
3437 
 
3438 
  PC = cia;
3439 
  dstreg = translate_rreg (SD_, RN0);
3440 
 
3441 
  temp = ((signed64)(signed32)State.regs[dstreg]
3442 
          *  (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3443 
  State.regs[dstreg] = temp & 0xffffffff;
3444 
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3445 
  z = (State.regs[dstreg] == 0);
3446 
  n = (State.regs[dstreg] & 0x80000000) != 0;
3447 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3448 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3449 
}
3450 
 
3451 
// 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3452 
8.0xfd+8.0xb9+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::mulu
3453 
"mulu"
3454 
*am33
3455 
{
3456 
  int dstreg;
3457 
  unsigned long long temp;
3458 
  int z, n;
3459 
 
3460 
  PC = cia;
3461 
  dstreg = translate_rreg (SD_, RN0);
3462 
 
3463 
  temp = ((unsigned64)State.regs[dstreg]
3464 
          *  (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
3465 
  State.regs[dstreg] = temp & 0xffffffff;
3466 
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
3467 
  z = (State.regs[dstreg] == 0);
3468 
  n = (State.regs[dstreg] & 0x80000000) != 0;
3469 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3470 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3471 
}
3472 
 
3473 
// 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3474 
8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3475 
"btst"
3476 
*am33
3477 
{
3478 
  int srcreg;
3479 
 
3480 
  PC = cia;
3481 
  srcreg = translate_rreg (SD_, RN0);
3482 
  genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3483 
}
3484 
 
3485 
// 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3486 
8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3487 
"mov"
3488 
*am33
3489 
{
3490 
  int srcreg, dstreg;
3491 
 
3492 
  PC = cia;
3493 
  srcreg = translate_rreg (SD_, RM0);
3494 
  dstreg = translate_rreg (SD_, RN2);
3495 
  State.regs[dstreg] = load_word (State.regs[srcreg]
3496 
                                  + EXTEND24 (FETCH24 (IMM24A,
3497 
                                                       IMM24B, IMM24C)));
3498 
}
3499 
 
3500 
// 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3501 
8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3502 
"mov"
3503 
*am33
3504 
{
3505 
  int srcreg, dstreg;
3506 
 
3507 
  PC = cia;
3508 
  srcreg = translate_rreg (SD_, RM2);
3509 
  dstreg = translate_rreg (SD_, RN0);
3510 
  store_word (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3511 
              State.regs[srcreg]);
3512 
}
3513 
 
3514 
// 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3515 
8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3516 
"movbu"
3517 
*am33
3518 
{
3519 
  int srcreg, dstreg;
3520 
 
3521 
  PC = cia;
3522 
  srcreg = translate_rreg (SD_, RM0);
3523 
  dstreg = translate_rreg (SD_, RN2);
3524 
  State.regs[dstreg] = load_byte (State.regs[srcreg]
3525 
                                  + EXTEND24 (FETCH24 (IMM24A,
3526 
                                                       IMM24B, IMM24C)));
3527 
}
3528 
 
3529 
// 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3530 
8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3531 
"movbu"
3532 
*am33
3533 
{
3534 
  int srcreg, dstreg;
3535 
 
3536 
  PC = cia;
3537 
  srcreg = translate_rreg (SD_, RM2);
3538 
  dstreg = translate_rreg (SD_, RN0);
3539 
  store_byte (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3540 
              State.regs[srcreg]);
3541 
}
3542 
 
3543 
// 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3544 
8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3545 
"movhu"
3546 
*am33
3547 
{
3548 
  int srcreg, dstreg;
3549 
 
3550 
  PC = cia;
3551 
  srcreg = translate_rreg (SD_, RM0);
3552 
  dstreg = translate_rreg (SD_, RN2);
3553 
  State.regs[dstreg] = load_half (State.regs[srcreg]
3554 
                                  + EXTEND24 (FETCH24 (IMM24A,
3555 
                                              IMM24B, IMM24C)));
3556 
}
3557 
 
3558 
// 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3559 
8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3560 
"movhu"
3561 
*am33
3562 
{
3563 
  int srcreg, dstreg;
3564 
 
3565 
  PC = cia;
3566 
  srcreg = translate_rreg (SD_, RM2);
3567 
  dstreg = translate_rreg (SD_, RN0);
3568 
  store_half (State.regs[dstreg] + EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)),
3569 
              State.regs[srcreg]);
3570 
}
3571 
 
3572 
// 1111 1101 0110 1010 Rn Rm IMM24; mov (d24,Rm+),Rn
3573 
8.0xfd+8.0x6a+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::mov
3574 
"mov"
3575 
*am33
3576 
{
3577 
  int srcreg, dstreg;
3578 
 
3579 
  PC = cia;
3580 
  srcreg = translate_rreg (SD_, RM0);
3581 
  dstreg = translate_rreg (SD_, RN2);
3582 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
3583 
  State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3584 
}
3585 
 
3586 
// 1111 1101 0111 1010 Rm Rn IMM24; mov Rm,(d24,Rn+)
3587 
8.0xfd+8.0x7a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mov
3588 
"mov"
3589 
*am33
3590 
{
3591 
  int srcreg, dstreg;
3592 
 
3593 
  PC = cia;
3594 
  srcreg = translate_rreg (SD_, RM2);
3595 
  dstreg = translate_rreg (SD_, RN0);
3596 
  store_word (State.regs[dstreg], State.regs[srcreg]);
3597 
  State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3598 
}
3599 
 
3600 
 
3601 
// 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3602 
8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3603 
"mov"
3604 
*am33
3605 
{
3606 
  int dstreg;
3607 
 
3608 
  PC = cia;
3609 
  dstreg = translate_rreg (SD_, RN2);
3610 
  State.regs[dstreg] = load_word (State.regs[REG_SP]
3611 
                                  + FETCH24 (IMM24A, IMM24B, IMM24C));
3612 
}
3613 
 
3614 
// 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3615 
8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3616 
"mov"
3617 
*am33
3618 
{
3619 
  int srcreg;
3620 
 
3621 
  PC = cia;
3622 
  srcreg = translate_rreg (SD_, RM2);
3623 
  store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3624 
              State.regs[srcreg]);
3625 
}
3626 
 
3627 
// 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3628 
8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3629 
"movbu"
3630 
*am33
3631 
{
3632 
  int dstreg;
3633 
 
3634 
  PC = cia;
3635 
  dstreg = translate_rreg (SD_, RN2);
3636 
  State.regs[dstreg] = load_byte (State.regs[REG_SP]
3637 
                                  + EXTEND24 (FETCH24 (IMM24A,
3638 
                                                       IMM24B, IMM24C)));
3639 
}
3640 
 
3641 
// 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3642 
8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3643 
"movbu"
3644 
*am33
3645 
{
3646 
  int srcreg;
3647 
 
3648 
  PC = cia;
3649 
  srcreg = translate_rreg (SD_, RM2);
3650 
  store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3651 
              State.regs[srcreg]);
3652 
}
3653 
 
3654 
// 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3655 
8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3656 
"movhu"
3657 
*am33
3658 
{
3659 
  int dstreg;
3660 
 
3661 
  PC = cia;
3662 
  dstreg = translate_rreg (SD_, RN2);
3663 
  State.regs[dstreg] = load_half (State.regs[REG_SP]
3664 
                                  + FETCH24 (IMM24A, IMM24B, IMM24C));
3665 
}
3666 
 
3667 
// 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3668 
8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3669 
"movhu"
3670 
*am33
3671 
{
3672 
  int srcreg;
3673 
 
3674 
  PC = cia;
3675 
  srcreg = translate_rreg (SD_, RM2);
3676 
  store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3677 
              State.regs[srcreg]);
3678 
}
3679 
 
3680 
// 1111 1101 1110 1010 Rn Rm IMM24; movhu (d24,Rm+),Rn
3681 
8.0xfd+8.0xea+4.RN2,4.RM0!RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4y:::movhu
3682 
"movhu"
3683 
*am33
3684 
{
3685 
  int srcreg, dstreg;
3686 
 
3687 
  PC = cia;
3688 
  srcreg = translate_rreg (SD_, RM0);
3689 
  dstreg = translate_rreg (SD_, RN2);
3690 
  State.regs[dstreg] = load_half (State.regs[srcreg]);
3691 
  State.regs[dstreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3692 
}
3693 
 
3694 
// 1111 1101 1111 1010 Rm Rn IMM24; movhu Rm,(d24,Rn+)
3695 
8.0xfd+8.0xfa+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::movhu
3696 
"movhu"
3697 
*am33
3698 
{
3699 
  int srcreg, dstreg;
3700 
 
3701 
  PC = cia;
3702 
  srcreg = translate_rreg (SD_, RM2);
3703 
  dstreg = translate_rreg (SD_, RN0);
3704 
  store_half (State.regs[dstreg], State.regs[srcreg]);
3705 
  State.regs[srcreg] += EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
3706 
}
3707 
 
3708 
// 1111 1101 0000 1011 Rn IMM24; mac imm24,Rn
3709 
8.0xfd+8.0x0b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mac
3710 
"mac"
3711 
*am33
3712 
{
3713 
  int srcreg;
3714 
  long long temp, sum;
3715 
  int c, v;
3716 
 
3717 
  PC = cia;
3718 
  srcreg = translate_rreg (SD_, RN2);
3719 
 
3720 
  temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
3721 
          * (signed64)State.regs[srcreg]);
3722 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3723 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3724 
  State.regs[REG_MCRL] = sum;
3725 
  temp >>= 32;
3726 
  temp &= 0xffffffff;
3727 
  sum = State.regs[REG_MCRH] + temp + c;
3728 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3729 
        && (temp & 0x80000000) != (sum & 0x80000000));
3730 
  State.regs[REG_MCRH] = sum;
3731 
  if (v)
3732 
    State.regs[REG_MCVF] = 1;
3733 
}
3734 
 
3735 
// 1111 1101 0001 1011 Rn IMM24; macu imm24,Rn
3736 
8.0xfd+8.0x1b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macu
3737 
"macu"
3738 
*am33
3739 
{
3740 
  int srcreg;
3741 
  long long temp, sum;
3742 
  int c, v;
3743 
 
3744 
  PC = cia;
3745 
  srcreg = translate_rreg (SD_, RN2);
3746 
 
3747 
  temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3748 
          * (unsigned64)State.regs[srcreg]);
3749 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3750 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3751 
  State.regs[REG_MCRL] = sum;
3752 
  temp >>= 32;
3753 
  temp &= 0xffffffff;
3754 
  sum = State.regs[REG_MCRH] + temp + c;
3755 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3756 
        && (temp & 0x80000000) != (sum & 0x80000000));
3757 
  State.regs[REG_MCRH] = sum;
3758 
  if (v)
3759 
    State.regs[REG_MCVF] = 1;
3760 
}
3761 
 
3762 
// 1111 1101 0010 1011 Rn IMM24; macb imm24,Rn
3763 
8.0xfd+8.0x2b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macb
3764 
"macb"
3765 
*am33
3766 
{
3767 
  int srcreg;
3768 
  long long temp, sum;
3769 
  int c, v;
3770 
 
3771 
  PC = cia;
3772 
  srcreg = translate_rreg (SD_, RN2);
3773 
 
3774 
  temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
3775 
          * (signed64)State.regs[srcreg] & 0xff);
3776 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3777 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3778 
  State.regs[REG_MCRL] = sum;
3779 
  temp >>= 32;
3780 
  temp &= 0xffffffff;
3781 
  sum = State.regs[REG_MCRH] + temp + c;
3782 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3783 
        && (temp & 0x80000000) != (sum & 0x80000000));
3784 
  State.regs[REG_MCRH] = sum;
3785 
  if (v)
3786 
    State.regs[REG_MCVF] = 1;
3787 
}
3788 
 
3789 
// 1111 1101 0011 1011 Rn IMM24; macbu imm24,Rn
3790 
8.0xfd+8.0x3b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::macbu
3791 
"macbu"
3792 
*am33
3793 
{
3794 
  int srcreg;
3795 
  long long temp, sum;
3796 
  int c, v;
3797 
 
3798 
  PC = cia;
3799 
  srcreg = translate_rreg (SD_, RN2);
3800 
 
3801 
  temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
3802 
          * (unsigned64)State.regs[srcreg] & 0xff);
3803 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3804 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3805 
  State.regs[REG_MCRL] = sum;
3806 
  temp >>= 32;
3807 
  temp &= 0xffffffff;
3808 
  sum = State.regs[REG_MCRH] + temp + c;
3809 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3810 
        && (temp & 0x80000000) != (sum & 0x80000000));
3811 
  State.regs[REG_MCRH] = sum;
3812 
  if (v)
3813 
    State.regs[REG_MCVF] = 1;
3814 
}
3815 
 
3816 
// 1111 1101 0100 1011 Rn IMM24; mach imm24,Rn
3817 
8.0xfd+8.0x4b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::mach
3818 
"mach"
3819 
*am33
3820 
{
3821 
  int srcreg;
3822 
  long long temp, sum;
3823 
  int c, v;
3824 
 
3825 
  PC = cia;
3826 
  srcreg = translate_rreg (SD_, RN2);
3827 
 
3828 
  temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
3829 
          * (signed64)State.regs[srcreg] & 0xffff);
3830 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3831 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3832 
  State.regs[REG_MCRL] = sum;
3833 
  temp >>= 32;
3834 
  temp &= 0xffffffff;
3835 
  sum = State.regs[REG_MCRH] + temp + c;
3836 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3837 
        && (temp & 0x80000000) != (sum & 0x80000000));
3838 
  State.regs[REG_MCRH] = sum;
3839 
  if (v)
3840 
    State.regs[REG_MCVF] = 1;
3841 
}
3842 
 
3843 
// 1111 1101 0101 1011 Rn IMM24; machu imm24,Rn
3844 
8.0xfd+8.0x5b+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4z:::machu
3845 
"machu"
3846 
*am33
3847 
{
3848 
  int srcreg;
3849 
  long long temp, sum;
3850 
  int c, v;
3851 
 
3852 
  PC = cia;
3853 
  srcreg = translate_rreg (SD_, RN2);
3854 
 
3855 
  temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
3856 
          * (unsigned64)State.regs[srcreg] & 0xffff);
3857 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
3858 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
3859 
  State.regs[REG_MCRL] = sum;
3860 
  temp >>= 32;
3861 
  temp &= 0xffffffff;
3862 
  sum = State.regs[REG_MCRH] + temp + c;
3863 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
3864 
        && (temp & 0x80000000) != (sum & 0x80000000));
3865 
  State.regs[REG_MCRH] = sum;
3866 
  if (v)
3867 
    State.regs[REG_MCVF] = 1;
3868 
}
3869 
 
3870 
// 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3871 
8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3872 
"mov"
3873 
*am33
3874 
{
3875 
  int dstreg;
3876 
 
3877 
  PC = cia;
3878 
  dstreg = translate_rreg (SD_, RN2);
3879 
  State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3880 
}
3881 
 
3882 
// 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3883 
8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3884 
"mov"
3885 
*am33
3886 
{
3887 
  int srcreg;
3888 
 
3889 
  PC = cia;
3890 
  srcreg = translate_rreg (SD_, RM2);
3891 
  store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3892 
}
3893 
 
3894 
 
3895 
// 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3896 
8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3897 
"movbu"
3898 
*am33
3899 
{
3900 
  int dstreg;
3901 
 
3902 
  PC = cia;
3903 
  dstreg = translate_rreg (SD_, RN2);
3904 
  State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3905 
}
3906 
 
3907 
// 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3908 
8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3909 
"movbu"
3910 
*am33
3911 
{
3912 
  int srcreg;
3913 
 
3914 
  PC = cia;
3915 
  srcreg = translate_rreg (SD_, RM2);
3916 
  store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3917 
}
3918 
 
3919 
 
3920 
// 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3921 
8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3922 
"movhu"
3923 
*am33
3924 
{
3925 
  int dstreg;
3926 
 
3927 
  PC = cia;
3928 
  dstreg = translate_rreg (SD_, RN2);
3929 
  State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3930 
}
3931 
 
3932 
// 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3933 
8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3934 
"movhu"
3935 
*am33
3936 
{
3937 
  int srcreg;
3938 
 
3939 
  PC = cia;
3940 
  srcreg = translate_rreg (SD_, RM2);
3941 
  store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3942 
}
3943 
 
3944 
 
3945 
// 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3946 
8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3947 
"mov"
3948 
*am33
3949 
{
3950 
  int dstreg;
3951 
 
3952 
  PC = cia;
3953 
  dstreg = translate_rreg (SD_, RN0);
3954 
  State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3955 
}
3956 
 
3957 
// 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3958 
8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3959 
"movu"
3960 
*am33
3961 
{
3962 
  int dstreg;
3963 
 
3964 
  PC = cia;
3965 
  dstreg = translate_rreg (SD_, RN0);
3966 
  State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3967 
}
3968 
 
3969 
// 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3970 
8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3971 
"add"
3972 
*am33
3973 
{
3974 
  int dstreg;
3975 
 
3976 
  PC = cia;
3977 
  dstreg = translate_rreg (SD_, RN0);
3978 
  genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3979 
}
3980 
 
3981 
// 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3982 
8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3983 
"addc"
3984 
*am33
3985 
{
3986 
  int dstreg;
3987 
  unsigned int imm, reg2, sum;
3988 
  int z, n, c, v;
3989 
 
3990 
  PC = cia;
3991 
  dstreg = translate_rreg (SD_, RN0);
3992 
 
3993 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3994 
  reg2 = State.regs[dstreg];
3995 
  sum = imm + reg2 + ((PSW & PSW_C) != 0);
3996 
  State.regs[dstreg] = sum;
3997 
 
3998 
  z = ((PSW & PSW_Z) != 0) && (sum == 0);
3999 
  n = (sum & 0x80000000);
4000 
  c = (sum < imm) || (sum < reg2);
4001 
  v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4002 
       && (reg2 & 0x80000000) != (sum & 0x80000000));
4003 
 
4004 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4005 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4006 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4007 
}
4008 
 
4009 
// 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
4010 
8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
4011 
"sub"
4012 
*am33
4013 
{
4014 
  int dstreg;
4015 
 
4016 
  PC = cia;
4017 
  dstreg = translate_rreg (SD_, RN0);
4018 
  genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
4019 
}
4020 
 
4021 
// 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
4022 
8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
4023 
"subc"
4024 
*am33
4025 
{
4026 
  int dstreg;
4027 
  unsigned int imm, reg2, difference;
4028 
  int z, n, c, v;
4029 
 
4030 
  PC = cia;
4031 
  dstreg = translate_rreg (SD_, RN0);
4032 
 
4033 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4034 
  reg2 = State.regs[dstreg];
4035 
  difference = reg2 - imm - ((PSW & PSW_C) != 0);
4036 
  State.regs[dstreg] = difference;
4037 
 
4038 
  z = ((PSW & PSW_Z) != 0) && (difference == 0);
4039 
  n = (difference & 0x80000000);
4040 
  c = (imm > reg2);
4041 
  v = ((reg2 & 0x80000000) == (imm & 0x80000000)
4042 
       && (reg2 & 0x80000000) != (difference & 0x80000000));
4043 
 
4044 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4045 
  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
4046 
          | (c ? PSW_C : 0) | (v ? PSW_V : 0));
4047 
}
4048 
 
4049 
// 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
4050 
8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
4051 
"cmp"
4052 
*am33
4053 
{
4054 
  int srcreg;
4055 
 
4056 
  PC = cia;
4057 
  srcreg = translate_rreg (SD_, RN0);
4058 
  genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4059 
}
4060 
 
4061 
// 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
4062 
8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
4063 
"mov"
4064 
*am33
4065 
{
4066 
  int dstreg;
4067 
 
4068 
  PC = cia;
4069 
  dstreg = translate_xreg (SD_, XRN0);
4070 
 
4071 
  State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
4072 
}
4073 
 
4074 
// 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
4075 
8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
4076 
"and"
4077 
*am33
4078 
{
4079 
  int dstreg;
4080 
  int z,n;
4081 
 
4082 
  PC = cia;
4083 
  dstreg = translate_rreg (SD_, RN0);
4084 
 
4085 
  State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4086 
  z = (State.regs[dstreg] == 0);
4087 
  n = (State.regs[dstreg] & 0x80000000) != 0;
4088 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4089 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4090 
}
4091 
 
4092 
// 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
4093 
8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
4094 
"or"
4095 
*am33
4096 
{
4097 
  int dstreg;
4098 
  int z,n;
4099 
 
4100 
  PC = cia;
4101 
  dstreg = translate_rreg (SD_, RN0);
4102 
 
4103 
  State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4104 
  z = (State.regs[dstreg] == 0);
4105 
  n = (State.regs[dstreg] & 0x80000000) != 0;
4106 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4107 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4108 
}
4109 
 
4110 
// 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
4111 
8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
4112 
"xor"
4113 
*am33
4114 
{
4115 
  int dstreg;
4116 
  int z,n;
4117 
 
4118 
  PC = cia;
4119 
  dstreg = translate_rreg (SD_, RN0);
4120 
 
4121 
  State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4122 
  z = (State.regs[dstreg] == 0);
4123 
  n = (State.regs[dstreg] & 0x80000000) != 0;
4124 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4125 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4126 
}
4127 
 
4128 
// 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
4129 
8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
4130 
"asr"
4131 
*am33
4132 
{
4133 
  int dstreg;
4134 
  long temp;
4135 
  int c, z, n;
4136 
 
4137 
  PC = cia;
4138 
  dstreg = translate_rreg (SD_, RN0);
4139 
 
4140 
  temp = State.regs[dstreg];
4141 
  c = temp & 1;
4142 
  temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4143 
  State.regs[dstreg] = temp;
4144 
  z = (State.regs[dstreg] == 0);
4145 
  n = (State.regs[dstreg] & 0x80000000) != 0;
4146 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
4147 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4148 
}
4149 
 
4150 
// 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
4151 
8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
4152 
"lsr"
4153 
*am33
4154 
{
4155 
  int dstreg;
4156 
  int z, n, c;
4157 
 
4158 
  PC = cia;
4159 
  dstreg = translate_rreg (SD_, RN0);
4160 
 
4161 
  c = State.regs[dstreg] & 1;
4162 
  State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4163 
  z = (State.regs[dstreg] == 0);
4164 
  n = (State.regs[dstreg] & 0x80000000) != 0;
4165 
  PSW &= ~(PSW_Z | PSW_N | PSW_C);
4166 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
4167 
}
4168 
 
4169 
// 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
4170 
8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
4171 
"asl"
4172 
*am33
4173 
{
4174 
  int srcreg, dstreg;
4175 
  int z, n;
4176 
 
4177 
  PC = cia;
4178 
  dstreg = translate_rreg (SD_, RN0);
4179 
 
4180 
  State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4181 
  z = (State.regs[dstreg] == 0);
4182 
  n = (State.regs[dstreg] & 0x80000000) != 0;
4183 
  PSW &= ~(PSW_Z | PSW_N);
4184 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4185 
}
4186 
 
4187 
// 1111 1110 1010 1001 Rn Rn IMM32; mul imm32,Rn
4188 
8.0xfe+8.0xa9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mul
4189 
"mul"
4190 
*am33
4191 
{
4192 
  int dstreg;
4193 
  unsigned long long temp;
4194 
  int z, n;
4195 
 
4196 
  PC = cia;
4197 
  dstreg = translate_rreg (SD_, RN0);
4198 
 
4199 
  temp = ((signed64)(signed32)State.regs[dstreg]
4200 
          *  (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4201 
  State.regs[dstreg] = temp & 0xffffffff;
4202 
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4203 
  z = (State.regs[dstreg] == 0);
4204 
  n = (State.regs[dstreg] & 0x80000000) != 0;
4205 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4206 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4207 
}
4208 
 
4209 
// 1111 1110 1011 1001 Rn Rn IMM32; mulu imm32,Rn
4210 
8.0xfe+8.0xb9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mulu
4211 
"mulu"
4212 
*am33
4213 
{
4214 
  int dstreg;
4215 
  unsigned long long temp;
4216 
  int z, n;
4217 
 
4218 
  PC = cia;
4219 
  dstreg = translate_rreg (SD_, RN0);
4220 
 
4221 
  temp = ((unsigned64)State.regs[dstreg]
4222 
          *  (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
4223 
  State.regs[dstreg] = temp & 0xffffffff;
4224 
  State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
4225 
  z = (State.regs[dstreg] == 0);
4226 
  n = (State.regs[dstreg] & 0x80000000) != 0;
4227 
  PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
4228 
  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
4229 
}
4230 
 
4231 
// 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
4232 
8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
4233 
"btst"
4234 
*am33
4235 
{
4236 
  int srcreg;
4237 
 
4238 
  PC = cia;
4239 
  srcreg = translate_rreg (SD_, RN0);
4240 
  genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4241 
}
4242 
 
4243 
// 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
4244 
8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
4245 
"mov"
4246 
*am33
4247 
{
4248 
  int srcreg, dstreg;
4249 
 
4250 
  PC = cia;
4251 
  srcreg = translate_rreg (SD_, RM0);
4252 
  dstreg = translate_rreg (SD_, RN2);
4253 
  State.regs[dstreg] = load_word (State.regs[srcreg]
4254 
                                  + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4255 
}
4256 
 
4257 
// 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
4258 
8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
4259 
"mov"
4260 
*am33
4261 
{
4262 
  int srcreg, dstreg;
4263 
 
4264 
  PC = cia;
4265 
  srcreg = translate_rreg (SD_, RM2);
4266 
  dstreg = translate_rreg (SD_, RN0);
4267 
  store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4268 
              State.regs[srcreg]);
4269 
}
4270 
 
4271 
// 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
4272 
8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
4273 
"movbu"
4274 
*am33
4275 
{
4276 
  int srcreg, dstreg;
4277 
 
4278 
  PC = cia;
4279 
  srcreg = translate_rreg (SD_, RM0);
4280 
  dstreg = translate_rreg (SD_, RN2);
4281 
  State.regs[dstreg] = load_byte (State.regs[srcreg]
4282 
                                  + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4283 
}
4284 
 
4285 
// 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
4286 
8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
4287 
"movbu"
4288 
*am33
4289 
{
4290 
  int srcreg, dstreg;
4291 
 
4292 
  PC = cia;
4293 
  srcreg = translate_rreg (SD_, RM2);
4294 
  dstreg = translate_rreg (SD_, RN0);
4295 
  store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4296 
              State.regs[srcreg]);
4297 
}
4298 
 
4299 
// 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
4300 
8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
4301 
"movhu"
4302 
*am33
4303 
{
4304 
  int srcreg, dstreg;
4305 
 
4306 
  PC = cia;
4307 
  srcreg = translate_rreg (SD_, RM0);
4308 
  dstreg = translate_rreg (SD_, RN2);
4309 
  State.regs[dstreg] = load_half (State.regs[srcreg]
4310 
                                  + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4311 
}
4312 
 
4313 
// 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
4314 
8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
4315 
"movhu"
4316 
*am33
4317 
{
4318 
  int srcreg, dstreg;
4319 
 
4320 
  PC = cia;
4321 
  srcreg = translate_rreg (SD_, RM2);
4322 
  dstreg = translate_rreg (SD_, RN0);
4323 
  store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4324 
              State.regs[srcreg]);
4325 
}
4326 
 
4327 
// 1111 1110 0110 1010 Rn Rm IMM32; mov (d32,Rm+),Rn
4328 
8.0xfe+8.0x6a+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::mov
4329 
"mov"
4330 
*am33
4331 
{
4332 
  int srcreg, dstreg;
4333 
 
4334 
  PC = cia;
4335 
  srcreg = translate_rreg (SD_, RM0);
4336 
  dstreg = translate_rreg (SD_, RN2);
4337 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
4338 
  State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4339 
}
4340 
 
4341 
// 1111 1110 0111 1010 Rm Rn IMM32; mov Rm,(d32,Rn+)
4342 
8.0xfe+8.0x7a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5z:::mov
4343 
"mov"
4344 
*am33
4345 
{
4346 
  int srcreg, dstreg;
4347 
 
4348 
  PC = cia;
4349 
  srcreg = translate_rreg (SD_, RM2);
4350 
  dstreg = translate_rreg (SD_, RN0);
4351 
  store_word (State.regs[dstreg], State.regs[srcreg]);
4352 
  State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4353 
}
4354 
 
4355 
 
4356 
// 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
4357 
8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
4358 
"mov"
4359 
*am33
4360 
{
4361 
  int dstreg;
4362 
 
4363 
  PC = cia;
4364 
  dstreg = translate_rreg (SD_, RN2);
4365 
  State.regs[dstreg] = load_word (State.regs[REG_SP]
4366 
                                  + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4367 
}
4368 
 
4369 
// 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
4370 
8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
4371 
"mov"
4372 
*am33
4373 
{
4374 
  int srcreg;
4375 
 
4376 
  PC = cia;
4377 
  srcreg = translate_rreg (SD_, RM2);
4378 
  store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4379 
              State.regs[srcreg]);
4380 
}
4381 
 
4382 
// 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
4383 
8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
4384 
"movbu"
4385 
*am33
4386 
{
4387 
  int dstreg;
4388 
 
4389 
  PC = cia;
4390 
  dstreg = translate_rreg (SD_, RN2);
4391 
  State.regs[dstreg] = load_byte (State.regs[REG_SP]
4392 
                                  + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4393 
}
4394 
 
4395 
// 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
4396 
8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4397 
"movbu"
4398 
*am33
4399 
{
4400 
  int srcreg;
4401 
 
4402 
  PC = cia;
4403 
  srcreg = translate_rreg (SD_, RM2);
4404 
  store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4405 
              State.regs[srcreg]);
4406 
}
4407 
 
4408 
// 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4409 
8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4410 
"movhu"
4411 
*am33
4412 
{
4413 
  int dstreg;
4414 
 
4415 
  PC = cia;
4416 
  dstreg = translate_rreg (SD_, RN2);
4417 
  State.regs[dstreg] = load_half (State.regs[REG_SP]
4418 
                                  + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4419 
}
4420 
 
4421 
// 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4422 
8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4423 
"movhu"
4424 
*am33
4425 
{
4426 
  int srcreg;
4427 
 
4428 
  PC = cia;
4429 
  srcreg = translate_rreg (SD_, RM2);
4430 
  store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4431 
              State.regs[srcreg]);
4432 
}
4433 
 
4434 
 
4435 
// 1111 1110 1110 1010 Rn Rm IMM32; movhu (d32,Rm+),Rn
4436 
8.0xfe+8.0xea+4.RN2,4.RM0!RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5y:::movhu
4437 
"movhu"
4438 
*am33
4439 
{
4440 
  int srcreg, dstreg;
4441 
 
4442 
  PC = cia;
4443 
  srcreg = translate_rreg (SD_, RM0);
4444 
  dstreg = translate_rreg (SD_, RN2);
4445 
  State.regs[dstreg] = load_half (State.regs[srcreg]);
4446 
  State.regs[srcreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4447 
}
4448 
 
4449 
// 1111 1110 1111 1010 Rm Rn IMM32; movhu Rm,(d32,Rn+)
4450 
8.0xfe+8.0xfa+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::movhu
4451 
"movhu"
4452 
*am33
4453 
{
4454 
  int srcreg, dstreg;
4455 
 
4456 
  PC = cia;
4457 
  srcreg = translate_rreg (SD_, RM2);
4458 
  dstreg = translate_rreg (SD_, RN0);
4459 
  store_half (State.regs[dstreg], State.regs[srcreg]);
4460 
  State.regs[dstreg] += FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4461 
}
4462 
 
4463 
 
4464 
// 1111 1110 0000 1011 Rn Rn IMM32; mac imm32,Rn
4465 
8.0xfe+8.0x0b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mac
4466 
"mac"
4467 
*am33
4468 
{
4469 
  int srcreg, imm;
4470 
  long long temp, sum;
4471 
  int c, v;
4472 
 
4473 
  PC = cia;
4474 
  srcreg = translate_rreg (SD_, RN0);
4475 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4476 
 
4477 
  temp = ((signed64)(signed32)State.regs[srcreg]
4478 
          * (signed64)(signed32)imm);
4479 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4480 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4481 
  State.regs[REG_MCRL] = sum;
4482 
  temp >>= 32;
4483 
  temp &= 0xffffffff;
4484 
  sum = State.regs[REG_MCRH] + temp + c;
4485 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4486 
        && (temp & 0x80000000) != (sum & 0x80000000));
4487 
  State.regs[REG_MCRH] = sum;
4488 
  if (v)
4489 
    State.regs[REG_MCVF] = 1;
4490 
}
4491 
 
4492 
// 1111 1110 0001 1011 Rn Rn IMM32; macu imm32,Rn
4493 
8.0xfe+8.0x1b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macu
4494 
"macu"
4495 
*am33
4496 
{
4497 
  int srcreg, imm;
4498 
  long long temp, sum;
4499 
  int c, v;
4500 
 
4501 
  PC = cia;
4502 
  srcreg = translate_rreg (SD_, RN0);
4503 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4504 
 
4505 
  temp = ((unsigned64)State.regs[srcreg]
4506 
          * (unsigned64)imm);
4507 
  sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
4508 
  c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
4509 
  State.regs[REG_MCRL] = sum;
4510 
  temp >>= 32;
4511 
  temp &= 0xffffffff;
4512 
  sum = State.regs[REG_MCRH] + temp + c;
4513 
  v = ((State.regs[REG_MCRH] & 0x80000000) == (temp & 0x80000000)
4514 
        && (temp & 0x80000000) != (sum & 0x80000000));
4515 
  State.regs[REG_MCRH] = sum;
4516 
  if (v)
4517 
    State.regs[REG_MCVF] = 1;
4518 
}
4519 
 
4520 
// 1111 1110 0010 1011 Rn Rn IMM32; macb imm32,Rn
4521 
8.0xfe+8.0x2b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macb
4522 
"macb"
4523 
*am33
4524 
{
4525 
  int srcreg, imm;
4526 
  long temp, sum;
4527 
  int v;
4528 
 
4529 
  PC = cia;
4530 
  srcreg = translate_rreg (SD_, RN0);
4531 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4532 
 
4533 
  temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
4534 
          * (signed32)(signed8)(imm & 0xff));
4535 
  sum = State.regs[REG_MCRL] + temp;
4536 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4537 
        && (temp & 0x80000000) != (sum & 0x80000000));
4538 
  State.regs[REG_MCRL] = sum;
4539 
  if (v)
4540 
    State.regs[REG_MCVF] = 1;
4541 
}
4542 
 
4543 
// 1111 1110 0011 1011 Rn Rn IMM32; macbu imm32,Rn
4544 
8.0xfe+8.0x3b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::macbu
4545 
"macbu"
4546 
*am33
4547 
{
4548 
  int srcreg, imm;
4549 
  long temp, sum;
4550 
  int v;
4551 
 
4552 
  PC = cia;
4553 
  srcreg = translate_rreg (SD_, RN0);
4554 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4555 
 
4556 
  temp = ((unsigned32)(State.regs[srcreg] & 0xff)
4557 
          * (unsigned32)(imm & 0xff));
4558 
  sum = State.regs[REG_MCRL] + temp;
4559 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4560 
        && (temp & 0x80000000) != (sum & 0x80000000));
4561 
  State.regs[REG_MCRL] = sum;
4562 
  if (v)
4563 
    State.regs[REG_MCVF] = 1;
4564 
}
4565 
 
4566 
// 1111 1110 0100 1011 Rn Rn IMM32; mach imm32,Rn
4567 
8.0xfe+8.0x4b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mach
4568 
"mach"
4569 
*am33
4570 
{
4571 
  int srcreg, imm;
4572 
  long temp, sum;
4573 
  int v;
4574 
 
4575 
  PC = cia;
4576 
  srcreg = translate_rreg (SD_, RN0);
4577 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4578 
 
4579 
  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4580 
          * (signed32)(signed16)(imm & 0xffff));
4581 
  sum = State.regs[REG_MCRL] + temp;
4582 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4583 
        && (temp & 0x80000000) != (sum & 0x80000000));
4584 
  State.regs[REG_MCRL] = sum;
4585 
  if (v)
4586 
    State.regs[REG_MCVF] = 1;
4587 
}
4588 
 
4589 
// 1111 1110 0101 1011 Rn Rn IMM32; machu imm32,Rn
4590 
8.0xfe+8.0x5b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::machu
4591 
"machu"
4592 
*am33
4593 
{
4594 
  int srcreg, imm;
4595 
  long temp, sum;
4596 
  int v;
4597 
 
4598 
  PC = cia;
4599 
  srcreg = translate_rreg (SD_, RN0);
4600 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4601 
 
4602 
  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4603 
          * (unsigned32)(imm & 0xffff));
4604 
  sum = State.regs[REG_MCRL] + temp;
4605 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4606 
        && (temp & 0x80000000) != (sum & 0x80000000));
4607 
  State.regs[REG_MCRL] = sum;
4608 
  if (v)
4609 
    State.regs[REG_MCVF] = 1;
4610 
}
4611 
 
4612 
// 1111 1110 0110 1011 Rn Rn IMM32; dmach imm32,Rn
4613 
8.0xfe+8.0x6b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmach
4614 
"dmach"
4615 
*am33
4616 
{
4617 
  int srcreg, imm;
4618 
  long temp, temp2, sum;
4619 
  int v;
4620 
 
4621 
  PC = cia;
4622 
  srcreg = translate_rreg (SD_, RN0);
4623 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4624 
 
4625 
  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
4626 
          * (signed32)(signed16)(imm & 0xffff));
4627 
  temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
4628 
           * (signed32)(signed16)((imm >> 16) & 0xffff));
4629 
  sum = temp + temp2 + State.regs[REG_MCRL];
4630 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4631 
        && (temp & 0x80000000) != (sum & 0x80000000));
4632 
  State.regs[REG_MCRL] = sum;
4633 
  if (v)
4634 
    State.regs[REG_MCVF] = 1;
4635 
}
4636 
 
4637 
// 1111 1110 0111 1011 Rn Rn IMM32; dmachu imm32,Rn
4638 
8.0xfe+8.0x7b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmachu
4639 
"dmachu"
4640 
*am33
4641 
{
4642 
  int srcreg, imm;
4643 
  long temp, temp2, sum;
4644 
  int v;
4645 
 
4646 
  PC = cia;
4647 
  srcreg = translate_rreg (SD_, RN0);
4648 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4649 
 
4650 
  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
4651 
          * (unsigned32)(imm & 0xffff));
4652 
  temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
4653 
           * (unsigned32)((imm >> 16) & 0xffff));
4654 
  sum = temp + temp2 + State.regs[REG_MCRL];
4655 
  v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
4656 
        && (temp & 0x80000000) != (sum & 0x80000000));
4657 
  State.regs[REG_MCRL] = sum;
4658 
  if (v)
4659 
    State.regs[REG_MCVF] = 1;
4660 
}
4661 
 
4662 
// 1111 1110 1000 1011 Rn Rn IMM32; dmulh imm32,Rn
4663 
8.0xfe+8.0x8b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulh
4664 
"dmulh"
4665 
*am33
4666 
{
4667 
  int imm, dstreg;
4668 
  long temp;
4669 
 
4670 
  PC = cia;
4671 
  dstreg = translate_rreg (SD_, RN0);
4672 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4673 
 
4674 
  temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
4675 
          * (signed32)(signed16)(imm & 0xffff));
4676 
  State.regs[REG_MDRQ] = temp;
4677 
  temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
4678 
          * (signed32)(signed16)((imm>>16) & 0xffff));
4679 
  State.regs[dstreg] = temp;
4680 
}
4681 
 
4682 
// 1111 1110 1001 1011 Rn Rn IMM32; dmulhu imm32,Rn
4683 
8.0xfe+8.0x9b+4.RN2,4.RN0=RN2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::dmulhu
4684 
"dmulhu"
4685 
*am33
4686 
{
4687 
  int imm, dstreg;
4688 
  long temp;
4689 
 
4690 
  PC = cia;
4691 
  dstreg = translate_rreg (SD_, RN0);
4692 
  imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
4693 
 
4694 
  temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
4695 
          * (unsigned32)(imm & 0xffff));
4696 
  State.regs[REG_MDRQ] = temp;
4697 
  temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
4698 
          * (unsigned32)((imm >>16) & 0xffff));
4699 
  State.regs[dstreg] = temp;
4700 
}
4701 
 
4702 
// 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4703 
8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4704 
"mov"
4705 
*am33
4706 
{
4707 
  int dstreg;
4708 
 
4709 
  PC = cia;
4710 
  dstreg = translate_rreg (SD_, RN2);
4711 
  State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4712 
}
4713 
 
4714 
// 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4715 
8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4716 
"mov"
4717 
*am33
4718 
{
4719 
  int srcreg;
4720 
 
4721 
  PC = cia;
4722 
  srcreg = translate_rreg (SD_, RM2);
4723 
  store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4724 
}
4725 
 
4726 
// 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4727 
8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4728 
"movbu"
4729 
*am33
4730 
{
4731 
  int dstreg;
4732 
 
4733 
  PC = cia;
4734 
  dstreg = translate_rreg (SD_, RN2);
4735 
  State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4736 
}
4737 
 
4738 
// 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4739 
8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4740 
"movbu"
4741 
*am33
4742 
{
4743 
  int srcreg;
4744 
 
4745 
  PC = cia;
4746 
  srcreg = translate_rreg (SD_, RM2);
4747 
  store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4748 
}
4749 
 
4750 
// 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4751 
8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4752 
"movhu"
4753 
*am33
4754 
{
4755 
  int dstreg;
4756 
 
4757 
  PC = cia;
4758 
  dstreg = translate_rreg (SD_, RN2);
4759 
  State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4760 
}
4761 
 
4762 
// 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4763 
8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4764 
"movhu"
4765 
*am33
4766 
{
4767 
  int srcreg;
4768 
 
4769 
  PC = cia;
4770 
  srcreg = translate_rreg (SD_, RM2);
4771 
  store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4772 
}
4773 
 
4774 
// 1111 0111 0000 0000 Rm1 Rn1 Rm2 Rn2; add_add Rm1, Rn1, Rm2, Rn2
4775 
8.0xf7+8.0x00+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_add
4776 
"add_add"
4777 
*am33
4778 
{
4779 
  int srcreg1, srcreg2, dstreg1, dstreg2;
4780 
  int result1;
4781 
 
4782 
  PC = cia;
4783 
  srcreg1 = translate_rreg (SD_, RM1);
4784 
  srcreg2 = translate_rreg (SD_, RM2);
4785 
  dstreg1 = translate_rreg (SD_, RN1);
4786 
  dstreg2 = translate_rreg (SD_, RN2);
4787 
 
4788 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4789 
  State.regs[dstreg2] += State.regs[srcreg2];
4790 
  State.regs[dstreg1] = result1;
4791 
}
4792 
 
4793 
// 1111 0111 0001 0000 Rm1 Rn1 imm4 Rn2; add_add Rm1, Rn1, imm4, Rn2
4794 
8.0xf7+8.0x10+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_add
4795 
"add_add"
4796 
*am33
4797 
{
4798 
  int srcreg1, dstreg1, dstreg2;
4799 
  int result1;
4800 
 
4801 
  PC = cia;
4802 
  srcreg1 = translate_rreg (SD_, RM1);
4803 
  dstreg1 = translate_rreg (SD_, RN1);
4804 
  dstreg2 = translate_rreg (SD_, RN2);
4805 
 
4806 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4807 
  State.regs[dstreg2] += EXTEND4 (IMM4);
4808 
  State.regs[dstreg1] = result1;
4809 
}
4810 
 
4811 
// 1111 0111 0010 0000 Rm1 Rn1 Rm2 Rn2; add_sub Rm1, Rn1, Rm2, Rn2
4812 
8.0xf7+8.0x20+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_sub
4813 
"add_sub"
4814 
*am33
4815 
{
4816 
  int srcreg1, srcreg2, dstreg1, dstreg2;
4817 
  int result1;
4818 
 
4819 
  PC = cia;
4820 
  srcreg1 = translate_rreg (SD_, RM1);
4821 
  srcreg2 = translate_rreg (SD_, RM2);
4822 
  dstreg1 = translate_rreg (SD_, RN1);
4823 
  dstreg2 = translate_rreg (SD_, RN2);
4824 
 
4825 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4826 
  State.regs[dstreg2] -= State.regs[srcreg2];
4827 
  State.regs[dstreg1] = result1;
4828 
}
4829 
 
4830 
// 1111 0111 0011 0000 Rm1 Rn1 imm4 Rn2; add_sub Rm1, Rn1, imm4, Rn2
4831 
8.0xf7+8.0x30+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_sub
4832 
"add_sub"
4833 
*am33
4834 
{
4835 
  int srcreg1, dstreg1, dstreg2;
4836 
  int result1;
4837 
 
4838 
  PC = cia;
4839 
  srcreg1 = translate_rreg (SD_, RM1);
4840 
  dstreg1 = translate_rreg (SD_, RN1);
4841 
  dstreg2 = translate_rreg (SD_, RN2);
4842 
 
4843 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4844 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
4845 
  State.regs[dstreg1] = result1;
4846 
}
4847 
 
4848 
// 1111 0111 0100 0000 Rm1 Rn1 Rm2 Rn2; add_cmp Rm1, Rn1, Rm2, Rn2
4849 
8.0xf7+8.0x40+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_cmp
4850 
"add_cmp"
4851 
*am33
4852 
{
4853 
  int srcreg1, srcreg2, dstreg1, dstreg2;
4854 
 
4855 
  PC = cia;
4856 
  srcreg1 = translate_rreg (SD_, RM1);
4857 
  srcreg2 = translate_rreg (SD_, RM2);
4858 
  dstreg1 = translate_rreg (SD_, RN1);
4859 
  dstreg2 = translate_rreg (SD_, RN2);
4860 
 
4861 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
4862 
  State.regs[dstreg1] += State.regs[srcreg1];
4863 
}
4864 
 
4865 
// 1111 0111 0101 0000 Rm1 Rn1 imm4 Rn2; add_cmp Rm1, Rn1, imm4, Rn2
4866 
8.0xf7+8.0x50+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_cmp
4867 
"add_cmp"
4868 
*am33
4869 
{
4870 
  int srcreg1, dstreg1, dstreg2;
4871 
 
4872 
  PC = cia;
4873 
  srcreg1 = translate_rreg (SD_, RM1);
4874 
  dstreg1 = translate_rreg (SD_, RN1);
4875 
  dstreg2 = translate_rreg (SD_, RN2);
4876 
 
4877 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
4878 
  State.regs[dstreg1] += State.regs[srcreg1];
4879 
}
4880 
 
4881 
// 1111 0111 0110 0000 Rm1 Rn1 Rm2 Rn2; add_mov Rm1, Rn1, Rm2, Rn2
4882 
8.0xf7+8.0x60+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_mov
4883 
"add_mov"
4884 
*am33
4885 
{
4886 
  int srcreg1, srcreg2, dstreg1, dstreg2;
4887 
  int result1;
4888 
 
4889 
  PC = cia;
4890 
  srcreg1 = translate_rreg (SD_, RM1);
4891 
  srcreg2 = translate_rreg (SD_, RM2);
4892 
  dstreg1 = translate_rreg (SD_, RN1);
4893 
  dstreg2 = translate_rreg (SD_, RN2);
4894 
 
4895 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4896 
  State.regs[dstreg2] = State.regs[srcreg2];
4897 
  State.regs[dstreg1] = result1;
4898 
}
4899 
 
4900 
// 1111 0111 0111 0000 Rm1 Rn1 imm4 Rn2; add_mov Rm1, Rn1, imm4, Rn2
4901 
8.0xf7+8.0x70+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_mov
4902 
"add_mov"
4903 
*am33
4904 
{
4905 
  int srcreg1, dstreg1, dstreg2;
4906 
  int result1;
4907 
 
4908 
  PC = cia;
4909 
  srcreg1 = translate_rreg (SD_, RM1);
4910 
  dstreg1 = translate_rreg (SD_, RN1);
4911 
  dstreg2 = translate_rreg (SD_, RN2);
4912 
 
4913 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4914 
  State.regs[dstreg2] = EXTEND4 (IMM4);
4915 
  State.regs[dstreg1] = result1;
4916 
}
4917 
 
4918 
// 1111 0111 1000 0000 Rm1 Rn1 Rm2 Rn2; add_asr Rm1, Rn1, Rm2, Rn2
4919 
8.0xf7+8.0x80+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asr
4920 
"add_asr"
4921 
*am33
4922 
{
4923 
  int srcreg1, srcreg2, dstreg1, dstreg2;
4924 
  int result1;
4925 
  signed int temp;
4926 
 
4927 
  PC = cia;
4928 
  srcreg1 = translate_rreg (SD_, RM1);
4929 
  srcreg2 = translate_rreg (SD_, RM2);
4930 
  dstreg1 = translate_rreg (SD_, RN1);
4931 
  dstreg2 = translate_rreg (SD_, RN2);
4932 
 
4933 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4934 
  temp = State.regs[dstreg2];
4935 
  temp >>= State.regs[srcreg2];
4936 
  State.regs[dstreg2] = temp;
4937 
  State.regs[dstreg1] = result1;
4938 
}
4939 
 
4940 
// 1111 0111 1001 0000 Rm1 Rn1 imm4 Rn2; add_asr Rm1, Rn1, imm4, Rn2
4941 
8.0xf7+8.0x90+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asr
4942 
"add_asr"
4943 
*am33
4944 
{
4945 
  int srcreg1, dstreg1, dstreg2;
4946 
  int result1;
4947 
  signed int temp;
4948 
 
4949 
  PC = cia;
4950 
  srcreg1 = translate_rreg (SD_, RM1);
4951 
  dstreg1 = translate_rreg (SD_, RN1);
4952 
  dstreg2 = translate_rreg (SD_, RN2);
4953 
 
4954 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4955 
  temp = State.regs[dstreg2];
4956 
  temp >>= IMM4;
4957 
  State.regs[dstreg2] = temp;
4958 
  State.regs[dstreg1] = result1;
4959 
}
4960 
 
4961 
// 1111 0111 1010 0000 Rm1 Rn1 Rm2 Rn2; add_lsr Rm1, Rn1, Rm2, Rn2
4962 
8.0xf7+8.0xa0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_lsr
4963 
"add_lsr"
4964 
*am33
4965 
{
4966 
  int srcreg1, srcreg2, dstreg1, dstreg2;
4967 
  int result1;
4968 
 
4969 
  PC = cia;
4970 
  srcreg1 = translate_rreg (SD_, RM1);
4971 
  srcreg2 = translate_rreg (SD_, RM2);
4972 
  dstreg1 = translate_rreg (SD_, RN1);
4973 
  dstreg2 = translate_rreg (SD_, RN2);
4974 
 
4975 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4976 
  State.regs[dstreg2] >>= State.regs[srcreg2];
4977 
  State.regs[dstreg1] = result1;
4978 
}
4979 
 
4980 
// 1111 0111 1011 0000 Rm1 Rn1 imm4 Rn2; add_lsr Rm1, Rn1, imm4, Rn2
4981 
8.0xf7+8.0xb0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_lsr
4982 
"add_lsr"
4983 
*am33
4984 
{
4985 
  int srcreg1, dstreg1, dstreg2;
4986 
  int result1;
4987 
  signed int temp;
4988 
 
4989 
  PC = cia;
4990 
  srcreg1 = translate_rreg (SD_, RM1);
4991 
  dstreg1 = translate_rreg (SD_, RN1);
4992 
  dstreg2 = translate_rreg (SD_, RN2);
4993 
 
4994 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
4995 
  State.regs[dstreg2] >>= IMM4;
4996 
  State.regs[dstreg1] = result1;
4997 
}
4998 
 
4999 
 
5000 
// 1111 0111 1100 0000 Rm1 Rn1 Rm2 Rn2; add_asl Rm1, Rn1, Rm2, Rn2
5001 
8.0xf7+8.0xc0+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::add_asl
5002 
"add_asl"
5003 
*am33
5004 
{
5005 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5006 
  int result1;
5007 
 
5008 
  PC = cia;
5009 
  srcreg1 = translate_rreg (SD_, RM1);
5010 
  srcreg2 = translate_rreg (SD_, RM2);
5011 
  dstreg1 = translate_rreg (SD_, RN1);
5012 
  dstreg2 = translate_rreg (SD_, RN2);
5013 
 
5014 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
5015 
  State.regs[dstreg2] <<= State.regs[srcreg2];
5016 
  State.regs[dstreg1] = result1;
5017 
}
5018 
 
5019 
// 1111 0111 1101 0000 Rm1 Rn1 imm4 Rn2; add_asl Rm1, Rn1, imm4, Rn2
5020 
8.0xf7+8.0xd0+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::add_asl
5021 
"add_asl"
5022 
*am33
5023 
{
5024 
  int srcreg1, dstreg1, dstreg2;
5025 
  int result1;
5026 
  signed int temp;
5027 
 
5028 
  PC = cia;
5029 
  srcreg1 = translate_rreg (SD_, RM1);
5030 
  dstreg1 = translate_rreg (SD_, RN1);
5031 
  dstreg2 = translate_rreg (SD_, RN2);
5032 
 
5033 
  result1 = State.regs[dstreg1] + State.regs[srcreg1];
5034 
  State.regs[dstreg2] <<= IMM4;
5035 
  State.regs[dstreg1] = result1;
5036 
}
5037 
 
5038 
// 1111 0111 0000 0001 Rm1 Rn1 Rm2 Rn2; cmp_add Rm1, Rn1, Rm2, Rn2
5039 
8.0xf7+8.0x01+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_add
5040 
"cmp_add"
5041 
*am33
5042 
{
5043 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5044 
 
5045 
  PC = cia;
5046 
  srcreg1 = translate_rreg (SD_, RM1);
5047 
  srcreg2 = translate_rreg (SD_, RM2);
5048 
  dstreg1 = translate_rreg (SD_, RN1);
5049 
  dstreg2 = translate_rreg (SD_, RN2);
5050 
 
5051 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5052 
  State.regs[dstreg2] += State.regs[srcreg2];
5053 
}
5054 
 
5055 
// 1111 0111 0001 0001 Rm1 Rn1 imm4 Rn2; cmp_add Rm1, Rn1, imm4, Rn2
5056 
8.0xf7+8.0x11+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_add
5057 
"cmp_add"
5058 
*am33
5059 
{
5060 
  int srcreg1, dstreg1, dstreg2;
5061 
 
5062 
  PC = cia;
5063 
  srcreg1 = translate_rreg (SD_, RM1);
5064 
  dstreg1 = translate_rreg (SD_, RN1);
5065 
  dstreg2 = translate_rreg (SD_, RN2);
5066 
 
5067 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5068 
  State.regs[dstreg2] += EXTEND4 (IMM4);
5069 
}
5070 
 
5071 
// 1111 0111 0010 0001 Rm1 Rn1 Rm2 Rn2; cmp_sub Rm1, Rn1, Rm2, Rn2
5072 
8.0xf7+8.0x21+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_sub
5073 
"cmp_sub"
5074 
*am33
5075 
{
5076 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5077 
 
5078 
  PC = cia;
5079 
  srcreg1 = translate_rreg (SD_, RM1);
5080 
  srcreg2 = translate_rreg (SD_, RM2);
5081 
  dstreg1 = translate_rreg (SD_, RN1);
5082 
  dstreg2 = translate_rreg (SD_, RN2);
5083 
 
5084 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5085 
  State.regs[dstreg2] -= State.regs[srcreg2];
5086 
}
5087 
 
5088 
// 1111 0111 0011 0001 Rm1 Rn1 imm4 Rn2; cmp_sub Rm1, Rn1, imm4, Rn2
5089 
8.0xf7+8.0x31+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_sub
5090 
"cmp_sub"
5091 
*am33
5092 
{
5093 
  int srcreg1, dstreg1, dstreg2;
5094 
 
5095 
  PC = cia;
5096 
  srcreg1 = translate_rreg (SD_, RM1);
5097 
  dstreg1 = translate_rreg (SD_, RN1);
5098 
  dstreg2 = translate_rreg (SD_, RN2);
5099 
 
5100 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5101 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
5102 
}
5103 
 
5104 
// 1111 0111 0110 0001 Rm1 Rn1 Rm2 Rn2; cmp_mov Rm1, Rn1, Rm2, Rn2
5105 
8.0xf7+8.0x61+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_mov
5106 
"cmp_mov"
5107 
*am33
5108 
{
5109 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5110 
 
5111 
  PC = cia;
5112 
  srcreg1 = translate_rreg (SD_, RM1);
5113 
  srcreg2 = translate_rreg (SD_, RM2);
5114 
  dstreg1 = translate_rreg (SD_, RN1);
5115 
  dstreg2 = translate_rreg (SD_, RN2);
5116 
 
5117 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5118 
  State.regs[dstreg2] = State.regs[srcreg2];
5119 
}
5120 
 
5121 
// 1111 0111 0111 0001 Rm1 Rn1 imm4 Rn2; cmp_mov Rm1, Rn1, imm4, Rn2
5122 
8.0xf7+8.0x71+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_mov
5123 
"cmp_mov"
5124 
*am33
5125 
{
5126 
  int srcreg1, dstreg1, dstreg2;
5127 
 
5128 
  PC = cia;
5129 
  srcreg1 = translate_rreg (SD_, RM1);
5130 
  dstreg1 = translate_rreg (SD_, RN1);
5131 
  dstreg2 = translate_rreg (SD_, RN2);
5132 
 
5133 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5134 
  State.regs[dstreg2] = EXTEND4 (IMM4);
5135 
}
5136 
 
5137 
// 1111 0111 1000 0001 Rm1 Rn1 Rm2 Rn2; cmp_asr Rm1, Rn1, Rm2, Rn2
5138 
8.0xf7+8.0x81+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asr
5139 
"cmp_asr"
5140 
*am33
5141 
{
5142 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5143 
  signed int temp;
5144 
 
5145 
  PC = cia;
5146 
  srcreg1 = translate_rreg (SD_, RM1);
5147 
  srcreg2 = translate_rreg (SD_, RM2);
5148 
  dstreg1 = translate_rreg (SD_, RN1);
5149 
  dstreg2 = translate_rreg (SD_, RN2);
5150 
 
5151 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5152 
  temp = State.regs[dstreg2];
5153 
  temp >>= State.regs[srcreg2];
5154 
  State.regs[dstreg2] = temp;
5155 
}
5156 
 
5157 
// 1111 0111 1001 0001 Rm1 Rn1 imm4 Rn2; cmp_asr Rm1, Rn1, imm4, Rn2
5158 
8.0xf7+8.0x91+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asr
5159 
"cmp_asr"
5160 
*am33
5161 
{
5162 
  int srcreg1, dstreg1, dstreg2;
5163 
  signed int temp;
5164 
 
5165 
  PC = cia;
5166 
  srcreg1 = translate_rreg (SD_, RM1);
5167 
  dstreg1 = translate_rreg (SD_, RN1);
5168 
  dstreg2 = translate_rreg (SD_, RN2);
5169 
 
5170 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5171 
  temp = State.regs[dstreg2];
5172 
  temp >>= IMM4;
5173 
  State.regs[dstreg2] = temp;
5174 
}
5175 
 
5176 
// 1111 0111 1010 0001 Rm1 Rn1 Rm2 Rn2; cmp_lsr Rm1, Rn1, Rm2, Rn2
5177 
8.0xf7+8.0xa1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_lsr
5178 
"cmp_lsr"
5179 
*am33
5180 
{
5181 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5182 
 
5183 
  PC = cia;
5184 
  srcreg1 = translate_rreg (SD_, RM1);
5185 
  srcreg2 = translate_rreg (SD_, RM2);
5186 
  dstreg1 = translate_rreg (SD_, RN1);
5187 
  dstreg2 = translate_rreg (SD_, RN2);
5188 
 
5189 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5190 
  State.regs[dstreg2] >>= State.regs[srcreg2];
5191 
}
5192 
 
5193 
// 1111 0111 1011 0001 Rm1 Rn1 imm4 Rn2; cmp_lsr Rm1, Rn1, imm4, Rn2
5194 
8.0xf7+8.0xb1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_lsr
5195 
"cmp_lsr"
5196 
*am33
5197 
{
5198 
  int srcreg1, dstreg1, dstreg2;
5199 
  signed int temp;
5200 
 
5201 
  PC = cia;
5202 
  srcreg1 = translate_rreg (SD_, RM1);
5203 
  dstreg1 = translate_rreg (SD_, RN1);
5204 
  dstreg2 = translate_rreg (SD_, RN2);
5205 
 
5206 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5207 
  State.regs[dstreg2] >>= IMM4;
5208 
}
5209 
 
5210 
 
5211 
// 1111 0111 1100 0001 Rm1 Rn1 Rm2 Rn2; cmp_asl Rm1, Rn1, Rm2, Rn2
5212 
8.0xf7+8.0xc1+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::cmp_asl
5213 
"cmp_asl"
5214 
*am33
5215 
{
5216 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5217 
 
5218 
  PC = cia;
5219 
  srcreg1 = translate_rreg (SD_, RM1);
5220 
  srcreg2 = translate_rreg (SD_, RM2);
5221 
  dstreg1 = translate_rreg (SD_, RN1);
5222 
  dstreg2 = translate_rreg (SD_, RN2);
5223 
 
5224 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5225 
  State.regs[dstreg2] <<= State.regs[srcreg2];
5226 
}
5227 
 
5228 
// 1111 0111 1101 0001 Rm1 Rn1 imm4 Rn2; cmp_asl Rm1, Rn1, imm4, Rn2
5229 
8.0xf7+8.0xd1+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::cmp_asl
5230 
"cmp_asl"
5231 
*am33
5232 
{
5233 
  int srcreg1, dstreg1, dstreg2;
5234 
  signed int temp;
5235 
 
5236 
  PC = cia;
5237 
  srcreg1 = translate_rreg (SD_, RM1);
5238 
  dstreg1 = translate_rreg (SD_, RN1);
5239 
  dstreg2 = translate_rreg (SD_, RN2);
5240 
 
5241 
  genericCmp (State.regs[srcreg1], State.regs[dstreg1]);
5242 
  State.regs[dstreg2] <<= IMM4;
5243 
}
5244 
 
5245 
// 1111 0111 0000 0010 Rm1 Rn1 Rm2 Rn2; sub_add Rm1, Rn1, Rm2, Rn2
5246 
8.0xf7+8.0x02+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_add
5247 
"sub_add"
5248 
*am33
5249 
{
5250 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5251 
  int result1;
5252 
 
5253 
  PC = cia;
5254 
  srcreg1 = translate_rreg (SD_, RM1);
5255 
  srcreg2 = translate_rreg (SD_, RM2);
5256 
  dstreg1 = translate_rreg (SD_, RN1);
5257 
  dstreg2 = translate_rreg (SD_, RN2);
5258 
 
5259 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5260 
  State.regs[dstreg2] += State.regs[srcreg2];
5261 
  State.regs[dstreg1] = result1;
5262 
}
5263 
 
5264 
// 1111 0111 0001 0010 Rm1 Rn1 imm4 Rn2; sub_add Rm1, Rn1, imm4, Rn2
5265 
8.0xf7+8.0x12+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_add
5266 
"sub_add"
5267 
*am33
5268 
{
5269 
  int srcreg1, dstreg1, dstreg2;
5270 
  int result1;
5271 
 
5272 
  PC = cia;
5273 
  srcreg1 = translate_rreg (SD_, RM1);
5274 
  dstreg1 = translate_rreg (SD_, RN1);
5275 
  dstreg2 = translate_rreg (SD_, RN2);
5276 
 
5277 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5278 
  State.regs[dstreg2] += EXTEND4 (IMM4);
5279 
  State.regs[dstreg1] = result1;
5280 
}
5281 
 
5282 
// 1111 0111 0010 0010 Rm1 Rn1 Rm2 Rn2; sub_sub Rm1, Rn1, Rm2, Rn2
5283 
8.0xf7+8.0x22+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_sub
5284 
"sub_sub"
5285 
*am33
5286 
{
5287 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5288 
  int result1;
5289 
 
5290 
  PC = cia;
5291 
  srcreg1 = translate_rreg (SD_, RM1);
5292 
  srcreg2 = translate_rreg (SD_, RM2);
5293 
  dstreg1 = translate_rreg (SD_, RN1);
5294 
  dstreg2 = translate_rreg (SD_, RN2);
5295 
 
5296 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5297 
  State.regs[dstreg2] -= State.regs[srcreg2];
5298 
  State.regs[dstreg1] = result1;
5299 
}
5300 
 
5301 
// 1111 0111 0011 0010 Rm1 Rn1 imm4 Rn2; sub_sub Rm1, Rn1, imm4, Rn2
5302 
8.0xf7+8.0x32+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_sub
5303 
"sub_sub"
5304 
*am33
5305 
{
5306 
  int srcreg1, dstreg1, dstreg2;
5307 
  int result1;
5308 
 
5309 
  PC = cia;
5310 
  srcreg1 = translate_rreg (SD_, RM1);
5311 
  dstreg1 = translate_rreg (SD_, RN1);
5312 
  dstreg2 = translate_rreg (SD_, RN2);
5313 
 
5314 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5315 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
5316 
  State.regs[dstreg1] = result1;
5317 
}
5318 
 
5319 
// 1111 0111 0100 0010 Rm1 Rn1 Rm2 Rn2; sub_cmp Rm1, Rn1, Rm2, Rn2
5320 
8.0xf7+8.0x42+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_cmp
5321 
"sub_cmp"
5322 
*am33
5323 
{
5324 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5325 
 
5326 
  PC = cia;
5327 
  srcreg1 = translate_rreg (SD_, RM1);
5328 
  srcreg2 = translate_rreg (SD_, RM2);
5329 
  dstreg1 = translate_rreg (SD_, RN1);
5330 
  dstreg2 = translate_rreg (SD_, RN2);
5331 
 
5332 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5333 
  State.regs[dstreg1] -= State.regs[srcreg1];
5334 
}
5335 
 
5336 
// 1111 0111 0101 0010 Rm1 Rn1 imm4 Rn2; sub_cmp Rm1, Rn1, imm4, Rn2
5337 
8.0xf7+8.0x52+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_cmp
5338 
"sub_cmp"
5339 
*am33
5340 
{
5341 
  int srcreg1, dstreg1, dstreg2;
5342 
  int result1;
5343 
 
5344 
  PC = cia;
5345 
  srcreg1 = translate_rreg (SD_, RM1);
5346 
  dstreg1 = translate_rreg (SD_, RN1);
5347 
  dstreg2 = translate_rreg (SD_, RN2);
5348 
 
5349 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5350 
  State.regs[dstreg1] -= State.regs[srcreg1];
5351 
}
5352 
 
5353 
// 1111 0111 0110 0010 Rm1 Rn1 Rm2 Rn2; sub_mov Rm1, Rn1, Rm2, Rn2
5354 
8.0xf7+8.0x62+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_mov
5355 
"sub_mov"
5356 
*am33
5357 
{
5358 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5359 
  int result1;
5360 
 
5361 
  PC = cia;
5362 
  srcreg1 = translate_rreg (SD_, RM1);
5363 
  srcreg2 = translate_rreg (SD_, RM2);
5364 
  dstreg1 = translate_rreg (SD_, RN1);
5365 
  dstreg2 = translate_rreg (SD_, RN2);
5366 
 
5367 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5368 
  State.regs[dstreg2] = State.regs[srcreg2];
5369 
  State.regs[dstreg1] = result1;
5370 
}
5371 
 
5372 
// 1111 0111 0111 0010 Rm1 Rn1 imm4 Rn2; sub_mov Rm1, Rn1, imm4, Rn2
5373 
8.0xf7+8.0x72+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_mov
5374 
"sub_mov"
5375 
*am33
5376 
{
5377 
  int srcreg1, dstreg1, dstreg2;
5378 
  int result1;
5379 
 
5380 
  PC = cia;
5381 
  srcreg1 = translate_rreg (SD_, RM1);
5382 
  dstreg1 = translate_rreg (SD_, RN1);
5383 
  dstreg2 = translate_rreg (SD_, RN2);
5384 
 
5385 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5386 
  State.regs[dstreg2] = EXTEND4 (IMM4);
5387 
  State.regs[dstreg1] = result1;
5388 
}
5389 
 
5390 
// 1111 0111 1000 0010 Rm1 Rn1 Rm2 Rn2; sub_asr Rm1, Rn1, Rm2, Rn2
5391 
8.0xf7+8.0x82+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asr
5392 
"sub_asr"
5393 
*am33
5394 
{
5395 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5396 
  int result1;
5397 
  signed int temp;
5398 
 
5399 
  PC = cia;
5400 
  srcreg1 = translate_rreg (SD_, RM1);
5401 
  srcreg2 = translate_rreg (SD_, RM2);
5402 
  dstreg1 = translate_rreg (SD_, RN1);
5403 
  dstreg2 = translate_rreg (SD_, RN2);
5404 
 
5405 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5406 
  temp = State.regs[dstreg2];
5407 
  temp >>= State.regs[srcreg2];
5408 
  State.regs[dstreg2] = temp;
5409 
  State.regs[dstreg1] = result1;
5410 
}
5411 
 
5412 
// 1111 0111 1001 0010 Rm1 Rn1 imm4 Rn2; sub_asr Rm1, Rn1, imm4, Rn2
5413 
8.0xf7+8.0x92+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asr
5414 
"sub_asr"
5415 
*am33
5416 
{
5417 
  int srcreg1, dstreg1, dstreg2;
5418 
  int result1;
5419 
  signed int temp;
5420 
 
5421 
  PC = cia;
5422 
  srcreg1 = translate_rreg (SD_, RM1);
5423 
  dstreg1 = translate_rreg (SD_, RN1);
5424 
  dstreg2 = translate_rreg (SD_, RN2);
5425 
 
5426 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5427 
  temp = State.regs[dstreg2];
5428 
  temp >>= IMM4;
5429 
  State.regs[dstreg2] = temp;
5430 
  State.regs[dstreg1] = result1;
5431 
}
5432 
 
5433 
// 1111 0111 1010 0010 Rm1 Rn1 Rm2 Rn2; sub_lsr Rm1, Rn1, Rm2, Rn2
5434 
8.0xf7+8.0xa2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_lsr
5435 
"sub_lsr"
5436 
*am33
5437 
{
5438 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5439 
  int result1;
5440 
 
5441 
  PC = cia;
5442 
  srcreg1 = translate_rreg (SD_, RM1);
5443 
  srcreg2 = translate_rreg (SD_, RM2);
5444 
  dstreg1 = translate_rreg (SD_, RN1);
5445 
  dstreg2 = translate_rreg (SD_, RN2);
5446 
 
5447 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5448 
  State.regs[dstreg2] >>= State.regs[srcreg2];
5449 
  State.regs[dstreg1] = result1;
5450 
}
5451 
 
5452 
// 1111 0111 1011 0010 Rm1 Rn1 imm4 Rn2; sub_lsr Rm1, Rn1, imm4, Rn2
5453 
8.0xf7+8.0xb2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_lsr
5454 
"sub_lsr"
5455 
*am33
5456 
{
5457 
  int srcreg1, dstreg1, dstreg2;
5458 
  int result1;
5459 
  signed int temp;
5460 
 
5461 
  PC = cia;
5462 
  srcreg1 = translate_rreg (SD_, RM1);
5463 
  dstreg1 = translate_rreg (SD_, RN1);
5464 
  dstreg2 = translate_rreg (SD_, RN2);
5465 
 
5466 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5467 
  State.regs[dstreg2] >>= IMM4;
5468 
  State.regs[dstreg1] = result1;
5469 
}
5470 
 
5471 
 
5472 
// 1111 0111 1100 0010 Rm1 Rn1 Rm2 Rn2; sub_asl Rm1, Rn1, Rm2, Rn2
5473 
8.0xf7+8.0xc2+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sub_asl
5474 
"sub_asl"
5475 
*am33
5476 
{
5477 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5478 
  int result1;
5479 
 
5480 
  PC = cia;
5481 
  srcreg1 = translate_rreg (SD_, RM1);
5482 
  srcreg2 = translate_rreg (SD_, RM2);
5483 
  dstreg1 = translate_rreg (SD_, RN1);
5484 
  dstreg2 = translate_rreg (SD_, RN2);
5485 
 
5486 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5487 
  State.regs[dstreg2] <<= State.regs[srcreg2];
5488 
  State.regs[dstreg1] = result1;
5489 
}
5490 
 
5491 
// 1111 0111 1101 0010 Rm1 Rn1 imm4 Rn2; sub_asl Rm1, Rn1, imm4, Rn2
5492 
8.0xf7+8.0xd2+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sub_asl
5493 
"sub_asl"
5494 
*am33
5495 
{
5496 
  int srcreg1, dstreg1, dstreg2;
5497 
  int result1;
5498 
  signed int temp;
5499 
 
5500 
  PC = cia;
5501 
  srcreg1 = translate_rreg (SD_, RM1);
5502 
  dstreg1 = translate_rreg (SD_, RN1);
5503 
  dstreg2 = translate_rreg (SD_, RN2);
5504 
 
5505 
  result1 = State.regs[dstreg1] - State.regs[srcreg1];
5506 
  State.regs[dstreg2] <<= IMM4;
5507 
  State.regs[dstreg1] = result1;
5508 
}
5509 
 
5510 
// 1111 0111 0000 0011 Rm1 Rn1 Rm2 Rn2; mov_add Rm1, Rn1, Rm2, Rn2
5511 
8.0xf7+8.0x03+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_add
5512 
"mov_add"
5513 
*am33
5514 
{
5515 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5516 
  int result1;
5517 
 
5518 
  PC = cia;
5519 
  srcreg1 = translate_rreg (SD_, RM1);
5520 
  srcreg2 = translate_rreg (SD_, RM2);
5521 
  dstreg1 = translate_rreg (SD_, RN1);
5522 
  dstreg2 = translate_rreg (SD_, RN2);
5523 
 
5524 
  result1 = State.regs[srcreg1];
5525 
  State.regs[dstreg2] += State.regs[srcreg2];
5526 
  State.regs[dstreg1] = result1;
5527 
}
5528 
 
5529 
// 1111 0111 0001 0011 Rm1 Rn1 imm4 Rn2; mov_add Rm1, Rn1, imm4, Rn2
5530 
8.0xf7+8.0x13+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_add
5531 
"mov_add"
5532 
*am33
5533 
{
5534 
  int srcreg1, dstreg1, dstreg2;
5535 
  int result1;
5536 
 
5537 
  PC = cia;
5538 
  srcreg1 = translate_rreg (SD_, RM1);
5539 
  dstreg1 = translate_rreg (SD_, RN1);
5540 
  dstreg2 = translate_rreg (SD_, RN2);
5541 
 
5542 
  result1 = State.regs[srcreg1];
5543 
  State.regs[dstreg2] += EXTEND4 (IMM4);
5544 
  State.regs[dstreg1] = result1;
5545 
}
5546 
 
5547 
// 1111 0111 0010 0011 Rm1 Rn1 Rm2 Rn2; mov_sub Rm1, Rn1, Rm2, Rn2
5548 
8.0xf7+8.0x23+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_sub
5549 
"mov_sub"
5550 
*am33
5551 
{
5552 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5553 
  int result1;
5554 
 
5555 
  PC = cia;
5556 
  srcreg1 = translate_rreg (SD_, RM1);
5557 
  srcreg2 = translate_rreg (SD_, RM2);
5558 
  dstreg1 = translate_rreg (SD_, RN1);
5559 
  dstreg2 = translate_rreg (SD_, RN2);
5560 
 
5561 
  result1 = State.regs[srcreg1];
5562 
  State.regs[dstreg2] -= State.regs[srcreg2];
5563 
  State.regs[dstreg1] = result1;
5564 
}
5565 
 
5566 
// 1111 0111 0011 0011 Rm1 Rn1 imm4 Rn2; mov_sub Rm1, Rn1, imm4, Rn2
5567 
8.0xf7+8.0x33+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_sub
5568 
"mov_sub"
5569 
*am33
5570 
{
5571 
  int srcreg1, dstreg1, dstreg2;
5572 
  int result1;
5573 
 
5574 
  PC = cia;
5575 
  srcreg1 = translate_rreg (SD_, RM1);
5576 
  dstreg1 = translate_rreg (SD_, RN1);
5577 
  dstreg2 = translate_rreg (SD_, RN2);
5578 
 
5579 
  result1 = State.regs[srcreg1];
5580 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
5581 
  State.regs[dstreg1] = result1;
5582 
}
5583 
 
5584 
// 1111 0111 0100 0011 Rm1 Rn1 Rm2 Rn2; mov_cmp Rm1, Rn1, Rm2, Rn2
5585 
8.0xf7+8.0x43+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_cmp
5586 
"mov_cmp"
5587 
*am33
5588 
{
5589 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5590 
 
5591 
  PC = cia;
5592 
  srcreg1 = translate_rreg (SD_, RM1);
5593 
  srcreg2 = translate_rreg (SD_, RM2);
5594 
  dstreg1 = translate_rreg (SD_, RN1);
5595 
  dstreg2 = translate_rreg (SD_, RN2);
5596 
 
5597 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5598 
  State.regs[dstreg1] = State.regs[srcreg1];
5599 
}
5600 
 
5601 
// 1111 0111 0101 0011 Rm1 Rn1 imm4 Rn2; mov_cmp Rm1, Rn1, imm4, Rn2
5602 
8.0xf7+8.0x53+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_cmp
5603 
"mov_cmp"
5604 
*am33
5605 
{
5606 
  int srcreg1, dstreg1, dstreg2;
5607 
 
5608 
  PC = cia;
5609 
  srcreg1 = translate_rreg (SD_, RM1);
5610 
  dstreg1 = translate_rreg (SD_, RN1);
5611 
  dstreg2 = translate_rreg (SD_, RN2);
5612 
 
5613 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5614 
  State.regs[dstreg1] = State.regs[srcreg1];
5615 
}
5616 
 
5617 
// 1111 0111 0110 0011 Rm1 Rn1 Rm2 Rn2; mov_mov Rm1, Rn1, Rm2, Rn2
5618 
8.0xf7+8.0x63+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_mov
5619 
"mov_mov"
5620 
*am33
5621 
{
5622 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5623 
  int result1;
5624 
 
5625 
  PC = cia;
5626 
  srcreg1 = translate_rreg (SD_, RM1);
5627 
  srcreg2 = translate_rreg (SD_, RM2);
5628 
  dstreg1 = translate_rreg (SD_, RN1);
5629 
  dstreg2 = translate_rreg (SD_, RN2);
5630 
 
5631 
  result1 = State.regs[srcreg1];
5632 
  State.regs[dstreg2] = State.regs[srcreg2];
5633 
  State.regs[dstreg1] = result1;
5634 
}
5635 
 
5636 
// 1111 0111 0111 0011 Rm1 Rn1 imm4 Rn2; mov_mov Rm1, Rn1, imm4, Rn2
5637 
8.0xf7+8.0x73+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_mov
5638 
"mov_mov"
5639 
*am33
5640 
{
5641 
  int srcreg1, dstreg1, dstreg2;
5642 
  int result1;
5643 
 
5644 
  PC = cia;
5645 
  srcreg1 = translate_rreg (SD_, RM1);
5646 
  dstreg1 = translate_rreg (SD_, RN1);
5647 
  dstreg2 = translate_rreg (SD_, RN2);
5648 
 
5649 
  result1 = State.regs[srcreg1];
5650 
  State.regs[dstreg2] = EXTEND4 (IMM4);
5651 
  State.regs[dstreg1] = result1;
5652 
}
5653 
 
5654 
// 1111 0111 1000 0011 Rm1 Rn1 Rm2 Rn2; mov_asr Rm1, Rn1, Rm2, Rn2
5655 
8.0xf7+8.0x83+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asr
5656 
"mov_asr"
5657 
*am33
5658 
{
5659 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5660 
  int result1;
5661 
  signed int temp;
5662 
 
5663 
  PC = cia;
5664 
  srcreg1 = translate_rreg (SD_, RM1);
5665 
  srcreg2 = translate_rreg (SD_, RM2);
5666 
  dstreg1 = translate_rreg (SD_, RN1);
5667 
  dstreg2 = translate_rreg (SD_, RN2);
5668 
 
5669 
  result1 = State.regs[srcreg1];
5670 
  temp = State.regs[dstreg2];
5671 
  temp >>= State.regs[srcreg2];
5672 
  State.regs[dstreg2] = temp;
5673 
  State.regs[dstreg1] = result1;
5674 
}
5675 
 
5676 
// 1111 0111 1001 0011 Rm1 Rn1 imm4 Rn2; mov_asr Rm1, Rn1, imm4, Rn2
5677 
8.0xf7+8.0x93+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asr
5678 
"mov_asr"
5679 
*am33
5680 
{
5681 
  int srcreg1, dstreg1, dstreg2;
5682 
  int result1;
5683 
  signed int temp;
5684 
 
5685 
  PC = cia;
5686 
  srcreg1 = translate_rreg (SD_, RM1);
5687 
  dstreg1 = translate_rreg (SD_, RN1);
5688 
  dstreg2 = translate_rreg (SD_, RN2);
5689 
 
5690 
  result1 = State.regs[srcreg1];
5691 
  temp = State.regs[dstreg2];
5692 
  temp >>= IMM4;
5693 
  State.regs[dstreg2] = temp;
5694 
  State.regs[dstreg1] = result1;
5695 
}
5696 
 
5697 
// 1111 0111 1010 0011 Rm1 Rn1 Rm2 Rn2; mov_lsr Rm1, Rn1, Rm2, Rn2
5698 
8.0xf7+8.0xa3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_lsr
5699 
"mov_lsr"
5700 
*am33
5701 
{
5702 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5703 
  int result1;
5704 
 
5705 
  PC = cia;
5706 
  srcreg1 = translate_rreg (SD_, RM1);
5707 
  srcreg2 = translate_rreg (SD_, RM2);
5708 
  dstreg1 = translate_rreg (SD_, RN1);
5709 
  dstreg2 = translate_rreg (SD_, RN2);
5710 
 
5711 
  result1 = State.regs[srcreg1];
5712 
  State.regs[dstreg2] >>= State.regs[srcreg2];
5713 
  State.regs[dstreg1] = result1;
5714 
}
5715 
 
5716 
// 1111 0111 1011 0011 Rm1 Rn1 imm4 Rn2; mov_lsr Rm1, Rn1, imm4, Rn2
5717 
8.0xf7+8.0xb3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_lsr
5718 
"mov_lsr"
5719 
*am33
5720 
{
5721 
  int srcreg1, dstreg1, dstreg2;
5722 
  int result1;
5723 
  signed int temp;
5724 
 
5725 
  PC = cia;
5726 
  srcreg1 = translate_rreg (SD_, RM1);
5727 
  dstreg1 = translate_rreg (SD_, RN1);
5728 
  dstreg2 = translate_rreg (SD_, RN2);
5729 
 
5730 
  result1 = State.regs[srcreg1];
5731 
  State.regs[dstreg2] >>= IMM4;
5732 
  State.regs[dstreg1] = result1;
5733 
}
5734 
 
5735 
 
5736 
// 1111 0111 1100 0011 Rm1 Rn1 Rm2 Rn2; mov_asl Rm1, Rn1, Rm2, Rn2
5737 
8.0xf7+8.0xc3+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::mov_asl
5738 
"mov_asl"
5739 
*am33
5740 
{
5741 
  int srcreg1, srcreg2, dstreg1, dstreg2;
5742 
  int result1;
5743 
 
5744 
  PC = cia;
5745 
  srcreg1 = translate_rreg (SD_, RM1);
5746 
  srcreg2 = translate_rreg (SD_, RM2);
5747 
  dstreg1 = translate_rreg (SD_, RN1);
5748 
  dstreg2 = translate_rreg (SD_, RN2);
5749 
 
5750 
  result1 = State.regs[srcreg1];
5751 
  State.regs[dstreg2] <<= State.regs[srcreg2];
5752 
  State.regs[dstreg1] = result1;
5753 
}
5754 
 
5755 
// 1111 0111 1101 0011 Rm1 Rn1 imm4 Rn2; mov_asl Rm1, Rn1, imm4, Rn2
5756 
8.0xf7+8.0xd3+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::mov_asl
5757 
"mov_asl"
5758 
*am33
5759 
{
5760 
  int srcreg1, dstreg1, dstreg2;
5761 
  int result1;
5762 
  signed int temp;
5763 
 
5764 
  PC = cia;
5765 
  srcreg1 = translate_rreg (SD_, RM1);
5766 
  dstreg1 = translate_rreg (SD_, RN1);
5767 
  dstreg2 = translate_rreg (SD_, RN2);
5768 
 
5769 
  result1 = State.regs[srcreg1];
5770 
  State.regs[dstreg2] <<= IMM4;
5771 
  State.regs[dstreg1] = result1;
5772 
}
5773 
 
5774 
// 1111 0111 0000 0100 imm4 Rn1 Rm2 Rn2; add_add imm4, Rn1, Rm2, Rn2
5775 
8.0xf7+8.0x04+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_add
5776 
"add_add"
5777 
*am33
5778 
{
5779 
  int srcreg2, dstreg1, dstreg2;
5780 
  int result1;
5781 
 
5782 
  PC = cia;
5783 
  srcreg2 = translate_rreg (SD_, RM2);
5784 
  dstreg1 = translate_rreg (SD_, RN1);
5785 
  dstreg2 = translate_rreg (SD_, RN2);
5786 
 
5787 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5788 
  State.regs[dstreg2] += State.regs[srcreg2];
5789 
  State.regs[dstreg1] = result1;
5790 
}
5791 
 
5792 
// 1111 0111 0001 0100 imm4 Rn1 imm4 Rn2; add_add imm4, Rn1, imm4, Rn2
5793 
8.0xf7+8.0x14+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_add
5794 
"add_add"
5795 
*am33
5796 
{
5797 
  int dstreg1, dstreg2;
5798 
  int result1;
5799 
 
5800 
  PC = cia;
5801 
  dstreg1 = translate_rreg (SD_, RN1);
5802 
  dstreg2 = translate_rreg (SD_, RN2);
5803 
 
5804 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5805 
  State.regs[dstreg2] += EXTEND4 (IMM4);
5806 
  State.regs[dstreg1] = result1;
5807 
}
5808 
 
5809 
// 1111 0111 0010 0100 imm4 Rn1 Rm2 Rn2; add_sub imm4, Rn1, Rm2, Rn2
5810 
8.0xf7+8.0x24+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_sub
5811 
"add_sub"
5812 
*am33
5813 
{
5814 
  int srcreg2, dstreg1, dstreg2;
5815 
  int result1;
5816 
 
5817 
  PC = cia;
5818 
  srcreg2 = translate_rreg (SD_, RM2);
5819 
  dstreg1 = translate_rreg (SD_, RN1);
5820 
  dstreg2 = translate_rreg (SD_, RN2);
5821 
 
5822 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5823 
  State.regs[dstreg2] -= State.regs[srcreg2];
5824 
  State.regs[dstreg1] = result1;
5825 
}
5826 
 
5827 
// 1111 0111 0011 0100 imm4 Rn1 imm4 Rn2; add_sub imm4, Rn1, imm4, Rn2
5828 
8.0xf7+8.0x34+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_sub
5829 
"add_sub"
5830 
*am33
5831 
{
5832 
  int dstreg1, dstreg2;
5833 
  int result1;
5834 
 
5835 
  PC = cia;
5836 
  dstreg1 = translate_rreg (SD_, RN1);
5837 
  dstreg2 = translate_rreg (SD_, RN2);
5838 
 
5839 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5840 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
5841 
  State.regs[dstreg1] = result1;
5842 
}
5843 
 
5844 
// 1111 0111 0100 0100 imm4 Rn1 Rm2 Rn2; add_cmp imm4, Rn1, Rm2, Rn2
5845 
8.0xf7+8.0x44+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_cmp
5846 
"add_cmp"
5847 
*am33
5848 
{
5849 
  int srcreg2, dstreg1, dstreg2;
5850 
 
5851 
  PC = cia;
5852 
  srcreg2 = translate_rreg (SD_, RM2);
5853 
  dstreg1 = translate_rreg (SD_, RN1);
5854 
  dstreg2 = translate_rreg (SD_, RN2);
5855 
 
5856 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
5857 
  State.regs[dstreg1] += EXTEND4 (IMM4A);
5858 
}
5859 
 
5860 
// 1111 0111 0101 0100 imm4 Rn1 imm4 Rn2; add_cmp imm4, Rn1, imm4, Rn2
5861 
8.0xf7+8.0x54+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_cmp
5862 
"add_cmp"
5863 
*am33
5864 
{
5865 
  int dstreg1, dstreg2;
5866 
 
5867 
  PC = cia;
5868 
  dstreg1 = translate_rreg (SD_, RN1);
5869 
  dstreg2 = translate_rreg (SD_, RN2);
5870 
 
5871 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
5872 
  State.regs[dstreg1] += EXTEND4 (IMM4A);
5873 
}
5874 
 
5875 
// 1111 0111 0110 0100 imm4 Rn1 Rm2 Rn2; add_mov imm4, Rn1, Rm2, Rn2
5876 
8.0xf7+8.0x64+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_mov
5877 
"add_mov"
5878 
*am33
5879 
{
5880 
  int srcreg2, dstreg1, dstreg2;
5881 
  int result1;
5882 
 
5883 
  PC = cia;
5884 
  srcreg2 = translate_rreg (SD_, RM2);
5885 
  dstreg1 = translate_rreg (SD_, RN1);
5886 
  dstreg2 = translate_rreg (SD_, RN2);
5887 
 
5888 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5889 
  State.regs[dstreg2] = State.regs[srcreg2];
5890 
  State.regs[dstreg1] = result1;
5891 
}
5892 
 
5893 
// 1111 0111 0111 0100 imm4 Rn1 imm4 Rn2; add_mov imm4, Rn1, imm4, Rn2
5894 
8.0xf7+8.0x74+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_mov
5895 
"add_mov"
5896 
*am33
5897 
{
5898 
  int dstreg1, dstreg2;
5899 
  int result1;
5900 
 
5901 
  PC = cia;
5902 
  dstreg1 = translate_rreg (SD_, RN1);
5903 
  dstreg2 = translate_rreg (SD_, RN2);
5904 
 
5905 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5906 
  State.regs[dstreg2] = EXTEND4 (IMM4);
5907 
  State.regs[dstreg1] = result1;
5908 
}
5909 
 
5910 
// 1111 0111 1000 0100 imm4 Rn1 Rm2 Rn2; add_asr imm4, Rn1, Rm2, Rn2
5911 
8.0xf7+8.0x84+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asr
5912 
"add_asr"
5913 
*am33
5914 
{
5915 
  int srcreg2, dstreg1, dstreg2;
5916 
  int result1;
5917 
  signed int temp;
5918 
 
5919 
  PC = cia;
5920 
  srcreg2 = translate_rreg (SD_, RM2);
5921 
  dstreg1 = translate_rreg (SD_, RN1);
5922 
  dstreg2 = translate_rreg (SD_, RN2);
5923 
 
5924 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5925 
  temp = State.regs[dstreg2];
5926 
  temp >>= State.regs[srcreg2];
5927 
  State.regs[dstreg2] = temp;
5928 
  State.regs[dstreg1] = result1;
5929 
}
5930 
 
5931 
// 1111 0111 1001 0100 imm4 Rn1 imm4 Rn2; add_asr imm4, Rn1, imm4, Rn2
5932 
8.0xf7+8.0x94+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asr
5933 
"add_asr"
5934 
*am33
5935 
{
5936 
  int dstreg1, dstreg2;
5937 
  int result1;
5938 
  signed int temp;
5939 
 
5940 
  PC = cia;
5941 
  dstreg1 = translate_rreg (SD_, RN1);
5942 
  dstreg2 = translate_rreg (SD_, RN2);
5943 
 
5944 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5945 
  temp = State.regs[dstreg2];
5946 
  temp >>= IMM4;
5947 
  State.regs[dstreg2] = temp;
5948 
  State.regs[dstreg1] = result1;
5949 
}
5950 
 
5951 
// 1111 0111 1010 0100 imm4 Rn1 Rm2 Rn2; add_lsr imm4, Rn1, Rm2, Rn2
5952 
8.0xf7+8.0xa4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_lsr
5953 
"add_lsr"
5954 
*am33
5955 
{
5956 
  int srcreg2, dstreg1, dstreg2;
5957 
  int result1;
5958 
 
5959 
  PC = cia;
5960 
  srcreg2 = translate_rreg (SD_, RM2);
5961 
  dstreg1 = translate_rreg (SD_, RN1);
5962 
  dstreg2 = translate_rreg (SD_, RN2);
5963 
 
5964 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5965 
  State.regs[dstreg2] >>= State.regs[srcreg2];
5966 
  State.regs[dstreg1] = result1;
5967 
}
5968 
 
5969 
// 1111 0111 1011 0100 imm4 Rn1 imm4 Rn2; add_lsr imm4, Rn1, imm4, Rn2
5970 
8.0xf7+8.0xb4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_lsr
5971 
"add_lsr"
5972 
*am33
5973 
{
5974 
  int dstreg1, dstreg2;
5975 
  int result1;
5976 
  signed int temp;
5977 
 
5978 
  PC = cia;
5979 
  dstreg1 = translate_rreg (SD_, RN1);
5980 
  dstreg2 = translate_rreg (SD_, RN2);
5981 
 
5982 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
5983 
  State.regs[dstreg2] >>= IMM4;
5984 
  State.regs[dstreg1] = result1;
5985 
}
5986 
 
5987 
 
5988 
// 1111 0111 1100 0100 imm4 Rn1 Rm2 Rn2; add_asl imm4, Rn1, Rm2, Rn2
5989 
8.0xf7+8.0xc4+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::add_asl
5990 
"add_asl"
5991 
*am33
5992 
{
5993 
  int srcreg2, dstreg1, dstreg2;
5994 
  int result1;
5995 
 
5996 
  PC = cia;
5997 
  srcreg2 = translate_rreg (SD_, RM2);
5998 
  dstreg1 = translate_rreg (SD_, RN1);
5999 
  dstreg2 = translate_rreg (SD_, RN2);
6000 
 
6001 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
6002 
  State.regs[dstreg2] <<= State.regs[srcreg2];
6003 
  State.regs[dstreg1] = result1;
6004 
}
6005 
 
6006 
// 1111 0111 1101 0100 imm4 Rn1 imm4 Rn2; add_asl imm4, Rn1, imm4, Rn2
6007 
8.0xf7+8.0xd4+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::add_asl
6008 
"add_asl"
6009 
*am33
6010 
{
6011 
  int dstreg1, dstreg2;
6012 
  int result1;
6013 
  signed int temp;
6014 
 
6015 
  PC = cia;
6016 
  dstreg1 = translate_rreg (SD_, RN1);
6017 
  dstreg2 = translate_rreg (SD_, RN2);
6018 
 
6019 
  result1 = State.regs[dstreg1] + EXTEND4 (IMM4A);
6020 
  State.regs[dstreg2] <<= IMM4;
6021 
  State.regs[dstreg1] = result1;
6022 
}
6023 
 
6024 
// 1111 0111 0000 0101 imm4 Rn1 Rm2 Rn2; cmp_add imm4, Rn1, Rm2, Rn2
6025 
8.0xf7+8.0x05+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_add
6026 
"cmp_add"
6027 
*am33
6028 
{
6029 
  int srcreg2, dstreg1, dstreg2;
6030 
 
6031 
  PC = cia;
6032 
  srcreg2 = translate_rreg (SD_, RM2);
6033 
  dstreg1 = translate_rreg (SD_, RN1);
6034 
  dstreg2 = translate_rreg (SD_, RN2);
6035 
 
6036 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6037 
  State.regs[dstreg2] += State.regs[srcreg2];
6038 
}
6039 
 
6040 
// 1111 0111 0001 0101 imm4 Rn1 imm4 Rn2; cmp_add imm4, Rn1, imm4, Rn2
6041 
8.0xf7+8.0x15+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_add
6042 
"cmp_add"
6043 
*am33
6044 
{
6045 
  int dstreg1, dstreg2;
6046 
 
6047 
  PC = cia;
6048 
  dstreg1 = translate_rreg (SD_, RN1);
6049 
  dstreg2 = translate_rreg (SD_, RN2);
6050 
 
6051 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6052 
  State.regs[dstreg2] += EXTEND4 (IMM4);
6053 
}
6054 
 
6055 
// 1111 0111 0010 0101 imm4 Rn1 Rm2 Rn2; cmp_sub imm4, Rn1, Rm2, Rn2
6056 
8.0xf7+8.0x25+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_sub
6057 
"cmp_sub"
6058 
*am33
6059 
{
6060 
  int srcreg2, dstreg1, dstreg2;
6061 
 
6062 
  PC = cia;
6063 
  srcreg2 = translate_rreg (SD_, RM2);
6064 
  dstreg1 = translate_rreg (SD_, RN1);
6065 
  dstreg2 = translate_rreg (SD_, RN2);
6066 
 
6067 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6068 
  State.regs[dstreg2] -= State.regs[srcreg2];
6069 
}
6070 
 
6071 
// 1111 0111 0011 0101 imm4 Rn1 imm4 Rn2; cmp_sub imm4, Rn1, imm4, Rn2
6072 
8.0xf7+8.0x35+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_sub
6073 
"cmp_sub"
6074 
*am33
6075 
{
6076 
  int dstreg1, dstreg2;
6077 
 
6078 
  PC = cia;
6079 
  dstreg1 = translate_rreg (SD_, RN1);
6080 
  dstreg2 = translate_rreg (SD_, RN2);
6081 
 
6082 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6083 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
6084 
}
6085 
 
6086 
// 1111 0111 0110 0101 imm4 Rn1 Rm2 Rn2; cmp_mov imm4, Rn1, Rm2, Rn2
6087 
8.0xf7+8.0x65+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_mov
6088 
"cmp_mov"
6089 
*am33
6090 
{
6091 
  int srcreg2, dstreg1, dstreg2;
6092 
 
6093 
  PC = cia;
6094 
  srcreg2 = translate_rreg (SD_, RM2);
6095 
  dstreg1 = translate_rreg (SD_, RN1);
6096 
  dstreg2 = translate_rreg (SD_, RN2);
6097 
 
6098 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6099 
  State.regs[dstreg2] = State.regs[srcreg2];
6100 
}
6101 
 
6102 
// 1111 0111 0111 0101 imm4 Rn1 imm4 Rn2; cmp_mov imm4, Rn1, imm4, Rn2
6103 
8.0xf7+8.0x75+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_mov
6104 
"cmp_mov"
6105 
*am33
6106 
{
6107 
  int dstreg1, dstreg2;
6108 
 
6109 
  PC = cia;
6110 
  dstreg1 = translate_rreg (SD_, RN1);
6111 
  dstreg2 = translate_rreg (SD_, RN2);
6112 
 
6113 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6114 
  State.regs[dstreg2] = EXTEND4 (IMM4);
6115 
}
6116 
 
6117 
// 1111 0111 1000 0101 imm4 Rn1 Rm2 Rn2; cmp_asr imm4, Rn1, Rm2, Rn2
6118 
8.0xf7+8.0x85+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asr
6119 
"cmp_asr"
6120 
*am33
6121 
{
6122 
  int srcreg2, dstreg1, dstreg2;
6123 
  signed int temp;
6124 
 
6125 
  PC = cia;
6126 
  srcreg2 = translate_rreg (SD_, RM2);
6127 
  dstreg1 = translate_rreg (SD_, RN1);
6128 
  dstreg2 = translate_rreg (SD_, RN2);
6129 
 
6130 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6131 
  temp = State.regs[dstreg2];
6132 
  temp >>= State.regs[srcreg2];
6133 
  State.regs[dstreg2] = temp;
6134 
}
6135 
 
6136 
// 1111 0111 1001 0101 imm4 Rn1 imm4 Rn2; cmp_asr imm4, Rn1, imm4, Rn2
6137 
8.0xf7+8.0x95+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asr
6138 
"cmp_asr"
6139 
*am33
6140 
{
6141 
  int dstreg1, dstreg2;
6142 
  signed int temp;
6143 
 
6144 
  PC = cia;
6145 
  dstreg1 = translate_rreg (SD_, RN1);
6146 
  dstreg2 = translate_rreg (SD_, RN2);
6147 
 
6148 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6149 
  temp = State.regs[dstreg2];
6150 
  temp >>= IMM4;
6151 
  State.regs[dstreg2] = temp;
6152 
}
6153 
 
6154 
// 1111 0111 1010 0101 imm4 Rn1 Rm2 Rn2; cmp_lsr imm4, Rn1, Rm2, Rn2
6155 
8.0xf7+8.0xa5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_lsr
6156 
"cmp_lsr"
6157 
*am33
6158 
{
6159 
  int srcreg2, dstreg1, dstreg2;
6160 
 
6161 
  PC = cia;
6162 
  srcreg2 = translate_rreg (SD_, RM2);
6163 
  dstreg1 = translate_rreg (SD_, RN1);
6164 
  dstreg2 = translate_rreg (SD_, RN2);
6165 
 
6166 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6167 
  State.regs[dstreg2] >>= State.regs[srcreg2];
6168 
}
6169 
 
6170 
// 1111 0111 1011 0101 imm4 Rn1 imm4 Rn2; cmp_lsr imm4, Rn1, imm4, Rn2
6171 
8.0xf7+8.0xb5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_lsr
6172 
"cmp_lsr"
6173 
*am33
6174 
{
6175 
  int dstreg1, dstreg2;
6176 
  signed int temp;
6177 
 
6178 
  PC = cia;
6179 
  dstreg1 = translate_rreg (SD_, RN1);
6180 
  dstreg2 = translate_rreg (SD_, RN2);
6181 
 
6182 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6183 
  State.regs[dstreg2] >>= IMM4;
6184 
}
6185 
 
6186 
 
6187 
// 1111 0111 1100 0101 imm4 Rn1 Rm2 Rn2; cmp_asl imm4, Rn1, Rm2, Rn2
6188 
8.0xf7+8.0xc5+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::cmp_asl
6189 
"cmp_asl"
6190 
*am33
6191 
{
6192 
  int srcreg2, dstreg1, dstreg2;
6193 
 
6194 
  PC = cia;
6195 
  srcreg2 = translate_rreg (SD_, RM2);
6196 
  dstreg1 = translate_rreg (SD_, RN1);
6197 
  dstreg2 = translate_rreg (SD_, RN2);
6198 
 
6199 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6200 
  State.regs[dstreg2] <<= State.regs[srcreg2];
6201 
}
6202 
 
6203 
// 1111 0111 1101 0101 imm4 Rn1 imm4 Rn2; cmp_asl imm4, Rn1, imm4, Rn2
6204 
8.0xf7+8.0xd5+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::cmp_asl
6205 
"cmp_asl"
6206 
*am33
6207 
{
6208 
  int dstreg1, dstreg2;
6209 
  signed int temp;
6210 
 
6211 
  PC = cia;
6212 
  dstreg1 = translate_rreg (SD_, RN1);
6213 
  dstreg2 = translate_rreg (SD_, RN2);
6214 
 
6215 
  genericCmp (EXTEND4 (IMM4A), State.regs[dstreg1]);
6216 
  State.regs[dstreg2] <<= IMM4;
6217 
}
6218 
 
6219 
// 1111 0111 0000 0110 imm4 Rn1 Rm2 Rn2; sub_add imm4, Rn1, Rm2, Rn2
6220 
8.0xf7+8.0x06+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_add
6221 
"sub_add"
6222 
*am33
6223 
{
6224 
  int srcreg2, dstreg1, dstreg2;
6225 
  int result1;
6226 
 
6227 
  PC = cia;
6228 
  srcreg2 = translate_rreg (SD_, RM2);
6229 
  dstreg1 = translate_rreg (SD_, RN1);
6230 
  dstreg2 = translate_rreg (SD_, RN2);
6231 
 
6232 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6233 
  State.regs[dstreg2] += State.regs[srcreg2];
6234 
  State.regs[dstreg1] = result1;
6235 
}
6236 
 
6237 
// 1111 0111 0001 0110 imm4 Rn1 imm4 Rn2; sub_add imm4, Rn1, imm4, Rn2
6238 
8.0xf7+8.0x16+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_add
6239 
"sub_add"
6240 
*am33
6241 
{
6242 
  int dstreg1, dstreg2;
6243 
  int result1;
6244 
 
6245 
  PC = cia;
6246 
  dstreg1 = translate_rreg (SD_, RN1);
6247 
  dstreg2 = translate_rreg (SD_, RN2);
6248 
 
6249 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6250 
  State.regs[dstreg2] += EXTEND4 (IMM4);
6251 
  State.regs[dstreg1] = result1;
6252 
}
6253 
 
6254 
// 1111 0111 0010 0110 imm4 Rn1 Rm2 Rn2; sub_sub imm4, Rn1, Rm2, Rn2
6255 
8.0xf7+8.0x26+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_sub
6256 
"sub_sub"
6257 
*am33
6258 
{
6259 
  int srcreg2, dstreg1, dstreg2;
6260 
  int result1;
6261 
 
6262 
  PC = cia;
6263 
  srcreg2 = translate_rreg (SD_, RM2);
6264 
  dstreg1 = translate_rreg (SD_, RN1);
6265 
  dstreg2 = translate_rreg (SD_, RN2);
6266 
 
6267 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6268 
  State.regs[dstreg2] -= State.regs[srcreg2];
6269 
  State.regs[dstreg1] = result1;
6270 
}
6271 
 
6272 
// 1111 0111 0011 0110 imm4 Rn1 imm4 Rn2; sub_sub imm4, Rn1, imm4, Rn2
6273 
8.0xf7+8.0x36+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_sub
6274 
"sub_sub"
6275 
*am33
6276 
{
6277 
  int dstreg1, dstreg2;
6278 
  int result1;
6279 
 
6280 
  PC = cia;
6281 
  dstreg1 = translate_rreg (SD_, RN1);
6282 
  dstreg2 = translate_rreg (SD_, RN2);
6283 
 
6284 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6285 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
6286 
  State.regs[dstreg1] = result1;
6287 
}
6288 
 
6289 
// 1111 0111 0100 0110 imm4 Rn1 Rm2 Rn2; sub_cmp imm4, Rn1, Rm2, Rn2
6290 
8.0xf7+8.0x46+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_cmp
6291 
"sub_cmp"
6292 
*am33
6293 
{
6294 
  int srcreg2, dstreg1, dstreg2;
6295 
  int result1;
6296 
 
6297 
  PC = cia;
6298 
  srcreg2 = translate_rreg (SD_, RM2);
6299 
  dstreg1 = translate_rreg (SD_, RN1);
6300 
  dstreg2 = translate_rreg (SD_, RN2);
6301 
 
6302 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6303 
  State.regs[dstreg1] -= EXTEND4 (IMM4A);
6304 
}
6305 
 
6306 
// 1111 0111 0101 0110 imm4 Rn1 imm4 Rn2; sub_cmp imm4, Rn1, imm4, Rn2
6307 
8.0xf7+8.0x56+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_cmp
6308 
"sub_cmp"
6309 
*am33
6310 
{
6311 
  int dstreg1, dstreg2;
6312 
  int result1;
6313 
 
6314 
  PC = cia;
6315 
  dstreg1 = translate_rreg (SD_, RN1);
6316 
  dstreg2 = translate_rreg (SD_, RN2);
6317 
 
6318 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6319 
  State.regs[dstreg1] -= EXTEND4 (IMM4A);
6320 
}
6321 
 
6322 
// 1111 0111 0110 0110 imm4 Rn1 Rm2 Rn2; sub_mov imm4, Rn1, Rm2, Rn2
6323 
8.0xf7+8.0x66+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_mov
6324 
"sub_mov"
6325 
*am33
6326 
{
6327 
  int srcreg2, dstreg1, dstreg2;
6328 
  int result1;
6329 
 
6330 
  PC = cia;
6331 
  srcreg2 = translate_rreg (SD_, RM2);
6332 
  dstreg1 = translate_rreg (SD_, RN1);
6333 
  dstreg2 = translate_rreg (SD_, RN2);
6334 
 
6335 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6336 
  State.regs[dstreg2] = State.regs[srcreg2];
6337 
  State.regs[dstreg1] = result1;
6338 
}
6339 
 
6340 
// 1111 0111 0111 0110 imm4 Rn1 imm4 Rn2; sub_mov imm4, Rn1, imm4, Rn2
6341 
8.0xf7+8.0x76+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_mov
6342 
"sub_mov"
6343 
*am33
6344 
{
6345 
  int dstreg1, dstreg2;
6346 
  int result1;
6347 
 
6348 
  PC = cia;
6349 
  dstreg1 = translate_rreg (SD_, RN1);
6350 
  dstreg2 = translate_rreg (SD_, RN2);
6351 
 
6352 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6353 
  State.regs[dstreg2] = EXTEND4 (IMM4);
6354 
  State.regs[dstreg1] = result1;
6355 
}
6356 
 
6357 
// 1111 0111 1000 0110 imm4 Rn1 Rm2 Rn2; sub_asr imm4, Rn1, Rm2, Rn2
6358 
8.0xf7+8.0x86+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asr
6359 
"sub_asr"
6360 
*am33
6361 
{
6362 
  int srcreg2, dstreg1, dstreg2;
6363 
  int result1;
6364 
  signed int temp;
6365 
 
6366 
  PC = cia;
6367 
  srcreg2 = translate_rreg (SD_, RM2);
6368 
  dstreg1 = translate_rreg (SD_, RN1);
6369 
  dstreg2 = translate_rreg (SD_, RN2);
6370 
 
6371 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6372 
  temp = State.regs[dstreg2];
6373 
  temp >>= State.regs[srcreg2];
6374 
  State.regs[dstreg2] = temp;
6375 
  State.regs[dstreg1] = result1;
6376 
}
6377 
 
6378 
// 1111 0111 1001 0110 imm4 Rn1 imm4 Rn2; sub_asr imm4, Rn1, imm4, Rn2
6379 
8.0xf7+8.0x96+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asr
6380 
"sub_asr"
6381 
*am33
6382 
{
6383 
  int dstreg1, dstreg2;
6384 
  int result1;
6385 
  signed int temp;
6386 
 
6387 
  PC = cia;
6388 
  dstreg1 = translate_rreg (SD_, RN1);
6389 
  dstreg2 = translate_rreg (SD_, RN2);
6390 
 
6391 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6392 
  temp = State.regs[dstreg2];
6393 
  temp >>= IMM4;
6394 
  State.regs[dstreg2] = temp;
6395 
  State.regs[dstreg1] = result1;
6396 
}
6397 
 
6398 
// 1111 0111 1010 0110 imm4 Rn1 Rm2 Rn2; sub_lsr imm4, Rn1, Rm2, Rn2
6399 
8.0xf7+8.0xa6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_lsr
6400 
"sub_lsr"
6401 
*am33
6402 
{
6403 
  int srcreg2, dstreg1, dstreg2;
6404 
  int result1;
6405 
 
6406 
  PC = cia;
6407 
  srcreg2 = translate_rreg (SD_, RM2);
6408 
  dstreg1 = translate_rreg (SD_, RN1);
6409 
  dstreg2 = translate_rreg (SD_, RN2);
6410 
 
6411 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6412 
  State.regs[dstreg2] >>= State.regs[srcreg2];
6413 
  State.regs[dstreg1] = result1;
6414 
}
6415 
 
6416 
// 1111 0111 1011 0110 imm4 Rn1 imm4 Rn2; sub_lsr imm4, Rn1, imm4, Rn2
6417 
8.0xf7+8.0xb6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_lsr
6418 
"sub_lsr"
6419 
*am33
6420 
{
6421 
  int dstreg1, dstreg2;
6422 
  int result1;
6423 
  signed int temp;
6424 
 
6425 
  PC = cia;
6426 
  dstreg1 = translate_rreg (SD_, RN1);
6427 
  dstreg2 = translate_rreg (SD_, RN2);
6428 
 
6429 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6430 
  State.regs[dstreg2] >>= IMM4;
6431 
  State.regs[dstreg1] = result1;
6432 
}
6433 
 
6434 
 
6435 
// 1111 0111 1100 0110 imm4 Rn1 Rm2 Rn2; sub_asl imm4, Rn1, Rm2, Rn2
6436 
8.0xf7+8.0xc6+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::sub_asl
6437 
"sub_asl"
6438 
*am33
6439 
{
6440 
  int srcreg2, dstreg1, dstreg2;
6441 
  int result1;
6442 
 
6443 
  PC = cia;
6444 
  srcreg2 = translate_rreg (SD_, RM2);
6445 
  dstreg1 = translate_rreg (SD_, RN1);
6446 
  dstreg2 = translate_rreg (SD_, RN2);
6447 
 
6448 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6449 
  State.regs[dstreg2] <<= State.regs[srcreg2];
6450 
  State.regs[dstreg1] = result1;
6451 
}
6452 
 
6453 
// 1111 0111 1101 0110 imm4 Rn1 imm4 Rn2; sub_asl imm4, Rn1, imm4, Rn2
6454 
8.0xf7+8.0xd6+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::sub_asl
6455 
"sub_asl"
6456 
*am33
6457 
{
6458 
  int dstreg1, dstreg2;
6459 
  int result1;
6460 
  signed int temp;
6461 
 
6462 
  PC = cia;
6463 
  dstreg1 = translate_rreg (SD_, RN1);
6464 
  dstreg2 = translate_rreg (SD_, RN2);
6465 
 
6466 
  result1 = State.regs[dstreg1] - EXTEND4 (IMM4A);
6467 
  State.regs[dstreg2] <<= IMM4;
6468 
  State.regs[dstreg1] = result1;
6469 
}
6470 
 
6471 
// 1111 0111 0000 0111 imm4 Rn1 Rm2 Rn2; mov_add imm4, Rn1, Rm2, Rn2
6472 
8.0xf7+8.0x07+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_add
6473 
"mov_add"
6474 
*am33
6475 
{
6476 
  int srcreg2, dstreg1, dstreg2;
6477 
  int result1;
6478 
 
6479 
  PC = cia;
6480 
  srcreg2 = translate_rreg (SD_, RM2);
6481 
  dstreg1 = translate_rreg (SD_, RN1);
6482 
  dstreg2 = translate_rreg (SD_, RN2);
6483 
 
6484 
  result1 = EXTEND4 (IMM4A);
6485 
  State.regs[dstreg2] += State.regs[srcreg2];
6486 
  State.regs[dstreg1] = result1;
6487 
}
6488 
 
6489 
// 1111 0111 0001 0111 imm4 Rn1 imm4 Rn2; mov_add imm4, Rn1, imm4, Rn2
6490 
8.0xf7+8.0x17+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_add
6491 
"mov_add"
6492 
*am33
6493 
{
6494 
  int dstreg1, dstreg2;
6495 
  int result1;
6496 
 
6497 
  PC = cia;
6498 
  dstreg1 = translate_rreg (SD_, RN1);
6499 
  dstreg2 = translate_rreg (SD_, RN2);
6500 
 
6501 
  result1 = EXTEND4 (IMM4A);
6502 
  State.regs[dstreg2] += EXTEND4 (IMM4);
6503 
  State.regs[dstreg1] = result1;
6504 
}
6505 
 
6506 
// 1111 0111 0010 0111 imm4 Rn1 Rm2 Rn2; mov_sub imm4, Rn1, Rm2, Rn2
6507 
8.0xf7+8.0x27+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_sub
6508 
"mov_sub"
6509 
*am33
6510 
{
6511 
  int srcreg2, dstreg1, dstreg2;
6512 
  int result1;
6513 
 
6514 
  PC = cia;
6515 
  srcreg2 = translate_rreg (SD_, RM2);
6516 
  dstreg1 = translate_rreg (SD_, RN1);
6517 
  dstreg2 = translate_rreg (SD_, RN2);
6518 
 
6519 
  result1 = EXTEND4 (IMM4A);
6520 
  State.regs[dstreg2] -= State.regs[srcreg2];
6521 
  State.regs[dstreg1] = result1;
6522 
}
6523 
 
6524 
// 1111 0111 0011 0111 imm4 Rn1 imm4 Rn2; mov_sub imm4, Rn1, imm4, Rn2
6525 
8.0xf7+8.0x37+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_sub
6526 
"mov_sub"
6527 
*am33
6528 
{
6529 
  int dstreg1, dstreg2;
6530 
  int result1;
6531 
 
6532 
  PC = cia;
6533 
  dstreg1 = translate_rreg (SD_, RN1);
6534 
  dstreg2 = translate_rreg (SD_, RN2);
6535 
 
6536 
  result1 = EXTEND4 (IMM4A);
6537 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
6538 
  State.regs[dstreg1] = result1;
6539 
}
6540 
 
6541 
// 1111 0111 0100 0111 imm4 Rn1 Rm2 Rn2; mov_cmp imm4, Rn1, Rm2, Rn2
6542 
8.0xf7+8.0x47+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_cmp
6543 
"mov_cmp"
6544 
*am33
6545 
{
6546 
  int srcreg2, dstreg1, dstreg2;
6547 
 
6548 
  PC = cia;
6549 
  srcreg2 = translate_rreg (SD_, RM2);
6550 
  dstreg1 = translate_rreg (SD_, RN1);
6551 
  dstreg2 = translate_rreg (SD_, RN2);
6552 
 
6553 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6554 
  State.regs[dstreg1] = EXTEND4 (IMM4A);
6555 
}
6556 
 
6557 
// 1111 0111 0101 0111 imm4 Rn1 imm4 Rn2; mov_cmp imm4, Rn1, imm4, Rn2
6558 
8.0xf7+8.0x57+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_cmp
6559 
"mov_cmp"
6560 
*am33
6561 
{
6562 
  int dstreg1, dstreg2;
6563 
 
6564 
  PC = cia;
6565 
  dstreg1 = translate_rreg (SD_, RN1);
6566 
  dstreg2 = translate_rreg (SD_, RN2);
6567 
 
6568 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6569 
  State.regs[dstreg1] = EXTEND4 (IMM4A);
6570 
}
6571 
 
6572 
// 1111 0111 0110 0111 imm4 Rn1 Rm2 Rn2; mov_mov imm4, Rn1, Rm2, Rn2
6573 
8.0xf7+8.0x67+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_mov
6574 
"mov_mov"
6575 
*am33
6576 
{
6577 
  int srcreg2, dstreg1, dstreg2;
6578 
  int result1;
6579 
 
6580 
  PC = cia;
6581 
  srcreg2 = translate_rreg (SD_, RM2);
6582 
  dstreg1 = translate_rreg (SD_, RN1);
6583 
  dstreg2 = translate_rreg (SD_, RN2);
6584 
 
6585 
  result1 = EXTEND4 (IMM4A);
6586 
  State.regs[dstreg2] = State.regs[srcreg2];
6587 
  State.regs[dstreg1] = result1;
6588 
}
6589 
 
6590 
// 1111 0111 0111 0111 imm4 Rn1 imm4 Rn2; mov_mov imm4, Rn1, imm4, Rn2
6591 
8.0xf7+8.0x77+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_mov
6592 
"mov_mov"
6593 
*am33
6594 
{
6595 
  int dstreg1, dstreg2;
6596 
  int result1;
6597 
 
6598 
  PC = cia;
6599 
  dstreg1 = translate_rreg (SD_, RN1);
6600 
  dstreg2 = translate_rreg (SD_, RN2);
6601 
 
6602 
  result1 = EXTEND4 (IMM4A);
6603 
  State.regs[dstreg2] = EXTEND4 (IMM4);
6604 
  State.regs[dstreg1] = result1;
6605 
}
6606 
 
6607 
// 1111 0111 1000 0111 imm4 Rn1 Rm2 Rn2; mov_asr imm4, Rn1, Rm2, Rn2
6608 
8.0xf7+8.0x87+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asr
6609 
"mov_asr"
6610 
*am33
6611 
{
6612 
  int srcreg2, dstreg1, dstreg2;
6613 
  int result1;
6614 
  signed int temp;
6615 
 
6616 
  PC = cia;
6617 
  srcreg2 = translate_rreg (SD_, RM2);
6618 
  dstreg1 = translate_rreg (SD_, RN1);
6619 
  dstreg2 = translate_rreg (SD_, RN2);
6620 
 
6621 
  result1 = EXTEND4 (IMM4A);
6622 
  temp = State.regs[dstreg2];
6623 
  temp >>= State.regs[srcreg2];
6624 
  State.regs[dstreg2] = temp;
6625 
  State.regs[dstreg1] = result1;
6626 
}
6627 
 
6628 
// 1111 0111 1001 0111 imm4 Rn1 imm4 Rn2; mov_asr imm4, Rn1, imm4, Rn2
6629 
8.0xf7+8.0x97+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asr
6630 
"mov_asr"
6631 
*am33
6632 
{
6633 
  int dstreg1, dstreg2;
6634 
  int result1;
6635 
  signed int temp;
6636 
 
6637 
  PC = cia;
6638 
  dstreg1 = translate_rreg (SD_, RN1);
6639 
  dstreg2 = translate_rreg (SD_, RN2);
6640 
 
6641 
  result1 = EXTEND4 (IMM4A);
6642 
  temp = State.regs[dstreg2];
6643 
  temp >>= IMM4;
6644 
  State.regs[dstreg2] = temp;
6645 
  State.regs[dstreg1] = result1;
6646 
}
6647 
 
6648 
// 1111 0111 1010 0111 imm4 Rn1 Rm2 Rn2; mov_lsr imm4, Rn1, Rm2, Rn2
6649 
8.0xf7+8.0xa7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_lsr
6650 
"mov_lsr"
6651 
*am33
6652 
{
6653 
  int srcreg2, dstreg1, dstreg2;
6654 
  int result1;
6655 
 
6656 
  PC = cia;
6657 
  srcreg2 = translate_rreg (SD_, RM2);
6658 
  dstreg1 = translate_rreg (SD_, RN1);
6659 
  dstreg2 = translate_rreg (SD_, RN2);
6660 
 
6661 
  result1 = EXTEND4 (IMM4A);
6662 
  State.regs[dstreg2] >>= State.regs[srcreg2];
6663 
  State.regs[dstreg1] = result1;
6664 
}
6665 
 
6666 
// 1111 0111 1011 0111 imm4 Rn1 imm4 Rn2; mov_lsr imm4, Rn1, imm4, Rn2
6667 
8.0xf7+8.0xb7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_lsr
6668 
"mov_lsr"
6669 
*am33
6670 
{
6671 
  int dstreg1, dstreg2;
6672 
  int result1;
6673 
  signed int temp;
6674 
 
6675 
  PC = cia;
6676 
  dstreg1 = translate_rreg (SD_, RN1);
6677 
  dstreg2 = translate_rreg (SD_, RN2);
6678 
 
6679 
  result1 = EXTEND4 (IMM4A);
6680 
  State.regs[dstreg2] >>= IMM4;
6681 
  State.regs[dstreg1] = result1;
6682 
}
6683 
 
6684 
 
6685 
// 1111 0111 1100 0111 imm4 Rn1 Rm2 Rn2; mov_asl imm4, Rn1, Rm2, Rn2
6686 
8.0xf7+8.0xc7+4.IMM4A,4.RN1+4.RM2,4.RN2!RN1:D2c:::mov_asl
6687 
"mov_asl"
6688 
*am33
6689 
{
6690 
  int srcreg2, dstreg1, dstreg2;
6691 
  int result1;
6692 
 
6693 
  PC = cia;
6694 
  srcreg2 = translate_rreg (SD_, RM2);
6695 
  dstreg1 = translate_rreg (SD_, RN1);
6696 
  dstreg2 = translate_rreg (SD_, RN2);
6697 
 
6698 
  result1 = EXTEND4 (IMM4A);
6699 
  State.regs[dstreg2] <<= State.regs[srcreg2];
6700 
  State.regs[dstreg1] = result1;
6701 
}
6702 
 
6703 
// 1111 0111 1101 0111 imm4 Rn1 imm4 Rn2; mov_asl imm4, Rn1, imm4, Rn2
6704 
8.0xf7+8.0xd7+4.IMM4A,4.RN1+4.IMM4,4.RN2!RN1:D2d:::mov_asl
6705 
"mov_asl"
6706 
*am33
6707 
{
6708 
  int dstreg1, dstreg2;
6709 
  int result1;
6710 
  signed int temp;
6711 
 
6712 
  PC = cia;
6713 
  dstreg1 = translate_rreg (SD_, RN1);
6714 
  dstreg2 = translate_rreg (SD_, RN2);
6715 
 
6716 
  result1 = EXTEND4 (IMM4A);
6717 
  State.regs[dstreg2] <<= IMM4;
6718 
  State.regs[dstreg1] = result1;
6719 
}
6720 
 
6721 
// 1111 0111 0000 1000 Rm1 Rn1 Rm2 Rn2; and_add Rm1, Rn1, Rm2, Rn2
6722 
8.0xf7+8.0x08+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_add
6723 
"and_add"
6724 
*am33
6725 
{
6726 
  int srcreg1, srcreg2, dstreg1, dstreg2;
6727 
  int result1;
6728 
 
6729 
  PC = cia;
6730 
  srcreg1 = translate_rreg (SD_, RM1);
6731 
  srcreg2 = translate_rreg (SD_, RM2);
6732 
  dstreg1 = translate_rreg (SD_, RN1);
6733 
  dstreg2 = translate_rreg (SD_, RN2);
6734 
 
6735 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6736 
  State.regs[dstreg2] += State.regs[srcreg2];
6737 
  State.regs[dstreg1] = result1;
6738 
}
6739 
 
6740 
// 1111 0111 0001 1000 Rm1 Rn1 imm4 Rn2; and_add Rm1, Rn1, imm4, Rn2
6741 
8.0xf7+8.0x18+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_add
6742 
"and_add"
6743 
*am33
6744 
{
6745 
  int srcreg1, dstreg1, dstreg2;
6746 
  int result1;
6747 
 
6748 
  PC = cia;
6749 
  srcreg1 = translate_rreg (SD_, RM1);
6750 
  dstreg1 = translate_rreg (SD_, RN1);
6751 
  dstreg2 = translate_rreg (SD_, RN2);
6752 
 
6753 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6754 
  State.regs[dstreg2] += EXTEND4 (IMM4);
6755 
  State.regs[dstreg1] = result1;
6756 
}
6757 
 
6758 
// 1111 0111 0010 1000 Rm1 Rn1 Rm2 Rn2; and_sub Rm1, Rn1, Rm2, Rn2
6759 
8.0xf7+8.0x28+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_sub
6760 
"and_sub"
6761 
*am33
6762 
{
6763 
  int srcreg1, srcreg2, dstreg1, dstreg2;
6764 
  int result1;
6765 
 
6766 
  PC = cia;
6767 
  srcreg1 = translate_rreg (SD_, RM1);
6768 
  srcreg2 = translate_rreg (SD_, RM2);
6769 
  dstreg1 = translate_rreg (SD_, RN1);
6770 
  dstreg2 = translate_rreg (SD_, RN2);
6771 
 
6772 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6773 
  State.regs[dstreg2] -= State.regs[srcreg2];
6774 
  State.regs[dstreg1] = result1;
6775 
}
6776 
 
6777 
// 1111 0111 0011 1000 Rm1 Rn1 imm4 Rn2; and_sub Rm1, Rn1, imm4, Rn2
6778 
8.0xf7+8.0x38+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_sub
6779 
"and_sub"
6780 
*am33
6781 
{
6782 
  int srcreg1, dstreg1, dstreg2;
6783 
  int result1;
6784 
 
6785 
  PC = cia;
6786 
  srcreg1 = translate_rreg (SD_, RM1);
6787 
  dstreg1 = translate_rreg (SD_, RN1);
6788 
  dstreg2 = translate_rreg (SD_, RN2);
6789 
 
6790 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6791 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
6792 
  State.regs[dstreg1] = result1;
6793 
}
6794 
 
6795 
// 1111 0111 0100 1000 Rm1 Rn1 Rm2 Rn2; and_cmp Rm1, Rn1, Rm2, Rn2
6796 
8.0xf7+8.0x48+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_cmp
6797 
"and_cmp"
6798 
*am33
6799 
{
6800 
  int srcreg1, srcreg2, dstreg1, dstreg2;
6801 
 
6802 
  PC = cia;
6803 
  srcreg1 = translate_rreg (SD_, RM1);
6804 
  srcreg2 = translate_rreg (SD_, RM2);
6805 
  dstreg1 = translate_rreg (SD_, RN1);
6806 
  dstreg2 = translate_rreg (SD_, RN2);
6807 
 
6808 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
6809 
  State.regs[dstreg1] &= State.regs[srcreg1];
6810 
}
6811 
 
6812 
// 1111 0111 0101 1000 Rm1 Rn1 imm4 Rn2; and_cmp Rm1, Rn1, imm4, Rn2
6813 
8.0xf7+8.0x58+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_cmp
6814 
"and_cmp"
6815 
*am33
6816 
{
6817 
  int srcreg1, dstreg1, dstreg2;
6818 
 
6819 
  PC = cia;
6820 
  srcreg1 = translate_rreg (SD_, RM1);
6821 
  dstreg1 = translate_rreg (SD_, RN1);
6822 
  dstreg2 = translate_rreg (SD_, RN2);
6823 
 
6824 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
6825 
  State.regs[dstreg1] &= State.regs[srcreg1];
6826 
}
6827 
 
6828 
// 1111 0111 0110 1000 Rm1 Rn1 Rm2 Rn2; and_mov Rm1, Rn1, Rm2, Rn2
6829 
8.0xf7+8.0x68+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_mov
6830 
"and_mov"
6831 
*am33
6832 
{
6833 
  int srcreg1, srcreg2, dstreg1, dstreg2;
6834 
  int result1;
6835 
 
6836 
  PC = cia;
6837 
  srcreg1 = translate_rreg (SD_, RM1);
6838 
  srcreg2 = translate_rreg (SD_, RM2);
6839 
  dstreg1 = translate_rreg (SD_, RN1);
6840 
  dstreg2 = translate_rreg (SD_, RN2);
6841 
 
6842 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6843 
  State.regs[dstreg2] = State.regs[srcreg2];
6844 
  State.regs[dstreg1] = result1;
6845 
}
6846 
 
6847 
// 1111 0111 0111 1000 Rm1 Rn1 imm4 Rn2; and_mov Rm1, Rn1, imm4, Rn2
6848 
8.0xf7+8.0x78+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_mov
6849 
"and_mov"
6850 
*am33
6851 
{
6852 
  int srcreg1, dstreg1, dstreg2;
6853 
  int result1;
6854 
 
6855 
  PC = cia;
6856 
  srcreg1 = translate_rreg (SD_, RM1);
6857 
  dstreg1 = translate_rreg (SD_, RN1);
6858 
  dstreg2 = translate_rreg (SD_, RN2);
6859 
 
6860 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6861 
  State.regs[dstreg2] = EXTEND4 (IMM4);
6862 
  State.regs[dstreg1] = result1;
6863 
}
6864 
 
6865 
// 1111 0111 1000 1000 Rm1 Rn1 Rm2 Rn2; and_asr Rm1, Rn1, Rm2, Rn2
6866 
8.0xf7+8.0x88+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asr
6867 
"and_asr"
6868 
*am33
6869 
{
6870 
  int srcreg1, srcreg2, dstreg1, dstreg2;
6871 
  int result1;
6872 
  signed int temp;
6873 
 
6874 
  PC = cia;
6875 
  srcreg1 = translate_rreg (SD_, RM1);
6876 
  srcreg2 = translate_rreg (SD_, RM2);
6877 
  dstreg1 = translate_rreg (SD_, RN1);
6878 
  dstreg2 = translate_rreg (SD_, RN2);
6879 
 
6880 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6881 
  temp = State.regs[dstreg2];
6882 
  temp >>= State.regs[srcreg2];
6883 
  State.regs[dstreg2] = temp;
6884 
  State.regs[dstreg1] = result1;
6885 
}
6886 
 
6887 
// 1111 0111 1001 1000 Rm1 Rn1 imm4 Rn2; and_asr Rm1, Rn1, imm4, Rn2
6888 
8.0xf7+8.0x98+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asr
6889 
"and_asr"
6890 
*am33
6891 
{
6892 
  int srcreg1, dstreg1, dstreg2;
6893 
  int result1;
6894 
  signed int temp;
6895 
 
6896 
  PC = cia;
6897 
  srcreg1 = translate_rreg (SD_, RM1);
6898 
  dstreg1 = translate_rreg (SD_, RN1);
6899 
  dstreg2 = translate_rreg (SD_, RN2);
6900 
 
6901 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6902 
  temp = State.regs[dstreg2];
6903 
  temp >>= IMM4;
6904 
  State.regs[dstreg2] = temp;
6905 
  State.regs[dstreg1] = result1;
6906 
}
6907 
 
6908 
// 1111 0111 1010 1000 Rm1 Rn1 Rm2 Rn2; and_lsr Rm1, Rn1, Rm2, Rn2
6909 
8.0xf7+8.0xa8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_lsr
6910 
"and_lsr"
6911 
*am33
6912 
{
6913 
  int srcreg1, srcreg2, dstreg1, dstreg2;
6914 
  int result1;
6915 
 
6916 
  PC = cia;
6917 
  srcreg1 = translate_rreg (SD_, RM1);
6918 
  srcreg2 = translate_rreg (SD_, RM2);
6919 
  dstreg1 = translate_rreg (SD_, RN1);
6920 
  dstreg2 = translate_rreg (SD_, RN2);
6921 
 
6922 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6923 
  State.regs[dstreg2] >>= State.regs[srcreg2];
6924 
  State.regs[dstreg1] = result1;
6925 
}
6926 
 
6927 
// 1111 0111 1011 1000 Rm1 Rn1 imm4 Rn2; and_lsr Rm1, Rn1, imm4, Rn2
6928 
8.0xf7+8.0xb8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_lsr
6929 
"and_lsr"
6930 
*am33
6931 
{
6932 
  int srcreg1, dstreg1, dstreg2;
6933 
  int result1;
6934 
  signed int temp;
6935 
 
6936 
  PC = cia;
6937 
  srcreg1 = translate_rreg (SD_, RM1);
6938 
  dstreg1 = translate_rreg (SD_, RN1);
6939 
  dstreg2 = translate_rreg (SD_, RN2);
6940 
 
6941 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6942 
  State.regs[dstreg2] >>= IMM4;
6943 
  State.regs[dstreg1] = result1;
6944 
}
6945 
 
6946 
 
6947 
// 1111 0111 1100 1000 Rm1 Rn1 Rm2 Rn2; and_asl Rm1, Rn1, Rm2, Rn2
6948 
8.0xf7+8.0xc8+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::and_asl
6949 
"and_asl"
6950 
*am33
6951 
{
6952 
  int srcreg1, srcreg2, dstreg1, dstreg2;
6953 
  int result1;
6954 
 
6955 
  PC = cia;
6956 
  srcreg1 = translate_rreg (SD_, RM1);
6957 
  srcreg2 = translate_rreg (SD_, RM2);
6958 
  dstreg1 = translate_rreg (SD_, RN1);
6959 
  dstreg2 = translate_rreg (SD_, RN2);
6960 
 
6961 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6962 
  State.regs[dstreg2] <<= State.regs[srcreg2];
6963 
  State.regs[dstreg1] = result1;
6964 
}
6965 
 
6966 
// 1111 0111 1101 1000 Rm1 Rn1 imm4 Rn2; and_asl Rm1, Rn1, imm4, Rn2
6967 
8.0xf7+8.0xd8+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::and_asl
6968 
"and_asl"
6969 
*am33
6970 
{
6971 
  int srcreg1, dstreg1, dstreg2;
6972 
  int result1;
6973 
  signed int temp;
6974 
 
6975 
  PC = cia;
6976 
  srcreg1 = translate_rreg (SD_, RM1);
6977 
  dstreg1 = translate_rreg (SD_, RN1);
6978 
  dstreg2 = translate_rreg (SD_, RN2);
6979 
 
6980 
  result1 = State.regs[dstreg1] & State.regs[srcreg1];
6981 
  State.regs[dstreg2] <<= IMM4;
6982 
  State.regs[dstreg1] = result1;
6983 
}
6984 
 
6985 
// 1111 0111 0000 1001 Rm1 Rn1 Rm2 Rn2; dmach_add Rm1, Rn1, Rm2, Rn2
6986 
8.0xf7+8.0x09+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_add
6987 
"dmach_add"
6988 
*am33
6989 
{
6990 
  int srcreg1, srcreg2, dstreg1, dstreg2;
6991 
  long temp, temp2, sum;
6992 
 
6993 
  PC = cia;
6994 
  srcreg1 = translate_rreg (SD_, RM1);
6995 
  srcreg2 = translate_rreg (SD_, RM2);
6996 
  dstreg1 = translate_rreg (SD_, RN1);
6997 
  dstreg2 = translate_rreg (SD_, RN2);
6998 
 
6999 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7000 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7001 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7002 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7003 
  sum = temp + temp2 + State.regs[REG_MCRL];
7004 
 
7005 
  State.regs[dstreg2] += State.regs[srcreg2];
7006 
  State.regs[dstreg1] = sum;
7007 
}
7008 
 
7009 
// 1111 0111 0001 1001 Rm1 Rn1 imm4 Rn2; dmach_add Rm1, Rn1, imm4, Rn2
7010 
8.0xf7+8.0x19+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_add
7011 
"dmach_add"
7012 
*am33
7013 
{
7014 
  int srcreg1, dstreg1, dstreg2;
7015 
  long temp, temp2, sum;
7016 
 
7017 
  PC = cia;
7018 
  srcreg1 = translate_rreg (SD_, RM1);
7019 
  dstreg1 = translate_rreg (SD_, RN1);
7020 
  dstreg2 = translate_rreg (SD_, RN2);
7021 
 
7022 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7023 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7024 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7025 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7026 
  sum = temp + temp2 + State.regs[REG_MCRL];
7027 
 
7028 
  State.regs[dstreg2] += EXTEND4 (IMM4);
7029 
  State.regs[dstreg1] = sum;
7030 
}
7031 
 
7032 
// 1111 0111 0010 1001 Rm1 Rn1 Rm2 Rn2; dmach_sub Rm1, Rn1, Rm2, Rn2
7033 
8.0xf7+8.0x29+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_sub
7034 
"dmach_sub"
7035 
*am33
7036 
{
7037 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7038 
  long temp, temp2, sum;
7039 
 
7040 
  PC = cia;
7041 
  srcreg1 = translate_rreg (SD_, RM1);
7042 
  srcreg2 = translate_rreg (SD_, RM2);
7043 
  dstreg1 = translate_rreg (SD_, RN1);
7044 
  dstreg2 = translate_rreg (SD_, RN2);
7045 
 
7046 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7047 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7048 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7049 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7050 
  sum = temp + temp2 + State.regs[REG_MCRL];
7051 
 
7052 
  State.regs[dstreg2] -= State.regs[srcreg2];
7053 
  State.regs[dstreg1] = sum;
7054 
}
7055 
 
7056 
// 1111 0111 0011 1001 Rm1 Rn1 imm4 Rn2; dmach_sub Rm1, Rn1, imm4, Rn2
7057 
8.0xf7+8.0x39+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_sub
7058 
"dmach_sub"
7059 
*am33
7060 
{
7061 
  int srcreg1, dstreg1, dstreg2;
7062 
  long temp, temp2, sum;
7063 
 
7064 
  PC = cia;
7065 
  srcreg1 = translate_rreg (SD_, RM1);
7066 
  dstreg1 = translate_rreg (SD_, RN1);
7067 
  dstreg2 = translate_rreg (SD_, RN2);
7068 
 
7069 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7070 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7071 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7072 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7073 
  sum = temp + temp2 + State.regs[REG_MCRL];
7074 
 
7075 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
7076 
  State.regs[dstreg1] = sum;
7077 
}
7078 
 
7079 
// 1111 0111 0100 1001 Rm1 Rn1 Rm2 Rn2; dmach_cmp Rm1, Rn1, Rm2, Rn2
7080 
8.0xf7+8.0x49+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_cmp
7081 
"dmach_cmp"
7082 
*am33
7083 
{
7084 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7085 
  long temp, temp2, sum;
7086 
 
7087 
  PC = cia;
7088 
  srcreg1 = translate_rreg (SD_, RM1);
7089 
  srcreg2 = translate_rreg (SD_, RM2);
7090 
  dstreg1 = translate_rreg (SD_, RN1);
7091 
  dstreg2 = translate_rreg (SD_, RN2);
7092 
 
7093 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7094 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7095 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7096 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7097 
  sum = temp + temp2 + State.regs[REG_MCRL];
7098 
 
7099 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7100 
  State.regs[dstreg1] = sum;
7101 
}
7102 
 
7103 
// 1111 0111 0101 1001 Rm1 Rn1 imm4 Rn2; dmach_cmp Rm1, Rn1, imm4, Rn2
7104 
8.0xf7+8.0x59+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_cmp
7105 
"dmach_cmp"
7106 
*am33
7107 
{
7108 
  int srcreg1, dstreg1, dstreg2;
7109 
  long temp, temp2, sum;
7110 
 
7111 
  PC = cia;
7112 
  srcreg1 = translate_rreg (SD_, RM1);
7113 
  dstreg1 = translate_rreg (SD_, RN1);
7114 
  dstreg2 = translate_rreg (SD_, RN2);
7115 
 
7116 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7117 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7118 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7119 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7120 
  sum = temp + temp2 + State.regs[REG_MCRL];
7121 
 
7122 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7123 
  State.regs[dstreg1] = sum;
7124 
}
7125 
 
7126 
// 1111 0111 0110 1001 Rm1 Rn1 Rm2 Rn2; dmach_mov Rm1, Rn1, Rm2, Rn2
7127 
8.0xf7+8.0x69+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_mov
7128 
"dmach_mov"
7129 
*am33
7130 
{
7131 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7132 
  long temp, temp2, sum;
7133 
 
7134 
  PC = cia;
7135 
  srcreg1 = translate_rreg (SD_, RM1);
7136 
  srcreg2 = translate_rreg (SD_, RM2);
7137 
  dstreg1 = translate_rreg (SD_, RN1);
7138 
  dstreg2 = translate_rreg (SD_, RN2);
7139 
 
7140 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7141 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7142 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7143 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7144 
  sum = temp + temp2 + State.regs[REG_MCRL];
7145 
 
7146 
  State.regs[dstreg2] = State.regs[srcreg2];
7147 
  State.regs[dstreg1] = sum;
7148 
}
7149 
 
7150 
// 1111 0111 0111 1001 Rm1 Rn1 imm4 Rn2; dmach_mov Rm1, Rn1, imm4, Rn2
7151 
8.0xf7+8.0x79+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_mov
7152 
"dmach_mov"
7153 
*am33
7154 
{
7155 
  int srcreg1, dstreg1, dstreg2;
7156 
  long temp, temp2, sum;
7157 
 
7158 
  PC = cia;
7159 
  srcreg1 = translate_rreg (SD_, RM1);
7160 
  dstreg1 = translate_rreg (SD_, RN1);
7161 
  dstreg2 = translate_rreg (SD_, RN2);
7162 
 
7163 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7164 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7165 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7166 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7167 
  sum = temp + temp2 + State.regs[REG_MCRL];
7168 
 
7169 
  State.regs[dstreg2] = EXTEND4 (IMM4);
7170 
  State.regs[dstreg1] = sum;
7171 
}
7172 
 
7173 
// 1111 0111 1000 1001 Rm1 Rn1 Rm2 Rn2; dmach_asr Rm1, Rn1, Rm2, Rn2
7174 
8.0xf7+8.0x89+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asr
7175 
"dmach_asr"
7176 
*am33
7177 
{
7178 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7179 
  long temp, temp2, sum;
7180 
 
7181 
  PC = cia;
7182 
  srcreg1 = translate_rreg (SD_, RM1);
7183 
  srcreg2 = translate_rreg (SD_, RM2);
7184 
  dstreg1 = translate_rreg (SD_, RN1);
7185 
  dstreg2 = translate_rreg (SD_, RN2);
7186 
 
7187 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7188 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7189 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7190 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7191 
  sum = temp + temp2 + State.regs[REG_MCRL];
7192 
 
7193 
  temp = State.regs[dstreg2];
7194 
  temp >>= State.regs[srcreg2];
7195 
  State.regs[dstreg2] = temp;
7196 
  State.regs[dstreg1] = sum;
7197 
}
7198 
 
7199 
// 1111 0111 1001 1001 Rm1 Rn1 imm4 Rn2; dmach_asr Rm1, Rn1, imm4, Rn2
7200 
8.0xf7+8.0x99+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asr
7201 
"dmach_asr"
7202 
*am33
7203 
{
7204 
  int srcreg1, dstreg1, dstreg2;
7205 
  long temp, temp2, sum;
7206 
 
7207 
  PC = cia;
7208 
  srcreg1 = translate_rreg (SD_, RM1);
7209 
  dstreg1 = translate_rreg (SD_, RN1);
7210 
  dstreg2 = translate_rreg (SD_, RN2);
7211 
 
7212 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7213 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7214 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7215 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7216 
  sum = temp + temp2 + State.regs[REG_MCRL];
7217 
 
7218 
  temp = State.regs[dstreg2];
7219 
  temp >>= IMM4;
7220 
  State.regs[dstreg2] = temp;
7221 
  State.regs[dstreg1] = sum;
7222 
}
7223 
 
7224 
// 1111 0111 1010 1001 Rm1 Rn1 Rm2 Rn2; dmach_lsr Rm1, Rn1, Rm2, Rn2
7225 
8.0xf7+8.0xa9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_lsr
7226 
"dmach_lsr"
7227 
*am33
7228 
{
7229 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7230 
  long temp, temp2, sum;
7231 
 
7232 
  PC = cia;
7233 
  srcreg1 = translate_rreg (SD_, RM1);
7234 
  srcreg2 = translate_rreg (SD_, RM2);
7235 
  dstreg1 = translate_rreg (SD_, RN1);
7236 
  dstreg2 = translate_rreg (SD_, RN2);
7237 
 
7238 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7239 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7240 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7241 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7242 
  sum = temp + temp2 + State.regs[REG_MCRL];
7243 
 
7244 
  State.regs[dstreg2] >>= State.regs[srcreg2];
7245 
  State.regs[dstreg1] = sum;
7246 
}
7247 
 
7248 
// 1111 0111 1011 1001 Rm1 Rn1 imm4 Rn2; dmach_lsr Rm1, Rn1, imm4, Rn2
7249 
8.0xf7+8.0xb9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_lsr
7250 
"dmach_lsr"
7251 
*am33
7252 
{
7253 
  int srcreg1, dstreg1, dstreg2;
7254 
  long temp, temp2, sum;
7255 
 
7256 
  PC = cia;
7257 
  srcreg1 = translate_rreg (SD_, RM1);
7258 
  dstreg1 = translate_rreg (SD_, RN1);
7259 
  dstreg2 = translate_rreg (SD_, RN2);
7260 
 
7261 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7262 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7263 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7264 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7265 
  sum = temp + temp2 + State.regs[REG_MCRL];
7266 
 
7267 
  State.regs[dstreg2] >>= IMM4;
7268 
  State.regs[dstreg1] = sum;
7269 
}
7270 
 
7271 
 
7272 
// 1111 0111 1100 1001 Rm1 Rn1 Rm2 Rn2; dmach_asl Rm1, Rn1, Rm2, Rn2
7273 
8.0xf7+8.0xc9+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::dmach_asl
7274 
"dmach_asl"
7275 
*am33
7276 
{
7277 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7278 
  long temp, temp2, sum;
7279 
 
7280 
  PC = cia;
7281 
  srcreg1 = translate_rreg (SD_, RM1);
7282 
  srcreg2 = translate_rreg (SD_, RM2);
7283 
  dstreg1 = translate_rreg (SD_, RN1);
7284 
  dstreg2 = translate_rreg (SD_, RN2);
7285 
 
7286 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7287 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7288 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7289 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7290 
  sum = temp + temp2 + State.regs[REG_MCRL];
7291 
 
7292 
  State.regs[dstreg2] <<= State.regs[srcreg2];
7293 
  State.regs[dstreg1] = sum;
7294 
}
7295 
 
7296 
// 1111 0111 1101 1001 Rm1 Rn1 imm4 Rn2; dmach_asl Rm1, Rn1, imm4, Rn2
7297 
8.0xf7+8.0xd9+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::dmach_asl
7298 
"dmach_asl"
7299 
*am33
7300 
{
7301 
  int srcreg1, dstreg1, dstreg2;
7302 
  long temp, temp2, sum;
7303 
 
7304 
  PC = cia;
7305 
  srcreg1 = translate_rreg (SD_, RM1);
7306 
  dstreg1 = translate_rreg (SD_, RN1);
7307 
  dstreg2 = translate_rreg (SD_, RN2);
7308 
 
7309 
  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
7310 
          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
7311 
  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
7312 
           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
7313 
  sum = temp + temp2 + State.regs[REG_MCRL];
7314 
 
7315 
  State.regs[dstreg2] <<= IMM4;
7316 
  State.regs[dstreg1] = sum;
7317 
}
7318 
 
7319 
// 1111 0111 0000 1010 Rm1 Rn1 Rm2 Rn2; xor_add Rm1, Rn1, Rm2, Rn2
7320 
8.0xf7+8.0x0a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_add
7321 
"xor_add"
7322 
*am33
7323 
{
7324 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7325 
  int result1;
7326 
 
7327 
  PC = cia;
7328 
  srcreg1 = translate_rreg (SD_, RM1);
7329 
  srcreg2 = translate_rreg (SD_, RM2);
7330 
  dstreg1 = translate_rreg (SD_, RN1);
7331 
  dstreg2 = translate_rreg (SD_, RN2);
7332 
 
7333 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7334 
  State.regs[dstreg2] += State.regs[srcreg2];
7335 
  State.regs[dstreg1] = result1;
7336 
}
7337 
 
7338 
// 1111 0111 0001 1010 Rm1 Rn1 imm4 Rn2; xor_add Rm1, Rn1, imm4, Rn2
7339 
8.0xf7+8.0x1a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_add
7340 
"xor_add"
7341 
*am33
7342 
{
7343 
  int srcreg1, dstreg1, dstreg2;
7344 
  int result1;
7345 
 
7346 
  PC = cia;
7347 
  srcreg1 = translate_rreg (SD_, RM1);
7348 
  dstreg1 = translate_rreg (SD_, RN1);
7349 
  dstreg2 = translate_rreg (SD_, RN2);
7350 
 
7351 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7352 
  State.regs[dstreg2] += EXTEND4 (IMM4);
7353 
  State.regs[dstreg1] = result1;
7354 
}
7355 
 
7356 
// 1111 0111 0010 1010 Rm1 Rn1 Rm2 Rn2; xor_sub Rm1, Rn1, Rm2, Rn2
7357 
8.0xf7+8.0x2a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_sub
7358 
"xor_sub"
7359 
*am33
7360 
{
7361 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7362 
  int result1;
7363 
 
7364 
  PC = cia;
7365 
  srcreg1 = translate_rreg (SD_, RM1);
7366 
  srcreg2 = translate_rreg (SD_, RM2);
7367 
  dstreg1 = translate_rreg (SD_, RN1);
7368 
  dstreg2 = translate_rreg (SD_, RN2);
7369 
 
7370 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7371 
  State.regs[dstreg2] -= State.regs[srcreg2];
7372 
  State.regs[dstreg1] = result1;
7373 
}
7374 
 
7375 
// 1111 0111 0011 1010 Rm1 Rn1 imm4 Rn2; xor_sub Rm1, Rn1, imm4, Rn2
7376 
8.0xf7+8.0x3a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_sub
7377 
"xor_sub"
7378 
*am33
7379 
{
7380 
  int srcreg1, dstreg1, dstreg2;
7381 
  int result1;
7382 
 
7383 
  PC = cia;
7384 
  srcreg1 = translate_rreg (SD_, RM1);
7385 
  dstreg1 = translate_rreg (SD_, RN1);
7386 
  dstreg2 = translate_rreg (SD_, RN2);
7387 
 
7388 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7389 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
7390 
  State.regs[dstreg1] = result1;
7391 
}
7392 
 
7393 
// 1111 0111 0100 1010 Rm1 Rn1 Rm2 Rn2; xor_cmp Rm1, Rn1, Rm2, Rn2
7394 
8.0xf7+8.0x4a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_cmp
7395 
"xor_cmp"
7396 
*am33
7397 
{
7398 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7399 
 
7400 
  PC = cia;
7401 
  srcreg1 = translate_rreg (SD_, RM1);
7402 
  srcreg2 = translate_rreg (SD_, RM2);
7403 
  dstreg1 = translate_rreg (SD_, RN1);
7404 
  dstreg2 = translate_rreg (SD_, RN2);
7405 
 
7406 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7407 
  State.regs[dstreg1] ^= State.regs[srcreg1];
7408 
}
7409 
 
7410 
// 1111 0111 0101 1010 Rm1 Rn1 imm4 Rn2; xor_cmp Rm1, Rn1, imm4, Rn2
7411 
8.0xf7+8.0x5a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_cmp
7412 
"xor_cmp"
7413 
*am33
7414 
{
7415 
  int srcreg1, dstreg1, dstreg2;
7416 
 
7417 
  PC = cia;
7418 
  srcreg1 = translate_rreg (SD_, RM1);
7419 
  dstreg1 = translate_rreg (SD_, RN1);
7420 
  dstreg2 = translate_rreg (SD_, RN2);
7421 
 
7422 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7423 
  State.regs[dstreg1] ^= State.regs[srcreg1];
7424 
}
7425 
 
7426 
// 1111 0111 0110 1010 Rm1 Rn1 Rm2 Rn2; xor_mov Rm1, Rn1, Rm2, Rn2
7427 
8.0xf7+8.0x6a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_mov
7428 
"xor_mov"
7429 
*am33
7430 
{
7431 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7432 
  int result1;
7433 
 
7434 
  PC = cia;
7435 
  srcreg1 = translate_rreg (SD_, RM1);
7436 
  srcreg2 = translate_rreg (SD_, RM2);
7437 
  dstreg1 = translate_rreg (SD_, RN1);
7438 
  dstreg2 = translate_rreg (SD_, RN2);
7439 
 
7440 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7441 
  State.regs[dstreg2] = State.regs[srcreg2];
7442 
  State.regs[dstreg1] = result1;
7443 
}
7444 
 
7445 
// 1111 0111 0111 1010 Rm1 Rn1 imm4 Rn2; xor_mov Rm1, Rn1, imm4, Rn2
7446 
8.0xf7+8.0x7a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_mov
7447 
"xor_mov"
7448 
*am33
7449 
{
7450 
  int srcreg1, dstreg1, dstreg2;
7451 
  int result1;
7452 
 
7453 
  PC = cia;
7454 
  srcreg1 = translate_rreg (SD_, RM1);
7455 
  dstreg1 = translate_rreg (SD_, RN1);
7456 
  dstreg2 = translate_rreg (SD_, RN2);
7457 
 
7458 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7459 
  State.regs[dstreg2] = EXTEND4 (IMM4);
7460 
  State.regs[dstreg1] = result1;
7461 
}
7462 
 
7463 
// 1111 0111 1000 1010 Rm1 Rn1 Rm2 Rn2; xor_asr Rm1, Rn1, Rm2, Rn2
7464 
8.0xf7+8.0x8a+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asr
7465 
"xor_asr"
7466 
*am33
7467 
{
7468 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7469 
  int result1;
7470 
  signed int temp;
7471 
 
7472 
  PC = cia;
7473 
  srcreg1 = translate_rreg (SD_, RM1);
7474 
  srcreg2 = translate_rreg (SD_, RM2);
7475 
  dstreg1 = translate_rreg (SD_, RN1);
7476 
  dstreg2 = translate_rreg (SD_, RN2);
7477 
 
7478 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7479 
  temp = State.regs[dstreg2];
7480 
  temp >>= State.regs[srcreg2];
7481 
  State.regs[dstreg2] = temp;
7482 
  State.regs[dstreg1] = result1;
7483 
}
7484 
 
7485 
// 1111 0111 1001 1010 Rm1 Rn1 imm4 Rn2; xor_asr Rm1, Rn1, imm4, Rn2
7486 
8.0xf7+8.0x9a+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asr
7487 
"xor_asr"
7488 
*am33
7489 
{
7490 
  int srcreg1, dstreg1, dstreg2;
7491 
  int result1;
7492 
  signed int temp;
7493 
 
7494 
  PC = cia;
7495 
  srcreg1 = translate_rreg (SD_, RM1);
7496 
  dstreg1 = translate_rreg (SD_, RN1);
7497 
  dstreg2 = translate_rreg (SD_, RN2);
7498 
 
7499 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7500 
  temp = State.regs[dstreg2];
7501 
  temp >>= IMM4;
7502 
  State.regs[dstreg2] = temp;
7503 
  State.regs[dstreg1] = result1;
7504 
}
7505 
 
7506 
// 1111 0111 1010 1010 Rm1 Rn1 Rm2 Rn2; xor_lsr Rm1, Rn1, Rm2, Rn2
7507 
8.0xf7+8.0xaa+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_lsr
7508 
"xor_lsr"
7509 
*am33
7510 
{
7511 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7512 
  int result1;
7513 
 
7514 
  PC = cia;
7515 
  srcreg1 = translate_rreg (SD_, RM1);
7516 
  srcreg2 = translate_rreg (SD_, RM2);
7517 
  dstreg1 = translate_rreg (SD_, RN1);
7518 
  dstreg2 = translate_rreg (SD_, RN2);
7519 
 
7520 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7521 
  State.regs[dstreg2] >>= State.regs[srcreg2];
7522 
  State.regs[dstreg1] = result1;
7523 
}
7524 
 
7525 
// 1111 0111 1011 1010 Rm1 Rn1 imm4 Rn2; xor_lsr Rm1, Rn1, imm4, Rn2
7526 
8.0xf7+8.0xba+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_lsr
7527 
"xor_lsr"
7528 
*am33
7529 
{
7530 
  int srcreg1, dstreg1, dstreg2;
7531 
  int result1;
7532 
  signed int temp;
7533 
 
7534 
  PC = cia;
7535 
  srcreg1 = translate_rreg (SD_, RM1);
7536 
  dstreg1 = translate_rreg (SD_, RN1);
7537 
  dstreg2 = translate_rreg (SD_, RN2);
7538 
 
7539 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7540 
  State.regs[dstreg2] >>= IMM4;
7541 
  State.regs[dstreg1] = result1;
7542 
}
7543 
 
7544 
 
7545 
// 1111 0111 1100 1010 Rm1 Rn1 Rm2 Rn2; xor_asl Rm1, Rn1, Rm2, Rn2
7546 
8.0xf7+8.0xca+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::xor_asl
7547 
"xor_asl"
7548 
*am33
7549 
{
7550 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7551 
  int result1;
7552 
 
7553 
  PC = cia;
7554 
  srcreg1 = translate_rreg (SD_, RM1);
7555 
  srcreg2 = translate_rreg (SD_, RM2);
7556 
  dstreg1 = translate_rreg (SD_, RN1);
7557 
  dstreg2 = translate_rreg (SD_, RN2);
7558 
 
7559 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7560 
  State.regs[dstreg2] <<= State.regs[srcreg2];
7561 
  State.regs[dstreg1] = result1;
7562 
}
7563 
 
7564 
// 1111 0111 1101 1010 Rm1 Rn1 imm4 Rn2; xor_asl Rm1, Rn1, imm4, Rn2
7565 
8.0xf7+8.0xda+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::xor_asl
7566 
"xor_asl"
7567 
*am33
7568 
{
7569 
  int srcreg1, dstreg1, dstreg2;
7570 
  int result1;
7571 
  signed int temp;
7572 
 
7573 
  PC = cia;
7574 
  srcreg1 = translate_rreg (SD_, RM1);
7575 
  dstreg1 = translate_rreg (SD_, RN1);
7576 
  dstreg2 = translate_rreg (SD_, RN2);
7577 
 
7578 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7579 
  State.regs[dstreg2] <<= IMM4;
7580 
  State.regs[dstreg1] = result1;
7581 
}
7582 
 
7583 
// 1111 0111 0000 1011 Rm1 Rn1 Rm2 Rn2; swhw_add Rm1, Rn1, Rm2, Rn2
7584 
8.0xf7+8.0x0b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_add
7585 
"swhw_add"
7586 
*am33
7587 
{
7588 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7589 
  int result1;
7590 
 
7591 
  PC = cia;
7592 
  srcreg1 = translate_rreg (SD_, RM1);
7593 
  srcreg2 = translate_rreg (SD_, RM2);
7594 
  dstreg1 = translate_rreg (SD_, RN1);
7595 
  dstreg2 = translate_rreg (SD_, RN2);
7596 
 
7597 
  result1 = State.regs[dstreg1] ^ State.regs[srcreg1];
7598 
  State.regs[dstreg2] += State.regs[srcreg2];
7599 
  State.regs[dstreg1] = result1;
7600 
}
7601 
 
7602 
// 1111 0111 0001 1011 Rm1 Rn1 imm4 Rn2; swhw_add Rm1, Rn1, imm4, Rn2
7603 
8.0xf7+8.0x1b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_add
7604 
"swhw_add"
7605 
*am33
7606 
{
7607 
  int srcreg1, dstreg1, dstreg2;
7608 
  int result1;
7609 
 
7610 
  PC = cia;
7611 
  srcreg1 = translate_rreg (SD_, RM1);
7612 
  dstreg1 = translate_rreg (SD_, RN1);
7613 
  dstreg2 = translate_rreg (SD_, RN2);
7614 
 
7615 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7616 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7617 
  State.regs[dstreg2] += EXTEND4 (IMM4);
7618 
  State.regs[dstreg1] = result1;
7619 
}
7620 
 
7621 
// 1111 0111 0010 1011 Rm1 Rn1 Rm2 Rn2; swhw_sub Rm1, Rn1, Rm2, Rn2
7622 
8.0xf7+8.0x2b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_sub
7623 
"swhw_sub"
7624 
*am33
7625 
{
7626 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7627 
  int result1;
7628 
 
7629 
  PC = cia;
7630 
  srcreg1 = translate_rreg (SD_, RM1);
7631 
  srcreg2 = translate_rreg (SD_, RM2);
7632 
  dstreg1 = translate_rreg (SD_, RN1);
7633 
  dstreg2 = translate_rreg (SD_, RN2);
7634 
 
7635 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7636 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7637 
  State.regs[dstreg2] -= State.regs[srcreg2];
7638 
  State.regs[dstreg1] = result1;
7639 
}
7640 
 
7641 
// 1111 0111 0011 1011 Rm1 Rn1 imm4 Rn2; swhw_sub Rm1, Rn1, imm4, Rn2
7642 
8.0xf7+8.0x3b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_sub
7643 
"swhw_sub"
7644 
*am33
7645 
{
7646 
  int srcreg1, dstreg1, dstreg2;
7647 
  int result1;
7648 
 
7649 
  PC = cia;
7650 
  srcreg1 = translate_rreg (SD_, RM1);
7651 
  dstreg1 = translate_rreg (SD_, RN1);
7652 
  dstreg2 = translate_rreg (SD_, RN2);
7653 
 
7654 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7655 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7656 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
7657 
  State.regs[dstreg1] = result1;
7658 
}
7659 
 
7660 
// 1111 0111 0100 1011 Rm1 Rn1 Rm2 Rn2; swhw_cmp Rm1, Rn1, Rm2, Rn2
7661 
8.0xf7+8.0x4b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_cmp
7662 
"swhw_cmp"
7663 
*am33
7664 
{
7665 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7666 
 
7667 
  PC = cia;
7668 
  srcreg1 = translate_rreg (SD_, RM1);
7669 
  srcreg2 = translate_rreg (SD_, RM2);
7670 
  dstreg1 = translate_rreg (SD_, RN1);
7671 
  dstreg2 = translate_rreg (SD_, RN2);
7672 
 
7673 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7674 
  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7675 
                         | ((State.regs[srcreg1] >> 16) & 0xffff));
7676 
}
7677 
 
7678 
// 1111 0111 0101 1011 Rm1 Rn1 imm4 Rn2; swhw_cmp Rm1, Rn1, imm4, Rn2
7679 
8.0xf7+8.0x5b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_cmp
7680 
"swhw_cmp"
7681 
*am33
7682 
{
7683 
  int srcreg1, dstreg1, dstreg2;
7684 
 
7685 
  PC = cia;
7686 
  srcreg1 = translate_rreg (SD_, RM1);
7687 
  dstreg1 = translate_rreg (SD_, RN1);
7688 
  dstreg2 = translate_rreg (SD_, RN2);
7689 
 
7690 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7691 
  State.regs[dstreg1] = (((State.regs[srcreg1] & 0xffff) << 16)
7692 
                         | ((State.regs[srcreg1] >> 16) & 0xffff));
7693 
}
7694 
 
7695 
// 1111 0111 0110 1011 Rm1 Rn1 Rm2 Rn2; swhw_mov Rm1, Rn1, Rm2, Rn2
7696 
8.0xf7+8.0x6b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_mov
7697 
"swhw_mov"
7698 
*am33
7699 
{
7700 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7701 
  int result1;
7702 
 
7703 
  PC = cia;
7704 
  srcreg1 = translate_rreg (SD_, RM1);
7705 
  srcreg2 = translate_rreg (SD_, RM2);
7706 
  dstreg1 = translate_rreg (SD_, RN1);
7707 
  dstreg2 = translate_rreg (SD_, RN2);
7708 
 
7709 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7710 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7711 
  State.regs[dstreg2] = State.regs[srcreg2];
7712 
  State.regs[dstreg1] = result1;
7713 
}
7714 
 
7715 
// 1111 0111 0111 1011 Rm1 Rn1 imm4 Rn2; swhw_mov Rm1, Rn1, imm4, Rn2
7716 
8.0xf7+8.0x7b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_mov
7717 
"swhw_mov"
7718 
*am33
7719 
{
7720 
  int srcreg1, dstreg1, dstreg2;
7721 
  int result1;
7722 
 
7723 
  PC = cia;
7724 
  srcreg1 = translate_rreg (SD_, RM1);
7725 
  dstreg1 = translate_rreg (SD_, RN1);
7726 
  dstreg2 = translate_rreg (SD_, RN2);
7727 
 
7728 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7729 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7730 
  State.regs[dstreg2] = EXTEND4 (IMM4);
7731 
  State.regs[dstreg1] = result1;
7732 
}
7733 
 
7734 
// 1111 0111 1000 1011 Rm1 Rn1 Rm2 Rn2; swhw_asr Rm1, Rn1, Rm2, Rn2
7735 
8.0xf7+8.0x8b+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asr
7736 
"swhw_asr"
7737 
*am33
7738 
{
7739 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7740 
  int result1;
7741 
  signed int temp;
7742 
 
7743 
  PC = cia;
7744 
  srcreg1 = translate_rreg (SD_, RM1);
7745 
  srcreg2 = translate_rreg (SD_, RM2);
7746 
  dstreg1 = translate_rreg (SD_, RN1);
7747 
  dstreg2 = translate_rreg (SD_, RN2);
7748 
 
7749 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7750 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7751 
  temp = State.regs[dstreg2];
7752 
  temp >>= State.regs[srcreg2];
7753 
  State.regs[dstreg2] = temp;
7754 
  State.regs[dstreg1] = result1;
7755 
}
7756 
 
7757 
// 1111 0111 1001 1011 Rm1 Rn1 imm4 Rn2; swhw_asr Rm1, Rn1, imm4, Rn2
7758 
8.0xf7+8.0x9b+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asr
7759 
"swhw_asr"
7760 
*am33
7761 
{
7762 
  int srcreg1, dstreg1, dstreg2;
7763 
  int result1;
7764 
  signed int temp;
7765 
 
7766 
  PC = cia;
7767 
  srcreg1 = translate_rreg (SD_, RM1);
7768 
  dstreg1 = translate_rreg (SD_, RN1);
7769 
  dstreg2 = translate_rreg (SD_, RN2);
7770 
 
7771 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7772 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7773 
  temp = State.regs[dstreg2];
7774 
  temp >>= IMM4;
7775 
  State.regs[dstreg2] = temp;
7776 
  State.regs[dstreg1] = result1;
7777 
}
7778 
 
7779 
// 1111 0111 1010 1011 Rm1 Rn1 Rm2 Rn2; swhw_lsr Rm1, Rn1, Rm2, Rn2
7780 
8.0xf7+8.0xab+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_lsr
7781 
"swhw_lsr"
7782 
*am33
7783 
{
7784 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7785 
  int result1;
7786 
 
7787 
  PC = cia;
7788 
  srcreg1 = translate_rreg (SD_, RM1);
7789 
  srcreg2 = translate_rreg (SD_, RM2);
7790 
  dstreg1 = translate_rreg (SD_, RN1);
7791 
  dstreg2 = translate_rreg (SD_, RN2);
7792 
 
7793 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7794 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7795 
  State.regs[dstreg2] >>= State.regs[srcreg2];
7796 
  State.regs[dstreg1] = result1;
7797 
}
7798 
 
7799 
// 1111 0111 1011 1011 Rm1 Rn1 imm4 Rn2; swhw_lsr Rm1, Rn1, imm4, Rn2
7800 
8.0xf7+8.0xbb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_lsr
7801 
"swhw_lsr"
7802 
*am33
7803 
{
7804 
  int srcreg1, dstreg1, dstreg2;
7805 
  int result1;
7806 
  signed int temp;
7807 
 
7808 
  PC = cia;
7809 
  srcreg1 = translate_rreg (SD_, RM1);
7810 
  dstreg1 = translate_rreg (SD_, RN1);
7811 
  dstreg2 = translate_rreg (SD_, RN2);
7812 
 
7813 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7814 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7815 
  State.regs[dstreg2] >>= IMM4;
7816 
  State.regs[dstreg1] = result1;
7817 
}
7818 
 
7819 
 
7820 
// 1111 0111 1100 1011 Rm1 Rn1 Rm2 Rn2; swhw_asl Rm1, Rn1, Rm2, Rn2
7821 
8.0xf7+8.0xcb+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::swhw_asl
7822 
"swhw_asl"
7823 
*am33
7824 
{
7825 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7826 
  int result1;
7827 
 
7828 
  PC = cia;
7829 
  srcreg1 = translate_rreg (SD_, RM1);
7830 
  srcreg2 = translate_rreg (SD_, RM2);
7831 
  dstreg1 = translate_rreg (SD_, RN1);
7832 
  dstreg2 = translate_rreg (SD_, RN2);
7833 
 
7834 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7835 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7836 
  State.regs[dstreg2] <<= State.regs[srcreg2];
7837 
  State.regs[dstreg1] = result1;
7838 
}
7839 
 
7840 
// 1111 0111 1101 1011 Rm1 Rn1 imm4 Rn2; swhw_asl Rm1, Rn1, imm4, Rn2
7841 
8.0xf7+8.0xdb+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::swhw_asl
7842 
"swhw_asl"
7843 
*am33
7844 
{
7845 
  int srcreg1, dstreg1, dstreg2;
7846 
  int result1;
7847 
  signed int temp;
7848 
 
7849 
  PC = cia;
7850 
  srcreg1 = translate_rreg (SD_, RM1);
7851 
  dstreg1 = translate_rreg (SD_, RN1);
7852 
  dstreg2 = translate_rreg (SD_, RN2);
7853 
 
7854 
  result1 = (((State.regs[srcreg1] & 0xffff) << 16)
7855 
               | ((State.regs[srcreg1] >> 16) & 0xffff));
7856 
  State.regs[dstreg2] <<= IMM4;
7857 
  State.regs[dstreg1] = result1;
7858 
}
7859 
 
7860 
// 1111 0111 0000 1100 Rm1 Rn1 Rm2 Rn2; or_add Rm1, Rn1, Rm2, Rn2
7861 
8.0xf7+8.0x0c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_add
7862 
"or_add"
7863 
*am33
7864 
{
7865 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7866 
  int result1;
7867 
 
7868 
  PC = cia;
7869 
  srcreg1 = translate_rreg (SD_, RM1);
7870 
  srcreg2 = translate_rreg (SD_, RM2);
7871 
  dstreg1 = translate_rreg (SD_, RN1);
7872 
  dstreg2 = translate_rreg (SD_, RN2);
7873 
 
7874 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
7875 
  State.regs[dstreg2] += State.regs[srcreg2];
7876 
  State.regs[dstreg1] = result1;
7877 
}
7878 
 
7879 
// 1111 0111 0001 1100 Rm1 Rn1 imm4 Rn2; or_add Rm1, Rn1, imm4, Rn2
7880 
8.0xf7+8.0x1c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_add
7881 
"or_add"
7882 
*am33
7883 
{
7884 
  int srcreg1, dstreg1, dstreg2;
7885 
  int result1;
7886 
 
7887 
  PC = cia;
7888 
  srcreg1 = translate_rreg (SD_, RM1);
7889 
  dstreg1 = translate_rreg (SD_, RN1);
7890 
  dstreg2 = translate_rreg (SD_, RN2);
7891 
 
7892 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
7893 
  State.regs[dstreg2] += EXTEND4 (IMM4);
7894 
  State.regs[dstreg1] = result1;
7895 
}
7896 
 
7897 
// 1111 0111 0010 1100 Rm1 Rn1 Rm2 Rn2; or_sub Rm1, Rn1, Rm2, Rn2
7898 
8.0xf7+8.0x2c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_sub
7899 
"or_sub"
7900 
*am33
7901 
{
7902 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7903 
  int result1;
7904 
 
7905 
  PC = cia;
7906 
  srcreg1 = translate_rreg (SD_, RM1);
7907 
  srcreg2 = translate_rreg (SD_, RM2);
7908 
  dstreg1 = translate_rreg (SD_, RN1);
7909 
  dstreg2 = translate_rreg (SD_, RN2);
7910 
 
7911 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
7912 
  State.regs[dstreg2] -= State.regs[srcreg2];
7913 
  State.regs[dstreg1] = result1;
7914 
}
7915 
 
7916 
// 1111 0111 0011 1100 Rm1 Rn1 imm4 Rn2; or_sub Rm1, Rn1, imm4, Rn2
7917 
8.0xf7+8.0x3c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_sub
7918 
"or_sub"
7919 
*am33
7920 
{
7921 
  int srcreg1, dstreg1, dstreg2;
7922 
  int result1;
7923 
 
7924 
  PC = cia;
7925 
  srcreg1 = translate_rreg (SD_, RM1);
7926 
  dstreg1 = translate_rreg (SD_, RN1);
7927 
  dstreg2 = translate_rreg (SD_, RN2);
7928 
 
7929 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
7930 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
7931 
  State.regs[dstreg1] = result1;
7932 
}
7933 
 
7934 
// 1111 0111 0100 1100 Rm1 Rn1 Rm2 Rn2; or_cmp Rm1, Rn1, Rm2, Rn2
7935 
8.0xf7+8.0x4c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_cmp
7936 
"or_cmp"
7937 
*am33
7938 
{
7939 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7940 
 
7941 
  PC = cia;
7942 
  srcreg1 = translate_rreg (SD_, RM1);
7943 
  srcreg2 = translate_rreg (SD_, RM2);
7944 
  dstreg1 = translate_rreg (SD_, RN1);
7945 
  dstreg2 = translate_rreg (SD_, RN2);
7946 
 
7947 
  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
7948 
  State.regs[dstreg1] |= State.regs[srcreg1];
7949 
}
7950 
 
7951 
// 1111 0111 0101 1100 Rm1 Rn1 imm4 Rn2; or_cmp Rm1, Rn1, imm4, Rn2
7952 
8.0xf7+8.0x5c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_cmp
7953 
"or_cmp"
7954 
*am33
7955 
{
7956 
  int srcreg1, dstreg1, dstreg2;
7957 
 
7958 
  PC = cia;
7959 
  srcreg1 = translate_rreg (SD_, RM1);
7960 
  dstreg1 = translate_rreg (SD_, RN1);
7961 
  dstreg2 = translate_rreg (SD_, RN2);
7962 
 
7963 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
7964 
  State.regs[dstreg1] |= State.regs[srcreg1];
7965 
}
7966 
 
7967 
// 1111 0111 0110 1100 Rm1 Rn1 Rm2 Rn2; or_mov Rm1, Rn1, Rm2, Rn2
7968 
8.0xf7+8.0x6c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_mov
7969 
"or_mov"
7970 
*am33
7971 
{
7972 
  int srcreg1, srcreg2, dstreg1, dstreg2;
7973 
  int result1;
7974 
 
7975 
  PC = cia;
7976 
  srcreg1 = translate_rreg (SD_, RM1);
7977 
  srcreg2 = translate_rreg (SD_, RM2);
7978 
  dstreg1 = translate_rreg (SD_, RN1);
7979 
  dstreg2 = translate_rreg (SD_, RN2);
7980 
 
7981 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
7982 
  State.regs[dstreg2] = State.regs[srcreg2];
7983 
  State.regs[dstreg1] = result1;
7984 
}
7985 
 
7986 
// 1111 0111 0111 1100 Rm1 Rn1 imm4 Rn2; or_mov Rm1, Rn1, imm4, Rn2
7987 
8.0xf7+8.0x7c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_mov
7988 
"or_mov"
7989 
*am33
7990 
{
7991 
  int srcreg1, dstreg1, dstreg2;
7992 
  int result1;
7993 
 
7994 
  PC = cia;
7995 
  srcreg1 = translate_rreg (SD_, RM1);
7996 
  dstreg1 = translate_rreg (SD_, RN1);
7997 
  dstreg2 = translate_rreg (SD_, RN2);
7998 
 
7999 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
8000 
  State.regs[dstreg2] = EXTEND4 (IMM4);
8001 
  State.regs[dstreg1] = result1;
8002 
}
8003 
 
8004 
// 1111 0111 1000 1100 Rm1 Rn1 Rm2 Rn2; or_asr Rm1, Rn1, Rm2, Rn2
8005 
8.0xf7+8.0x8c+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asr
8006 
"or_asr"
8007 
*am33
8008 
{
8009 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8010 
  int result1;
8011 
  signed int temp;
8012 
 
8013 
  PC = cia;
8014 
  srcreg1 = translate_rreg (SD_, RM1);
8015 
  srcreg2 = translate_rreg (SD_, RM2);
8016 
  dstreg1 = translate_rreg (SD_, RN1);
8017 
  dstreg2 = translate_rreg (SD_, RN2);
8018 
 
8019 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
8020 
  temp = State.regs[dstreg2];
8021 
  temp >>= State.regs[srcreg2];
8022 
  State.regs[dstreg2] = temp;
8023 
  State.regs[dstreg1] = result1;
8024 
}
8025 
 
8026 
// 1111 0111 1001 1100 Rm1 Rn1 imm4 Rn2; or_asr Rm1, Rn1, imm4, Rn2
8027 
8.0xf7+8.0x9c+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asr
8028 
"or_asr"
8029 
*am33
8030 
{
8031 
  int srcreg1, dstreg1, dstreg2;
8032 
  int result1;
8033 
  signed int temp;
8034 
 
8035 
  PC = cia;
8036 
  srcreg1 = translate_rreg (SD_, RM1);
8037 
  dstreg1 = translate_rreg (SD_, RN1);
8038 
  dstreg2 = translate_rreg (SD_, RN2);
8039 
 
8040 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
8041 
  temp = State.regs[dstreg2];
8042 
  temp >>= IMM4;
8043 
  State.regs[dstreg2] = temp;
8044 
  State.regs[dstreg1] = result1;
8045 
}
8046 
 
8047 
// 1111 0111 1010 1100 Rm1 Rn1 Rm2 Rn2; or_lsr Rm1, Rn1, Rm2, Rn2
8048 
8.0xf7+8.0xac+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_lsr
8049 
"or_lsr"
8050 
*am33
8051 
{
8052 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8053 
  int result1;
8054 
 
8055 
  PC = cia;
8056 
  srcreg1 = translate_rreg (SD_, RM1);
8057 
  srcreg2 = translate_rreg (SD_, RM2);
8058 
  dstreg1 = translate_rreg (SD_, RN1);
8059 
  dstreg2 = translate_rreg (SD_, RN2);
8060 
 
8061 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
8062 
  State.regs[dstreg2] >>= State.regs[srcreg2];
8063 
  State.regs[dstreg1] = result1;
8064 
}
8065 
 
8066 
// 1111 0111 1011 1100 Rm1 Rn1 imm4 Rn2; or_lsr Rm1, Rn1, imm4, Rn2
8067 
8.0xf7+8.0xbc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_lsr
8068 
"or_lsr"
8069 
*am33
8070 
{
8071 
  int srcreg1, dstreg1, dstreg2;
8072 
  int result1;
8073 
  signed int temp;
8074 
 
8075 
  PC = cia;
8076 
  srcreg1 = translate_rreg (SD_, RM1);
8077 
  dstreg1 = translate_rreg (SD_, RN1);
8078 
  dstreg2 = translate_rreg (SD_, RN2);
8079 
 
8080 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
8081 
  State.regs[dstreg2] >>= IMM4;
8082 
  State.regs[dstreg1] = result1;
8083 
}
8084 
 
8085 
 
8086 
// 1111 0111 1100 1100 Rm1 Rn1 Rm2 Rn2; or_asl Rm1, Rn1, Rm2, Rn2
8087 
8.0xf7+8.0xcc+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::or_asl
8088 
"or_asl"
8089 
*am33
8090 
{
8091 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8092 
  int result1;
8093 
 
8094 
  PC = cia;
8095 
  srcreg1 = translate_rreg (SD_, RM1);
8096 
  srcreg2 = translate_rreg (SD_, RM2);
8097 
  dstreg1 = translate_rreg (SD_, RN1);
8098 
  dstreg2 = translate_rreg (SD_, RN2);
8099 
 
8100 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
8101 
  State.regs[dstreg2] <<= State.regs[srcreg2];
8102 
  State.regs[dstreg1] = result1;
8103 
}
8104 
 
8105 
// 1111 0111 1101 1100 Rm1 Rn1 imm4 Rn2; or_asl Rm1, Rn1, imm4, Rn2
8106 
8.0xf7+8.0xdc+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::or_asl
8107 
"or_asl"
8108 
*am33
8109 
{
8110 
  int srcreg1, dstreg1, dstreg2;
8111 
  int result1;
8112 
  signed int temp;
8113 
 
8114 
  PC = cia;
8115 
  srcreg1 = translate_rreg (SD_, RM1);
8116 
  dstreg1 = translate_rreg (SD_, RN1);
8117 
  dstreg2 = translate_rreg (SD_, RN2);
8118 
 
8119 
  result1 = State.regs[dstreg1] | State.regs[srcreg1];
8120 
  State.regs[dstreg2] <<= IMM4;
8121 
  State.regs[dstreg1] = result1;
8122 
}
8123 
 
8124 
// 1111 0111 0000 1101 Rm1 Rn1 Rm2 Rn2; sat16_add Rm1, Rn1, Rm2, Rn2
8125 
8.0xf7+8.0x0d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_add
8126 
"sat16_add"
8127 
*am33
8128 
{
8129 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8130 
  int result1;
8131 
 
8132 
  PC = cia;
8133 
  srcreg1 = translate_rreg (SD_, RM1);
8134 
  srcreg2 = translate_rreg (SD_, RM2);
8135 
  dstreg1 = translate_rreg (SD_, RN1);
8136 
  dstreg2 = translate_rreg (SD_, RN2);
8137 
 
8138 
  if (State.regs[srcreg1] >= 0x7fff)
8139 
    result1 = 0x7fff;
8140 
  else if (State.regs[srcreg1] <= 0xffff8000)
8141 
    result1 = 0xffff8000;
8142 
  else
8143 
    result1 = State.regs[srcreg1];
8144 
 
8145 
  State.regs[dstreg2] += State.regs[srcreg2];
8146 
  State.regs[dstreg1] = result1;
8147 
}
8148 
 
8149 
// 1111 0111 0001 1101 Rm1 Rn1 imm4 Rn2; sat16_add Rm1, Rn1, imm4, Rn2
8150 
8.0xf7+8.0x1d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_add
8151 
"sat16_add"
8152 
*am33
8153 
{
8154 
  int srcreg1, dstreg1, dstreg2;
8155 
  int result1;
8156 
 
8157 
  PC = cia;
8158 
  srcreg1 = translate_rreg (SD_, RM1);
8159 
  dstreg1 = translate_rreg (SD_, RN1);
8160 
  dstreg2 = translate_rreg (SD_, RN2);
8161 
 
8162 
  if (State.regs[srcreg1] >= 0x7fff)
8163 
    result1 = 0x7fff;
8164 
  else if (State.regs[srcreg1] <= 0xffff8000)
8165 
    result1 = 0xffff8000;
8166 
  else
8167 
    result1 = State.regs[srcreg1];
8168 
 
8169 
  State.regs[dstreg2] += EXTEND4 (IMM4);
8170 
  State.regs[dstreg1] = result1;
8171 
}
8172 
 
8173 
// 1111 0111 0010 1101 Rm1 Rn1 Rm2 Rn2; sat16_sub Rm1, Rn1, Rm2, Rn2
8174 
8.0xf7+8.0x2d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_sub
8175 
"sat16_sub"
8176 
*am33
8177 
{
8178 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8179 
  int result1;
8180 
 
8181 
  PC = cia;
8182 
  srcreg1 = translate_rreg (SD_, RM1);
8183 
  srcreg2 = translate_rreg (SD_, RM2);
8184 
  dstreg1 = translate_rreg (SD_, RN1);
8185 
  dstreg2 = translate_rreg (SD_, RN2);
8186 
 
8187 
  if (State.regs[srcreg1] >= 0x7fff)
8188 
    result1 = 0x7fff;
8189 
  else if (State.regs[srcreg1] <= 0xffff8000)
8190 
    result1 = 0xffff8000;
8191 
  else
8192 
    result1 = State.regs[srcreg1];
8193 
 
8194 
  State.regs[dstreg2] -= State.regs[srcreg2];
8195 
  State.regs[dstreg1] = result1;
8196 
}
8197 
 
8198 
// 1111 0111 0011 1101 Rm1 Rn1 imm4 Rn2; sat16_sub Rm1, Rn1, imm4, Rn2
8199 
8.0xf7+8.0x3d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_sub
8200 
"sat16_sub"
8201 
*am33
8202 
{
8203 
  int srcreg1, dstreg1, dstreg2;
8204 
  int result1;
8205 
 
8206 
  PC = cia;
8207 
  srcreg1 = translate_rreg (SD_, RM1);
8208 
  dstreg1 = translate_rreg (SD_, RN1);
8209 
  dstreg2 = translate_rreg (SD_, RN2);
8210 
 
8211 
  if (State.regs[srcreg1] >= 0x7fff)
8212 
    result1 = 0x7fff;
8213 
  else if (State.regs[srcreg1] <= 0xffff8000)
8214 
    result1 = 0xffff8000;
8215 
  else
8216 
    result1 = State.regs[srcreg1];
8217 
 
8218 
  State.regs[dstreg2] -= EXTEND4 (IMM4);
8219 
  State.regs[dstreg1] = result1;
8220 
}
8221 
 
8222 
// 1111 0111 0100 1101 Rm1 Rn1 Rm2 Rn2; sat16_cmp Rm1, Rn1, Rm2, Rn2
8223 
8.0xf7+8.0x4d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_cmp
8224 
"sat16_cmp"
8225 
*am33
8226 
{
8227 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8228 
  int result1;
8229 
 
8230 
  PC = cia;
8231 
  srcreg1 = translate_rreg (SD_, RM1);
8232 
  srcreg2 = translate_rreg (SD_, RM2);
8233 
  dstreg1 = translate_rreg (SD_, RN1);
8234 
  dstreg2 = translate_rreg (SD_, RN2);
8235 
 
8236 
  State.regs[dstreg1] = result1;
8237 
  if (State.regs[srcreg1] >= 0x7fff)
8238 
    State.regs[dstreg1] = 0x7fff;
8239 
  else if (State.regs[srcreg1] <= 0xffff8000)
8240 
    State.regs[dstreg1] = 0xffff8000;
8241 
  else
8242 
    State.regs[dstreg1] = State.regs[srcreg1];
8243 
}
8244 
 
8245 
// 1111 0111 0101 1101 Rm1 Rn1 imm4 Rn2; sat16_cmp Rm1, Rn1, imm4, Rn2
8246 
8.0xf7+8.0x5d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_cmp
8247 
"sat16_cmp"
8248 
*am33
8249 
{
8250 
  int srcreg1, dstreg1, dstreg2;
8251 
 
8252 
  PC = cia;
8253 
  srcreg1 = translate_rreg (SD_, RM1);
8254 
  dstreg1 = translate_rreg (SD_, RN1);
8255 
  dstreg2 = translate_rreg (SD_, RN2);
8256 
 
8257 
  genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
8258 
  if (State.regs[srcreg1] >= 0x7fff)
8259 
    State.regs[dstreg1] = 0x7fff;
8260 
  else if (State.regs[srcreg1] <= 0xffff8000)
8261 
    State.regs[dstreg1] = 0xffff8000;
8262 
  else
8263 
    State.regs[dstreg1] = State.regs[srcreg1];
8264 
}
8265 
 
8266 
// 1111 0111 0110 1101 Rm1 Rn1 Rm2 Rn2; sat16_mov Rm1, Rn1, Rm2, Rn2
8267 
8.0xf7+8.0x6d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_mov
8268 
"sat16_mov"
8269 
*am33
8270 
{
8271 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8272 
  int result1;
8273 
 
8274 
  PC = cia;
8275 
  srcreg1 = translate_rreg (SD_, RM1);
8276 
  srcreg2 = translate_rreg (SD_, RM2);
8277 
  dstreg1 = translate_rreg (SD_, RN1);
8278 
  dstreg2 = translate_rreg (SD_, RN2);
8279 
 
8280 
  if (State.regs[srcreg1] >= 0x7fff)
8281 
    result1 = 0x7fff;
8282 
  else if (State.regs[srcreg1] <= 0xffff8000)
8283 
    result1 = 0xffff8000;
8284 
  else
8285 
    result1 = State.regs[srcreg1];
8286 
 
8287 
  State.regs[dstreg2] = State.regs[srcreg2];
8288 
  State.regs[dstreg1] = result1;
8289 
}
8290 
 
8291 
// 1111 0111 0111 1101 Rm1 Rn1 imm4 Rn2; sat16_mov Rm1, Rn1, imm4, Rn2
8292 
8.0xf7+8.0x7d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_mov
8293 
"sat16_mov"
8294 
*am33
8295 
{
8296 
  int srcreg1, dstreg1, dstreg2;
8297 
  int result1;
8298 
 
8299 
  PC = cia;
8300 
  srcreg1 = translate_rreg (SD_, RM1);
8301 
  dstreg1 = translate_rreg (SD_, RN1);
8302 
  dstreg2 = translate_rreg (SD_, RN2);
8303 
 
8304 
  if (State.regs[srcreg1] >= 0x7fff)
8305 
    result1 = 0x7fff;
8306 
  else if (State.regs[srcreg1] <= 0xffff8000)
8307 
    result1 = 0xffff8000;
8308 
  else
8309 
    result1 = State.regs[srcreg1];
8310 
 
8311 
  State.regs[dstreg2] = EXTEND4 (IMM4);
8312 
  State.regs[dstreg1] = result1;
8313 
}
8314 
 
8315 
// 1111 0111 1000 1101 Rm1 Rn1 Rm2 Rn2; sat16_asr Rm1, Rn1, Rm2, Rn2
8316 
8.0xf7+8.0x8d+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asr
8317 
"sat16_asr"
8318 
*am33
8319 
{
8320 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8321 
  int result1;
8322 
  signed int temp;
8323 
 
8324 
  PC = cia;
8325 
  srcreg1 = translate_rreg (SD_, RM1);
8326 
  srcreg2 = translate_rreg (SD_, RM2);
8327 
  dstreg1 = translate_rreg (SD_, RN1);
8328 
  dstreg2 = translate_rreg (SD_, RN2);
8329 
 
8330 
  if (State.regs[srcreg1] >= 0x7fff)
8331 
    result1 = 0x7fff;
8332 
  else if (State.regs[srcreg1] <= 0xffff8000)
8333 
    result1 = 0xffff8000;
8334 
  else
8335 
    result1 = State.regs[srcreg1];
8336 
 
8337 
  temp = State.regs[dstreg2];
8338 
  temp >>= State.regs[srcreg2];
8339 
  State.regs[dstreg2] = temp;
8340 
  State.regs[dstreg1] = result1;
8341 
}
8342 
 
8343 
// 1111 0111 1001 1101 Rm1 Rn1 imm4 Rn2; sat16_asr Rm1, Rn1, imm4, Rn2
8344 
8.0xf7+8.0x9d+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asr
8345 
"sat16_asr"
8346 
*am33
8347 
{
8348 
  int srcreg1, dstreg1, dstreg2;
8349 
  int result1;
8350 
  signed int temp;
8351 
 
8352 
  PC = cia;
8353 
  srcreg1 = translate_rreg (SD_, RM1);
8354 
  dstreg1 = translate_rreg (SD_, RN1);
8355 
  dstreg2 = translate_rreg (SD_, RN2);
8356 
 
8357 
  if (State.regs[srcreg1] >= 0x7fff)
8358 
    result1 = 0x7fff;
8359 
  else if (State.regs[srcreg1] <= 0xffff8000)
8360 
    result1 = 0xffff8000;
8361 
  else
8362 
    result1 = State.regs[srcreg1];
8363 
 
8364 
  temp = State.regs[dstreg2];
8365 
  temp >>= IMM4;
8366 
  State.regs[dstreg2] = temp;
8367 
  State.regs[dstreg1] = result1;
8368 
}
8369 
 
8370 
// 1111 0111 1010 1101 Rm1 Rn1 Rm2 Rn2; sat16_lsr Rm1, Rn1, Rm2, Rn2
8371 
8.0xf7+8.0xad+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_lsr
8372 
"sat16_lsr"
8373 
*am33
8374 
{
8375 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8376 
  int result1;
8377 
 
8378 
  PC = cia;
8379 
  srcreg1 = translate_rreg (SD_, RM1);
8380 
  srcreg2 = translate_rreg (SD_, RM2);
8381 
  dstreg1 = translate_rreg (SD_, RN1);
8382 
  dstreg2 = translate_rreg (SD_, RN2);
8383 
 
8384 
  if (State.regs[srcreg1] >= 0x7fff)
8385 
    result1 = 0x7fff;
8386 
  else if (State.regs[srcreg1] <= 0xffff8000)
8387 
    result1 = 0xffff8000;
8388 
  else
8389 
    result1 = State.regs[srcreg1];
8390 
 
8391 
  State.regs[dstreg2] >>= State.regs[srcreg2];
8392 
  State.regs[dstreg1] = result1;
8393 
}
8394 
 
8395 
// 1111 0111 1011 1101 Rm1 Rn1 imm4 Rn2; sat16_lsr Rm1, Rn1, imm4, Rn2
8396 
8.0xf7+8.0xbd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_lsr
8397 
"sat16_lsr"
8398 
*am33
8399 
{
8400 
  int srcreg1, dstreg1, dstreg2;
8401 
  int result1;
8402 
  signed int temp;
8403 
 
8404 
  PC = cia;
8405 
  srcreg1 = translate_rreg (SD_, RM1);
8406 
  dstreg1 = translate_rreg (SD_, RN1);
8407 
  dstreg2 = translate_rreg (SD_, RN2);
8408 
 
8409 
  if (State.regs[srcreg1] >= 0x7fff)
8410 
    result1 = 0x7fff;
8411 
  else if (State.regs[srcreg1] <= 0xffff8000)
8412 
    result1 = 0xffff8000;
8413 
  else
8414 
    result1 = State.regs[srcreg1];
8415 
 
8416 
  State.regs[dstreg2] >>= IMM4;
8417 
  State.regs[dstreg1] = result1;
8418 
}
8419 
 
8420 
 
8421 
// 1111 0111 1100 1101 Rm1 Rn1 Rm2 Rn2; sat16_asl Rm1, Rn1, Rm2, Rn2
8422 
8.0xf7+8.0xcd+4.RM1,4.RN1+4.RM2,4.RN2!RN1:D2:::sat16_asl
8423 
"sat16_asl"
8424 
*am33
8425 
{
8426 
  int srcreg1, srcreg2, dstreg1, dstreg2;
8427 
  int result1;
8428 
 
8429 
  PC = cia;
8430 
  srcreg1 = translate_rreg (SD_, RM1);
8431 
  srcreg2 = translate_rreg (SD_, RM2);
8432 
  dstreg1 = translate_rreg (SD_, RN1);
8433 
  dstreg2 = translate_rreg (SD_, RN2);
8434 
 
8435 
  if (State.regs[srcreg1] >= 0x7fff)
8436 
    result1 = 0x7fff;
8437 
  else if (State.regs[srcreg1] <= 0xffff8000)
8438 
    result1 = 0xffff8000;
8439 
  else
8440 
    result1 = State.regs[srcreg1];
8441 
 
8442 
  State.regs[dstreg2] <<= State.regs[srcreg2];
8443 
  State.regs[dstreg1] = result1;
8444 
}
8445 
 
8446 
// 1111 0111 1101 1101 Rm1 Rn1 imm4 Rn2; sat16_asl Rm1, Rn1, imm4, Rn2
8447 
8.0xf7+8.0xdd+4.RM1,4.RN1+4.IMM4,4.RN2!RN1:D2b:::sat16_asl
8448 
"sat16_asl"
8449 
*am33
8450 
{
8451 
  int srcreg1, dstreg1, dstreg2;
8452 
  int result1;
8453 
  signed int temp;
8454 
 
8455 
  PC = cia;
8456 
  srcreg1 = translate_rreg (SD_, RM1);
8457 
  dstreg1 = translate_rreg (SD_, RN1);
8458 
  dstreg2 = translate_rreg (SD_, RN2);
8459 
 
8460 
  if (State.regs[srcreg1] >= 0x7fff)
8461 
    result1 = 0x7fff;
8462 
  else if (State.regs[srcreg1] <= 0xffff8000)
8463 
    result1 = 0xffff8000;
8464 
  else
8465 
    result1 = State.regs[srcreg1];
8466 
 
8467 
  State.regs[dstreg2] <<= IMM4;
8468 
  State.regs[dstreg1] = result1;
8469 
}
8470 
 
8471 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0000; mov_llt (Rm+,imm4),Rn
8472 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x0:D2:::mov_llt
8473 
"mov_llt"
8474 
*am33
8475 
{
8476 
  int srcreg, dstreg;
8477 
  int result1;
8478 
 
8479 
  PC = cia;
8480 
  srcreg = translate_rreg (SD_, RM);
8481 
  dstreg = translate_rreg (SD_, RN);
8482 
 
8483 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8484 
  State.regs[srcreg] += EXTEND4 (IMM4);
8485 
 
8486 
  if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
8487 
    {
8488 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8489 
      nia = PC;
8490 
    }
8491 
  State.regs[dstreg] = result1;
8492 
}
8493 
 
8494 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0001; mov_lgt (Rm+,imm4),Rn
8495 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x1:D2:::mov_lgt
8496 
"mov_lgt"
8497 
*am33
8498 
{
8499 
  int srcreg, dstreg;
8500 
 
8501 
  PC = cia;
8502 
  srcreg = translate_rreg (SD_, RM);
8503 
  dstreg = translate_rreg (SD_, RN);
8504 
 
8505 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8506 
  State.regs[srcreg] += EXTEND4 (IMM4);
8507 
 
8508 
  if (!((PSW & PSW_Z)
8509 
        || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
8510 
    {
8511 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8512 
      nia = PC;
8513 
    }
8514 
}
8515 
 
8516 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0010; mov_lge (Rm+,imm4),Rn
8517 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x2:D2:::mov_lge
8518 
"mov_lge"
8519 
*am33
8520 
{
8521 
  int srcreg, dstreg;
8522 
 
8523 
  PC = cia;
8524 
  srcreg = translate_rreg (SD_, RM);
8525 
  dstreg = translate_rreg (SD_, RN);
8526 
 
8527 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8528 
  State.regs[srcreg] += EXTEND4 (IMM4);
8529 
 
8530 
  if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8531 
    {
8532 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8533 
      nia = PC;
8534 
    }
8535 
}
8536 
 
8537 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0011; mov_lle (Rm+,imm4),Rn
8538 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x3:D2:::mov_lle
8539 
"mov_lle"
8540 
*am33
8541 
{
8542 
  int srcreg, dstreg;
8543 
 
8544 
  PC = cia;
8545 
  srcreg = translate_rreg (SD_, RM);
8546 
  dstreg = translate_rreg (SD_, RN);
8547 
 
8548 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8549 
  State.regs[srcreg] += EXTEND4 (IMM4);
8550 
 
8551 
  if ((PSW & PSW_Z)
8552 
      || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
8553 
    {
8554 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8555 
      nia = PC;
8556 
    }
8557 
}
8558 
 
8559 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0100; mov_lcs (Rm+,imm4),Rn
8560 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x4:D2:::mov_lcs
8561 
"mov_lcs"
8562 
*am33
8563 
{
8564 
  int srcreg, dstreg;
8565 
 
8566 
  PC = cia;
8567 
  srcreg = translate_rreg (SD_, RM);
8568 
  dstreg = translate_rreg (SD_, RN);
8569 
 
8570 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8571 
  State.regs[srcreg] += EXTEND4 (IMM4);
8572 
 
8573 
  if (PSW & PSW_C)
8574 
    {
8575 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8576 
      nia = PC;
8577 
    }
8578 
}
8579 
 
8580 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0101; mov_lhi (Rm+,imm4),Rn
8581 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x5:D2:::mov_lhi
8582 
"mov_lhi"
8583 
*am33
8584 
{
8585 
  int srcreg, dstreg;
8586 
 
8587 
  PC = cia;
8588 
  srcreg = translate_rreg (SD_, RM);
8589 
  dstreg = translate_rreg (SD_, RN);
8590 
 
8591 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8592 
  State.regs[srcreg] += EXTEND4 (IMM4);
8593 
 
8594 
  if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
8595 
    {
8596 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8597 
      nia = PC;
8598 
    }
8599 
}
8600 
 
8601 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0110; mov_lcc (Rm+,imm4),Rn
8602 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x6:D2:::mov_lcc
8603 
"mov_lcc"
8604 
*am33
8605 
{
8606 
  int srcreg, dstreg;
8607 
 
8608 
  PC = cia;
8609 
  srcreg = translate_rreg (SD_, RM);
8610 
  dstreg = translate_rreg (SD_, RN);
8611 
 
8612 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8613 
  State.regs[srcreg] += EXTEND4 (IMM4);
8614 
 
8615 
  if (!(PSW & PSW_C))
8616 
    {
8617 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8618 
      nia = PC;
8619 
    }
8620 
}
8621 
 
8622 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 0111; mov_lls (Rm+,imm4),Rn
8623 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x7:D2:::mov_lls
8624 
"mov_lls"
8625 
*am33
8626 
{
8627 
  int srcreg, dstreg;
8628 
 
8629 
  PC = cia;
8630 
  srcreg = translate_rreg (SD_, RM);
8631 
  dstreg = translate_rreg (SD_, RN);
8632 
 
8633 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8634 
  State.regs[srcreg] += EXTEND4 (IMM4);
8635 
 
8636 
  if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
8637 
    {
8638 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8639 
      nia = PC;
8640 
    }
8641 
}
8642 
 
8643 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 1000; mov_leq (Rm+,imm4),Rn
8644 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x8:D2:::mov_leq
8645 
"mov_leq"
8646 
*am33
8647 
{
8648 
  int srcreg, dstreg;
8649 
 
8650 
  PC = cia;
8651 
  srcreg = translate_rreg (SD_, RM);
8652 
  dstreg = translate_rreg (SD_, RN);
8653 
 
8654 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8655 
  State.regs[srcreg] += EXTEND4 (IMM4);
8656 
 
8657 
  if (PSW & PSW_Z)
8658 
    {
8659 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8660 
      nia = PC;
8661 
    }
8662 
}
8663 
 
8664 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 1001; mov_lne (Rm+,imm4),Rn
8665 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0x9:D2:::mov_lne
8666 
"mov_lne"
8667 
*am33
8668 
{
8669 
  int srcreg, dstreg;
8670 
 
8671 
  PC = cia;
8672 
  srcreg = translate_rreg (SD_, RM);
8673 
  dstreg = translate_rreg (SD_, RN);
8674 
 
8675 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8676 
  State.regs[srcreg] += EXTEND4 (IMM4);
8677 
 
8678 
  if (!(PSW & PSW_Z))
8679 
    {
8680 
      State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8681 
      nia = PC;
8682 
    }
8683 
}
8684 
 
8685 
// 1111 0111 1110 0000 Rm1 Rn1 imm4 1010; mov_lra (Rm+,imm4),Rn
8686 
8.0xf7+8.0xe0+4.RN,4.RM!RN+4.IMM4,4.0xa:D2:::mov_lra
8687 
"mov_lra"
8688 
*am33
8689 
{
8690 
  int srcreg, dstreg;
8691 
 
8692 
  PC = cia;
8693 
  srcreg = translate_rreg (SD_, RM);
8694 
  dstreg = translate_rreg (SD_, RN);
8695 
 
8696 
  State.regs[dstreg] = load_word (State.regs[srcreg]);
8697 
  State.regs[srcreg] += EXTEND4 (IMM4);
8698 
 
8699 
  State.regs[REG_PC] = State.regs[REG_LAR] - 4;
8700 
  nia = PC;
8701 
}

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