OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [oc/] [gdb-5.0/] [sim/] [mn10300/] [sim-main.h] - Blame information for rev 1771

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 106 markom
/*  This file is part of the program psim.
2
 
3
    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
4
    Copyright (C) 1997, Free Software Foundation
5
 
6
    This program is free software; you can redistribute it and/or modify
7
    it under the terms of the GNU General Public License as published by
8
    the Free Software Foundation; either version 2 of the License, or
9
    (at your option) any later version.
10
 
11
    This program is distributed in the hope that it will be useful,
12
    but WITHOUT ANY WARRANTY; without even the implied warranty of
13
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
    GNU General Public License for more details.
15
 
16
    You should have received a copy of the GNU General Public License
17
    along with this program; if not, write to the Free Software
18
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
 
20
    */
21
 
22
 
23
#ifndef SIM_MAIN_H
24
#define SIM_MAIN_H
25
 
26
#define WITH_CORE
27
#define WITH_WATCHPOINTS 1
28
#define SIM_HANDLES_LMA 1
29
 
30
#define SIM_ENGINE_HALT_HOOK(SD,LAST_CPU,CIA) 0 /* disable this hook */
31
 
32
#include "sim-basics.h"
33
#include "sim-signal.h"
34
 
35
#include <signal.h> /* For kill() in insns:do_trap */
36
 
37
#include <errno.h>
38
#ifdef HAVE_UNISTD_H
39
#include <unistd.h>
40
#endif
41
 
42
/* These are generated files.  */
43
#include "itable.h"
44
#include "idecode.h"
45
#include "idecode.h"
46
 
47
typedef instruction_address sim_cia;
48
static const sim_cia null_cia = {0}; /* Dummy */
49
#define NULL_CIA null_cia
50
/* FIXME: Perhaps igen should generate access macros for
51
   `instruction_address' that we could use.  */
52
/*#define CIA_ADDR(cia) ((cia).ip) doesn't work for mn10300*/
53
 
54
#define WITH_WATCHPOINTS 1
55
 
56
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR)  \
57
mn10300_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
58
 
59
 
60
#include "sim-base.h"
61
 
62
#include "mn10300_sim.h"
63
 
64
/* Bring data in from the cold */
65
 
66
#define IMEM8(EA) \
67
(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA)))
68
 
69
#define IMEM8_IMMED(EA, N) \
70
(sim_core_read_aligned_1(STATE_CPU(sd, 0), EA, exec_map, (EA) + (N)))
71
 
72
 
73
/* FIXME: For moment, save/restore PC value found in struct State.
74
   Struct State will one day go away, being placed in the sim_cpu
75
   state. */
76
#define CIA_GET(CPU) ((PC) + 0)
77
#define CIA_SET(CPU,VAL) ((CPU)->cia = (VAL), PC = (VAL))
78
 
79
 
80
struct _sim_cpu {
81
  sim_event *pending_nmi;
82
  sim_cia cia;
83
  sim_cpu_base base;
84
};
85
 
86
 
87
struct sim_state {
88
 
89
  /* the processors proper */
90
  sim_cpu cpu;
91
#define STATE_CPU(sd, n) (&(sd)->cpu)
92
 
93
  /* The base class.  */
94
  sim_state_base base;
95
 
96
};
97
 
98
/* For compatibility, until all functions converted to passing
99
   SIM_DESC as an argument */
100
extern SIM_DESC simulator;
101
 
102
/* (re) initialize the simulator */
103
 
104
extern void engine_init(SIM_DESC sd);
105
extern SIM_CORE_SIGNAL_FN mn10300_core_signal;
106
 
107
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.