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#include "spr_defs.h"
#include "board.h"
#include "mc.h"
 
 
 
        .extern _reset_support
        .extern _eth_int
        .extern _src_beg
        .extern _dst_beg
        .extern _dst_end
        .extern _c_reset
        .extern _int_main
 
        .global _lolev_ie
        .global _lolev_idis
 
              .section .stack, "aw", @nobits
.space  STACK_SIZE
_stack:
 
.if IN_FLASH
        .section .reset, "ax"
.else
              .section .vectors, "ax"
.endif
 
        .org 0x100
_reset:
.if IN_FLASH
        l.movhi r3,hi(MC_BASE_ADD)
        l.ori   r3,r3,MC_BA_MASK
        l.addi  r5,r0,0x00
        l.sw    0(r3),r5
.endif
        l.movhi r3,hi(_start)
        l.ori   r3,r3,lo(_start)
        l.jr    r3
        l.nop
 
.if IN_FLASH
        .section .vectors, "ax"
.endif
        .org 0x800
 
        l.j     _int_wrapper
        l.nop
 
        .section .text
 
_start:
.if IN_FLASH
        l.jal   _init_mc
        l.nop
 
        /* Wait for SDRAM */
        l.addi  r3,r0,0x0000  /* igor zmanjsal iz 0x7fff na 0x0000 */
1:      l.sfeqi r3,0
        l.bnf   1b
        l.addi  r3,r3,-1
.endif
        /* Copy form flash to sram */
.if IN_FLASH
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_vec_start)
        l.ori   r4,r4,lo(_vec_start)
        l.movhi r5,hi(_vec_end)
        l.ori   r5,r5,lo(_vec_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
2:
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
1:      l.sfgeu r4,r5
        l.bf    1f
        l.nop
        l.lwz   r8,0(r3)
        l.sw    0(r4),r8
        l.addi  r3,r3,4
        l.bnf   1b
        l.addi  r4,r4,4
1:
        l.addi  r3,r0,0
        l.addi  r4,r0,0
3:
.endif
 
.if IC_ENABLE
        l.jal   _ic_enable
        l.nop
.endif
 
.if DC_ENABLE
        l.jal   _dc_enable
        l.nop
.endif
 
        l.movhi r1,hi(_stack-4)
        l.addi  r1,r1,lo(_stack-4)
        l.addi  r2,r0,-3
        l.and   r1,r1,r2
 
        l.movhi r2,hi(_main)
        l.ori   r2,r2,lo(_main)
        l.jr    r2
        l.addi  r2,r0,0
 
_ic_enable:
 
        /* Flush IC */
        l.addi  r10,r0,0
        l.addi  r11,r0,IC_SIZE
1:
        l.mtspr r0,r10,SPR_ICBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable IC */
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
_dc_enable:
 
        /* Flush DC */
        l.addi  r10,r0,0
        l.addi  r11,r0,DC_SIZE
1:
        l.mtspr r0,r10,SPR_DCBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable DC */
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
 
        l.jr    r9
        l.nop
 
.if IN_FLASH
_init_mc:
 
        l.movhi r3,hi(MC_BASE_ADD)
        l.ori   r3,r3,lo(MC_BASE_ADD)
 
        l.addi  r4,r3,MC_CSC(0)
        l.movhi r5,hi(FLASH_BASE_ADD)
        l.srai  r5,r5,5
        l.ori   r5,r5,0x0025
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(0)
        l.movhi r5,hi(FLASH_TMS_VAL)
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_BA_MASK
        l.addi  r5,r0,MC_MASK_VAL
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSR
        l.movhi r5,hi(MC_CSR_VAL)
        l.ori   r5,r5,lo(MC_CSR_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(1)
        l.movhi r5,hi(SDRAM_TMS_VAL)
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSC(1)
        l.movhi r5,hi(SDRAM_BASE_ADD)
        l.srai  r5,r5,5
        l.ori   r5,r5,0x0411
        l.sw    0(r4),r5
 
        l.jr    r9
        l.nop
.endif
 
_int_wrapper:
        l.addi  r1,r1,-128
 
        l.sw    0x4(r1),r2
        l.sw    0x8(r1),r4
        l.sw    0xc(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
        l.sw    0x78(r1),r3
 
        l.movhi r3,hi(_eth_int)
        l.ori   r3,r3,lo(_eth_int)
        l.jalr  r3
        l.nop
 
        l.lwz   r2,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
#        l.lwz   r3,0x78(r1)
 
        l.mtspr r0,r0,SPR_PICSR
 
        l.mfspr r3,r0,SPR_ESR_BASE
        l.ori   r3,r3,SPR_SR_IEE
        l.mtspr r0,r3,SPR_ESR_BASE
 
        l.lwz   r3,0x78(r1)
 
        l.addi  r1,r1,128
        l.rfe
        l.nop
 
        .section .text
_lolev_ie:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IEE
        l.mtspr r0,r3,SPR_SR
        l.movhi r3,hi(ETH0_INT)
        l.ori   r3,r3,lo(ETH0_INT)
        l.mtspr r0,r3,SPR_PICMR
 
        l.jr    r9
        l.nop
 
_lolev_idis:
        l.mtspr r0,r0,SPR_PICMR
 
        l.jr    r9
        l.nop

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[/] [or1k/] [branches/] [oc/] [orpmon/] [reset.S] - Blame information for rev 1771

Line No.	Rev	Author	Line
1	809	simons	`#include "spr_defs.h"`
2			`#include "board.h"`
3			`#include "mc.h"`
4
5
6
7			`.extern _reset_support`
8			`.extern _eth_int`
9			`.extern _src_beg`
10			`.extern _dst_beg`
11			`.extern _dst_end`
12			`.extern _c_reset`
13			`.extern _int_main`
14
15			`.global _lolev_ie`
16			`.global _lolev_idis`
17
18			`.section .stack, "aw", @nobits`
19			`.space STACK_SIZE`
20			`_stack:`
21
22			`.if IN_FLASH`
23			`.section .reset, "ax"`
24			`.else`
25			`.section .vectors, "ax"`
26			`.endif`
27
28			`.org 0x100`
29			`_reset:`
30			`.if IN_FLASH`
31			`l.movhi r3,hi(MC_BASE_ADD)`
32			`l.ori r3,r3,MC_BA_MASK`
33			`l.addi r5,r0,0x00`
34			`l.sw 0(r3),r5`
35			`.endif`
36			`l.movhi r3,hi(_start)`
37			`l.ori r3,r3,lo(_start)`
38			`l.jr r3`
39			`l.nop`
40
41			`.if IN_FLASH`
42			`.section .vectors, "ax"`
43			`.endif`
44			`.org 0x800`
45
46			`l.j _int_wrapper`
47			`l.nop`
48
49			`.section .text`
50
51			`_start:`
52			`.if IN_FLASH`
53			`l.jal _init_mc`
54			`l.nop`
55
56			`/* Wait for SDRAM */`
57			`l.addi r3,r0,0x0000 /* igor zmanjsal iz 0x7fff na 0x0000 */`
58			`1: l.sfeqi r3,0`
59			`l.bnf 1b`
60			`l.addi r3,r3,-1`
61			`.endif`
62			`/* Copy form flash to sram */`
63			`.if IN_FLASH`
64			`l.movhi r3,hi(_src_beg)`
65			`l.ori r3,r3,lo(_src_beg)`
66			`l.movhi r4,hi(_vec_start)`
67			`l.ori r4,r4,lo(_vec_start)`
68			`l.movhi r5,hi(_vec_end)`
69			`l.ori r5,r5,lo(_vec_end)`
70			`l.sub r5,r5,r4`
71			`l.sfeqi r5,0`
72			`l.bf 2f`
73			`l.nop`
74			`1: l.lwz r6,0(r3)`
75			`l.sw 0(r4),r6`
76			`l.addi r3,r3,4`
77			`l.addi r4,r4,4`
78			`l.addi r5,r5,-4`
79			`l.sfgtsi r5,0`
80			`l.bf 1b`
81			`l.nop`
82			`2:`
83			`l.movhi r4,hi(_dst_beg)`
84			`l.ori r4,r4,lo(_dst_beg)`
85			`l.movhi r5,hi(_dst_end)`
86			`l.ori r5,r5,lo(_dst_end)`
87			`1: l.sfgeu r4,r5`
88			`l.bf 1f`
89			`l.nop`
90			`l.lwz r8,0(r3)`
91			`l.sw 0(r4),r8`
92			`l.addi r3,r3,4`
93			`l.bnf 1b`
94			`l.addi r4,r4,4`
95			`1:`
96			`l.addi r3,r0,0`
97			`l.addi r4,r0,0`
98			`3:`
99			`.endif`
100
101			`.if IC_ENABLE`
102			`l.jal _ic_enable`
103			`l.nop`
104			`.endif`
105
106			`.if DC_ENABLE`
107			`l.jal _dc_enable`
108			`l.nop`
109			`.endif`
110
111			`l.movhi r1,hi(_stack-4)`
112			`l.addi r1,r1,lo(_stack-4)`
113			`l.addi r2,r0,-3`
114			`l.and r1,r1,r2`
115
116			`l.movhi r2,hi(_main)`
117			`l.ori r2,r2,lo(_main)`
118			`l.jr r2`
119			`l.addi r2,r0,0`
120
121			`_ic_enable:`
122
123			`/* Flush IC */`
124			`l.addi r10,r0,0`
125			`l.addi r11,r0,IC_SIZE`
126			`1:`
127			`l.mtspr r0,r10,SPR_ICBIR`
128			`l.sfne r10,r11`
129			`l.bf 1b`
130			`l.addi r10,r10,16`
131
132			`/* Enable IC */`
133			`l.addi r10,r0,(SPR_SR_ICE\|SPR_SR_SM)`
134			`l.mtspr r0,r10,SPR_SR`
135			`l.nop`
136			`l.nop`
137			`l.nop`
138			`l.nop`
139			`l.nop`
140
141			`l.jr r9`
142			`l.nop`
143
144			`_dc_enable:`
145
146			`/* Flush DC */`
147			`l.addi r10,r0,0`
148			`l.addi r11,r0,DC_SIZE`
149			`1:`
150			`l.mtspr r0,r10,SPR_DCBIR`
151			`l.sfne r10,r11`
152			`l.bf 1b`
153			`l.addi r10,r10,16`
154
155			`/* Enable DC */`
156			`l.addi r10,r0,(SPR_SR_DCE\|SPR_SR_SM)`
157			`l.mtspr r0,r10,SPR_SR`
158
159			`l.jr r9`
160			`l.nop`
161
162			`.if IN_FLASH`
163			`_init_mc:`
164
165			`l.movhi r3,hi(MC_BASE_ADD)`
166			`l.ori r3,r3,lo(MC_BASE_ADD)`
167
168			`l.addi r4,r3,MC_CSC(0)`
169			`l.movhi r5,hi(FLASH_BASE_ADD)`
170			`l.srai r5,r5,5`
171			`l.ori r5,r5,0x0025`
172			`l.sw 0(r4),r5`
173
174			`l.addi r4,r3,MC_TMS(0)`
175			`l.movhi r5,hi(FLASH_TMS_VAL)`
176			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
177			`l.sw 0(r4),r5`
178
179			`l.addi r4,r3,MC_BA_MASK`
180			`l.addi r5,r0,MC_MASK_VAL`
181			`l.sw 0(r4),r5`
182
183			`l.addi r4,r3,MC_CSR`
184			`l.movhi r5,hi(MC_CSR_VAL)`
185			`l.ori r5,r5,lo(MC_CSR_VAL)`
186			`l.sw 0(r4),r5`
187
188			`l.addi r4,r3,MC_TMS(1)`
189			`l.movhi r5,hi(SDRAM_TMS_VAL)`
190			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
191			`l.sw 0(r4),r5`
192
193			`l.addi r4,r3,MC_CSC(1)`
194			`l.movhi r5,hi(SDRAM_BASE_ADD)`
195			`l.srai r5,r5,5`
196			`l.ori r5,r5,0x0411`
197			`l.sw 0(r4),r5`
198
199			`l.jr r9`
200			`l.nop`
201			`.endif`
202
203			`_int_wrapper:`
204			`l.addi r1,r1,-128`
205
206			`l.sw 0x4(r1),r2`
207			`l.sw 0x8(r1),r4`
208			`l.sw 0xc(r1),r5`
209			`l.sw 0x10(r1),r6`
210			`l.sw 0x14(r1),r7`
211			`l.sw 0x18(r1),r8`
212			`l.sw 0x1c(r1),r9`
213			`l.sw 0x20(r1),r10`
214			`l.sw 0x24(r1),r11`
215			`l.sw 0x28(r1),r12`
216			`l.sw 0x2c(r1),r13`
217			`l.sw 0x30(r1),r14`
218			`l.sw 0x34(r1),r15`
219			`l.sw 0x38(r1),r16`
220			`l.sw 0x3c(r1),r17`
221			`l.sw 0x40(r1),r18`
222			`l.sw 0x44(r1),r19`
223			`l.sw 0x48(r1),r20`
224			`l.sw 0x4c(r1),r21`
225			`l.sw 0x50(r1),r22`
226			`l.sw 0x54(r1),r23`
227			`l.sw 0x58(r1),r24`
228			`l.sw 0x5c(r1),r25`
229			`l.sw 0x60(r1),r26`
230			`l.sw 0x64(r1),r27`
231			`l.sw 0x68(r1),r28`
232			`l.sw 0x6c(r1),r29`
233			`l.sw 0x70(r1),r30`
234			`l.sw 0x74(r1),r31`
235			`l.sw 0x78(r1),r3`
236
237			`l.movhi r3,hi(_eth_int)`
238			`l.ori r3,r3,lo(_eth_int)`
239			`l.jalr r3`
240			`l.nop`
241
242			`l.lwz r2,0x4(r1)`
243			`l.lwz r4,0x8(r1)`
244			`l.lwz r5,0xc(r1)`
245			`l.lwz r6,0x10(r1)`
246			`l.lwz r7,0x14(r1)`
247			`l.lwz r8,0x18(r1)`
248			`l.lwz r9,0x1c(r1)`
249			`l.lwz r10,0x20(r1)`
250			`l.lwz r11,0x24(r1)`
251			`l.lwz r12,0x28(r1)`
252			`l.lwz r13,0x2c(r1)`
253			`l.lwz r14,0x30(r1)`
254			`l.lwz r15,0x34(r1)`
255			`l.lwz r16,0x38(r1)`
256			`l.lwz r17,0x3c(r1)`
257			`l.lwz r18,0x40(r1)`
258			`l.lwz r19,0x44(r1)`
259			`l.lwz r20,0x48(r1)`
260			`l.lwz r21,0x4c(r1)`
261			`l.lwz r22,0x50(r1)`
262			`l.lwz r23,0x54(r1)`
263			`l.lwz r24,0x58(r1)`
264			`l.lwz r25,0x5c(r1)`
265			`l.lwz r26,0x60(r1)`
266			`l.lwz r27,0x64(r1)`
267			`l.lwz r28,0x68(r1)`
268			`l.lwz r29,0x6c(r1)`
269			`l.lwz r30,0x70(r1)`
270			`l.lwz r31,0x74(r1)`
271			`# l.lwz r3,0x78(r1)`
272
273			`l.mtspr r0,r0,SPR_PICSR`
274
275			`l.mfspr r3,r0,SPR_ESR_BASE`
276			`l.ori r3,r3,SPR_SR_IEE`
277			`l.mtspr r0,r3,SPR_ESR_BASE`
278
279			`l.lwz r3,0x78(r1)`
280
281			`l.addi r1,r1,128`
282			`l.rfe`
283			`l.nop`
284
285			`.section .text`
286			`_lolev_ie:`
287			`l.mfspr r3,r0,SPR_SR`
288			`l.ori r3,r3,SPR_SR_IEE`
289			`l.mtspr r0,r3,SPR_SR`
290			`l.movhi r3,hi(ETH0_INT)`
291			`l.ori r3,r3,lo(ETH0_INT)`
292			`l.mtspr r0,r3,SPR_PICMR`
293
294			`l.jr r9`
295			`l.nop`
296
297			`_lolev_idis:`
298			`l.mtspr r0,r0,SPR_PICMR`
299
300			`l.jr r9`
301			`l.nop`