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1 809 simons
/* sim.cfg -- Simulator configuration script file
2
   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
3
 
4
This file includes a lot of help about configurations and default one
5
 
6
This file is part of OpenRISC 1000 Architectural Simulator.
7
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22
 
23
/* INTRODUCTION
24
 
25
   The or1ksim have various parameters, which can be set in configuration
26
   files.  Multiple configurations may be used and switched between at
27
   or1ksim startup.
28
   By default, or1ksim loads condfiguration file from './sim.cfg' and if not
29
   found it checks '~/.or1k/sim.cfg'. If even this file is not found or
30
   all parameters are not defined, default configuration is used.
31
   Users should not rely on default configuration, but rather redefine all
32
   critical settings, since default configuration may differ in newer
33
   versions of the or1ksim.
34
   If multiple configurations are used, user can switch between them by
35
   supplying -f  option when starting simulator.
36
 
37
   This file may contain (standard C) only comments - no // support.
38
 
39
   Configure files can also be included, using:
40
 
41
   include "file_name_to_include"
42
 
43
   Like normal configuration file, this file is divided in sections,
44
   where each section is described in detail also.
45
 
46
   Some section also have subsections. One example of such subsection is
47
   block:
48
 
49
   device 
50
     instance specific parameters...
51
   enddevice
52
 
53
   which creates a device instance.
54
*/
55
 
56
/* MEMORY SECTION
57
 
58
   This section specifies how is initial memory generated and which blocks
59
   it consist of.
60
 
61
   type = random/unknown/pattern
62
      specifies the initial memory values. 'random' parameter generate
63
      random memory using seed 'random_seed' parameter. 'pattern' parameter
64
      fills memory with 'pattern' parameter and 'unknown' does not specify
65
      how memory should be generated - the fastest option.
66
 
67
   random_seed = 
68
      random seed for randomizer, used if type = random
69
 
70
   pattern = 
71
      pattern to fill memory, used if type = pattern
72
 
73
   nmemories = 
74
      number of memory instances connected
75
 
76
   instance specific:
77
     baseaddr = 
78
        memory start address
79
 
80
     size = 
81
        memory size
82
 
83
     name = ""
84
        memory block name
85
 
86
     ce = 
87
        chip enable index of the memory instance
88
 
89
     delayr = 
90
        cycles, required for read access, -1 if instance does not support reading
91
 
92
     delayw = 
93
        cycles, required for write access, -1 if instance does not support writing
94
 
95
     16550 = 0/1
96
        0, if this device is uart 16450 and 1, if it is 16550
97
 
98
     log = ""
99
        filename, where to log memory accesses to, no log, if log command is not specified
100
*/
101
 
102
section memory
103
  /*random_seed = 12345
104
  type = random*/
105
  pattern = 0x00
106
  type = unknown /* Fastest */
107
 
108
  nmemories = 2
109
  device 0
110
    name = "FLASH"
111
    ce = 0
112
    baseaddr = 0x04000000
113
    size = 0x00200000
114
    delayr = 10
115
    delayw = -1
116
  enddevice
117
 
118
  device 1
119
    name = "RAM"
120
    ce = 1
121
    baseaddr = 0x00000000
122
    size = 0x00200000
123
    delayr = 2
124
    delayw = 4
125
  enddevice
126
end
127
 
128
 
129
/* IMMU SECTION
130
 
131
    This section configures Instruction Memory Menangement Unit
132
 
133
    enabled = 0/1
134
       whether IMMU is enabled
135
       (NOTE: UPR bit is set)
136
 
137
    nsets = 
138
       number of ITLB sets; must be power of two
139
 
140
    nways = 
141
       number of ITLB ways
142
 
143
    pagesize = 
144
       instruction page size; must be power of two
145
 
146
    entrysize = 
147
       instruction entry size in bytes
148
 
149
    ustates = 
150
       number of ITLB usage states (2, 3, 4 etc., max is 4)
151
 
152
    hitdelay = 
153
       number of cycles immu hit costs
154
 
155
    missdelay = 
156
       number of cycles immu miss costs
157
*/
158
 
159
section immu
160
  enabled = 0
161
  nsets = 32
162
  nways = 1
163
  pagesize = 8192
164
  hitdelay = 0
165
  missdelay = 0
166
end
167
 
168
 
169
/* DMMU SECTION
170
 
171
    This section configures Data Memory Menangement Unit
172
 
173
    enabled = 0/1
174
       whether DMMU is enabled
175
       (NOTE: UPR bit is set)
176
 
177
    nsets = 
178
       number of DTLB sets; must be power of two
179
 
180
    nways = 
181
       number of DTLB ways
182
 
183
    pagesize = 
184
       data page size; must be power of two
185
 
186
    entrysize = 
187
       data entry size in bytes
188
 
189
    ustates = 
190
       number of DTLB usage states (2, 3, 4 etc., max is 4)
191
 
192
    hitdelay = 
193
       number of cycles immu hit costs
194
 
195
    missdelay = 
196
       number of cycles immu miss costs
197
*/
198
 
199
section dmmu
200
  enabled = 0
201
  nsets = 32
202
  nways = 1
203
  pagesize = 8192
204
  hitdelay = 0
205
  missdelay = 0
206
end
207
 
208
 
209
/* IC SECTION
210
 
211
   This section configures Instruction Cache
212
 
213
   enabled = 0/1
214
      whether IC is enabled
215
      (NOTE: UPR bit is set)
216
 
217
   nsets = 
218
      number of IC sets; must be power of two
219
 
220
   nways = 
221
      number of IC ways
222
 
223
   blocksize = 
224
      IC block size in bytes; must be power of two
225
 
226
   ustates = 
227
      number of IC usage states (2, 3, 4 etc., max is 4)
228
 
229
   hitdelay = 
230
      number of cycles ic hit costs
231
 
232
    missdelay = 
233
      number of cycles ic miss costs
234
*/
235
 
236
section ic
237
  enabled = 0
238
  nsets = 512
239
  nways = 1
240
  blocksize = 16
241
  hitdelay = 0
242
  missdelay = 0
243
end
244
 
245
 
246
/* DC SECTION
247
 
248
   This section configures Data Cache
249
 
250
   enabled = 0/1
251
      whether DC is enabled
252
      (NOTE: UPR bit is set)
253
 
254
   nsets = 
255
      number of DC sets; must be power of two
256
 
257
   nways = 
258
      number of DC ways
259
 
260
   blocksize = 
261
      DC block size in bytes; must be power of two
262
 
263
   ustates = 
264
      number of DC usage states (2, 3, 4 etc., max is 4)
265
 
266
   load_hitdelay = 
267
      number of cycles dc load hit costs
268
 
269
   load_missdelay = 
270
      number of cycles dc load miss costs
271
 
272
   store_hitdelay = 
273
      number of cycles dc load hit costs
274
 
275
   store_missdelay = 
276
      number of cycles dc load miss costs
277
*/
278
 
279
section dc
280
  enabled = 0
281
  nsets = 512
282
  nways = 1
283
  blocksize = 16
284
  load_hitdelay = 0
285
  load_missdelay = 0
286
  store_hitdelay = 0
287
  store_missdelay = 0
288
end
289
 
290
/* SIM SECTION
291
 
292
  This section specifies how should sim behave.
293
 
294
  verbose = 0/1
295
      whether to print out extra messages
296
 
297
  debug = 0-9
298
      = 0 disabled debug messages
299
      1-9 level of sim debug information, greater the number more verbose is
300
          the output
301
 
302
  profile = 0/1
303
      whether to generate profiling file 'sim.profile'
304
 
305
  prof_fn = ""
306
      filename, where to generate profiling info, used
307
      only if 'profile' is set
308
 
309
  mprofile = 0/1
310
      whether to generate memory profiling file 'sim.mprofile'
311
 
312
  mprof_fn = ""
313
      filename, where to generate memory profiling info, used
314
      only if 'mprofile' is set
315
 
316
  history = 0/1
317
      whether instruction execution flow is tracked for
318
      display by simulator hist command. Useful for
319
      back-trace debugging.
320
 
321
  iprompt = 0/1
322
      whether we strart in interactive prompt
323
 
324
  exe_log = 0/1
325
      whether execution log should be generated
326
 
327
  exe_log = default/hardware/simple/software
328
      type of executed log, default is used if not specified
329
 
330
  exe_log_start = 
331
      index of first instruction to start log with, default = 0
332
 
333
  exe_log_end = 
334
      index of last instruction to end log with; not limited, if omitted
335
 
336
  exe_log_marker = 
337
       specifies number of instructions before horizontal marker is
338
      printed; if zero, markers are disabled (default)
339
 
340
  exe_log_fn = ""
341
      where to put execution log in, used only if 'exe_log'
342
      is set
343
 
344
  spr_log = 0/1
345
      whether log of writes/reads to/from sprs should be generated
346
 
347
  spr_log_fn = ""
348
      where to put sprs writes/reads in log, used only if 'spr_log'
349
      is set
350
 
351
  clkcycle = [ps|ns|us|ms]
352
      specifies time measurement for one cycle
353
*/
354
 
355
section sim
356
  /* verbose = 1 */
357
  debug = 3
358
  profile = 0
359
  prof_fn = "sim.profile"
360
  mprofile = 0
361
  mprof_fn = "sim.mprofile"
362
 
363
  history = 0
364
  /* iprompt = 0 */
365
  exe_log = 0
366
  exe_log_type = software
367
  exe_log_fn = "executed.log"
368
  spr_log = 0
369
  spr_log_fn = "spr.log"
370
  clkcycle = 100ns
371
end
372
 
373
 
374
/* SECTION VAPI
375
 
376
    This section configures Verification API, used for Advanced
377
    Core Verification.
378
 
379
    enabled = 0/1
380
        whether to start VAPI server
381
 
382
    server_port = 
383
        TCP/IP port to start VAPI server on
384
 
385
    log_enabled = 0/1
386
       whether logging of VAPI requests is enabled
387
 
388
    hide_device_id = 0/1
389
       whether to disable logging of device id (for compatability with old version)
390
 
391
    vapi_fn = 
392
       specifies filename where to log into, if log_enabled is selected
393
*/
394
 
395
section VAPI
396
  enabled = 0
397
  server_port = 9998
398
  log_enabled = 0
399
  vapi_log_fn = "vapi.log"
400
end
401
 
402
 
403
/* CPU SECTION
404
 
405
   This section specifies various CPU parameters.
406
 
407
   ver = 
408
   rev = 
409
      specifies version and revision of the CPU used
410
 
411
   upr = 
412
      changes the upr register
413
 
414
   sr = 
415
      sets the initial Supervision Register value
416
 
417
   superscalar = 0/1
418
      whether CPU is scalar or superscalar
419
      (modify cpu/or32/execute.c to tune superscalar model)
420
 
421
   hazards = 0/1
422
      whether data hazards are tracked in superscalar CPU
423
      and displayed by the simulator r command
424
 
425
   dependstats = 0/1
426
      whether inter-instruction dependencies are calculated
427
      and displayed by simulator stats command.
428
 
429
   sbuf_len = 
430
      length of store buffer (<= 256), 0 = disabled
431
*/
432
 
433
section cpu
434
  ver = 0x1200
435
  rev = 0x0001
436
  /* upr = */
437
  sr = 0x00008003
438
  superscalar = 0
439
  hazards = 0
440
  dependstats = 0
441
  sbuf_len = 0
442
end
443
 
444
 
445
/* PM SECTION
446
 
447
   This section specifies Power Menagement paramaters
448
 
449
   enabled = 0/1
450
      whether power menagement is enabled
451
*/
452
 
453
section pm
454
  enabled = 0
455
end
456
 
457
/* BPB SECTION
458
 
459
   This section specifies how branch prediction should behave.
460
 
461
   enabled = 0/1
462
      whether bpb is enabled
463
 
464
   btic = 0/1
465
      enable branch target instruction cache model
466
 
467
   sbp_bf_fwd = 0/1
468
      whether static branch prediction for l.bf uses forward prediction
469
 
470
   sbp_bnf_fwd = 0/1
471
      whether static branch prediction for l.bnf uses forward prediction
472
 
473
   hitdelay = 
474
       number of cycles bpb hit costs
475
 
476
   missdelay = 
477
       number of cycles bpb miss costs
478
*/
479
 
480
section bpb
481
  enabled = 0
482
  btic = 0
483
  sbp_bf_fwd = 0
484
  sbp_bnf_fwd = 0
485
  hitdelay = 0
486
  missdelay = 0
487
end
488
 
489
 
490
/* DEBUG SECTION
491
 
492
   This sections specifies how debug unit should behave.
493
 
494
   enabled = 0/1
495
      whether debug unit is enabled
496
 
497
   gdb_enabled = 0/1
498
      whether to start gdb server at 'server_port' port
499
 
500
   server_port = 
501
      TCP/IP port to start gdb server on, used only if gdb_enabled
502
      is set
503
 
504
   vapi_id = 
505
      Used to create "fake" vapi log file containing the JTAG proxy messages.
506
*/
507
 
508
section debug
509
  enabled = 1
510
  gdb_enabled = 0
511
  server_port = 9999
512
  vapi_id = 0xFFFF
513
end
514
 
515
 
516
/* MC SECTION
517
 
518
   This section configures the memory controller
519
 
520
   enabled = 0/1
521
      whether memory controller is enabled
522
 
523
   baseaddr = 
524
      address of first MC register
525
 
526
   POC = 
527
      Power On Configuration register
528
*/
529
 
530
section mc
531
  enabled = 1
532
  baseaddr = 0x60000000
533
  POC = 0x00000008                 /* Power on configuration register */
534
end
535
 
536
 
537
/* UART SECTION
538
 
539
   This section configures UARTs
540
 
541
   nuarts = 
542
      make specified number of instances, configure each
543
      instance within device - enddevice construct.
544
 
545
   instance specific:
546
     baseaddr = 
547
        address of first UART register for this device
548
 
549
     rxfile = ""
550
        filename, where to read data from
551
 
552
     txfile = ""
553
        filename, where to write data to
554
 
555
     irq = 
556
        irq number for this device
557
 
558
     16550 = 0/1
559
        0, if this device is uart 16450 and 1, if it is 16550
560
 
561
     jitter = 
562
        in msecs... time to block, -1 to disable it
563
 
564
     vapi_id = 
565
        VAPI id of this instance
566
*/
567
 
568
section uart
569
  nuarts = 1
570
 
571
  device 0
572
    baseaddr = 0x90000000
573
    irq = 2
574
    rxfile = "uart0.rx"
575
    txfile = "uart0.tx"
576
    jitter = -1                     /* async behaviour */
577
  enddevice
578
end
579
 
580
 
581
/* DMA SECTION
582
 
583
   This section configures DMAs
584
 
585
   ndmas = 
586
      make specified number of instances, configure each
587
      instance within device - enddevice construct.
588
 
589
   instance specific:
590
     baseaddr = 
591
        address of first DMA register for this device
592
 
593
     irq = 
594
        irq number for this device
595
 
596
     vapi_id = 
597
        VAPI id of this instance
598
*/
599
 
600
section dma
601
  ndmas = 0
602
/*
603
  device 0
604
    baseaddr = 0x90000000
605
    irq = 4
606
  enddevice
607
*/
608
end
609
 
610
 
611
/* ETHERNET SECTION
612
 
613
   This section configures ethernets
614
 
615
   nethernets = 
616
      make specified number of instances, configure each
617
      instance within device - enddevice construct.
618
 
619
   instance specific:
620
     baseaddr = 
621
        address of first ethernet register for this device
622
 
623
     dma = 
624
        which controller is this ethernet "connected" to
625
 
626
     rx_channel = 
627
        DMA channel used for RX
628
 
629
     tx_channel = 
630
        DMA channel used for TX
631
 
632
     rxfile = ""
633
        filename, where to read data from
634
 
635
     txfile = ""
636
        filename, where to write data to
637
 
638
     vapi_id = 
639
        VAPI id of this instance
640
*/
641
 
642
section ethernet
643
  nethernets = 1
644
 
645
 
646
  device 0
647
    baseaddr = 0xD0000000
648
    dma = 0
649
    tx_channel = 0
650
    rx_channel = 1
651
    rxfile = "/tmp/eth0.rx"
652
    txfile = "/tmp/eth0.tx"
653
  enddevice
654
 
655
end
656
 
657
/* GPIO SECTION
658
 
659
   This section configure GPIOs
660
 
661
   ngpios = 
662
      make specified number of instances, configure each
663
      instance within device - enddevice construct.
664
 
665
   instance specific:
666
     baseaddr = 
667
        address of first GPIO register for this device
668
 
669
     irq = 
670
        irq number for this device
671
 
672
     base_vapi_id = 
673
        first VAPI id of this instance
674
        GPIO uses 8 consecutive VAPI IDs
675
*/
676
 
677
section gpio
678
  ngpios = 1
679
 
680
  device 0
681
    baseaddr = 0xA0000000
682
    irq = 23
683
    base_vapi_id = 0x0200
684
  enddevice
685
end
686
 
687
/* VGA SECTION
688
 
689
    This section configures VGA/LCD controller
690
 
691
    nvgas = 
692
       number of VGA devices connected
693
 
694
    instance specific:
695
      baseaddr = 
696
        address of first VGA register
697
 
698
      irq = 
699
        irq number for this device
700
 
701
      refresh_rate = 
702
        number of cycles between screen dumps
703
 
704
      filename = ""
705
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
706
*/
707
/*
708
section vga
709
  nvgas = 1
710
 
711
  device 0
712
    baseaddr = 0xb0000000
713
    irq = 20
714
    refresh_rate = 100000
715
    filename = "primary"
716
  enddevice
717
end
718
*/
719
/* FB SECTION
720
 
721
    This section configures frame buffer
722
 
723
    enabled = 0/1
724
      whether frame buffer is enabled
725
 
726
    baseaddr = 
727
      base address of frame buffer
728
 
729
    paladdr = 
730
      base address of first palette entry
731
 
732
    refresh_rate = 
733
      number of cycles between screen dumps
734
 
735
    filename = ""
736
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
737
*/
738
 
739
section fb
740
  enabled = 1
741
  baseaddr = 0xb8000000
742
  refresh_rate = 100000
743
  filename = "primary"
744
end
745
 
746
/* KBD SECTION
747
 
748
    This section configures PS/2 compatible keyboard
749
 
750
    enabled = 0/1
751
      whether keyboard is enabled
752
 
753
    baseaddr = 
754
      base address of the keyboard device
755
 
756
    rxfile = ""
757
      filename, where to read data from
758
*/
759
 
760
section kbd
761
  enabled = 1
762
  irq = 21
763
  baseaddr = 0xb1000000
764
  rxfile = "/tmp/kbd.rx"
765
end

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