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[/] [or1k/] [branches/] [oc/] [xess/] [xsv_cpld/] [rtl/] [verilog/] [tdm_master_if.v] - Blame information for rev 1771

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1 767 lampret
// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module tdm_master_if(clk, rst, tdmfrm, tdmrx, tdmtx,
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                        din, dout
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                );
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input           clk;
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input           rst;
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output          tdmfrm;
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input           tdmrx;
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output          tdmtx;
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input   [7:0]    din;
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output  [7:0]    dout;
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reg     [2:0]    clk_cnt;
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reg     [7:0]    dout;
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reg             tdmtx;
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//
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// Counter for low speed clock and incoming JTAG data slots
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//
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always @(posedge clk or posedge rst)
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        if (rst)
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                clk_cnt <= #1 3'b000;
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        else
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                clk_cnt <= #1 clk_cnt + 1;
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//
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// Frame generation
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//
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assign tdmfrm = (clk_cnt == 3'b000) ? 1'b1 : 1'b0;
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//
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// RX Data slot extraction
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//
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always @(posedge clk or posedge rst)
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        if (rst) begin
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                dout <= #1 8'b0000_0000;
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        end else
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        case (clk_cnt[2:0])
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                3'd0:   dout[0] <= #1 tdmrx;
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                3'd1:   dout[1] <= #1 tdmrx;
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                3'd2:   dout[2] <= #1 tdmrx;
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                3'd3:   dout[3] <= #1 tdmrx;
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                3'd4:   dout[4] <= #1 tdmrx;
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                3'd5:   dout[5] <= #1 tdmrx;
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                3'd6:   dout[6] <= #1 tdmrx;
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                3'd7:   dout[7] <= #1 tdmrx;
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        endcase
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//
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// TX Data slot insertion
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//
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always @(clk_cnt or din)
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        case (clk_cnt[2:0])
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                3'd0:   tdmtx = din[0];
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                3'd1:   tdmtx = din[1];
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                3'd2:   tdmtx = din[2];
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                3'd3:   tdmtx = din[3];
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                3'd4:   tdmtx = din[4];
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                3'd5:   tdmtx = din[5];
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                3'd6:   tdmtx = din[6];
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                3'd7:   tdmtx = din[7];
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        endcase
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endmodule

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