Subversion Repositories or1k

//

// XC9500 CPLD design which controls the configuration of the XSV Virtex

// with data from the Flash chip.

//

`define ADDR_LEN 21     // number of Flash address bits

module xsv_cpld_top (clk,

                a, ceb, oeb, web, resetb,

                V_progb, V_cclk, V_csb, V_wrb, V_initb, V_dout,

                V_done, V_m,  rxd, txd, ppd, ppc, pps,

                eth_leds, eth_ledr, eth_ledt, eth_ledl, eth_ledc,

                eth_mf, eth_cfg, eth_mddis, eth_fde

);

input                   clk;            // clock from DS1075 prog. osc.

// Flash address and control pins

output  [`ADDR_LEN-1:0]  a;              // Flash address

output                  ceb;            // Flash chip-enable

output                  oeb;            // Flash output-enable

output                  web;            // Flash write-enable

output                  resetb;         // Flash reset

// Virtex configuration pins

output                  V_progb;        // Virtex PROGRAM pin

output                  V_cclk;         // Virtex config clock

output                  V_csb;          // Virtex config chip-select

output                  V_wrb;          // Virtex config write-enable

input                   V_initb;        // Virtex config init status

input                   V_dout;         // Virtex config busy status

input                   V_done;         // Virtex config done status

output  [2:0]            V_m;            // Virtex config. mode pins     

// connect UART to virtex FPGA

input  rxd;   // From RS232

output txd;   // To RS232

// parallel port data, control, and status pins

input   [7:0]   ppd;

input   [3:0]   ppc;

output  [6:3]   pps;

// Ethernet control/status

input                   eth_leds, eth_ledr,

                                eth_ledt, eth_ledl,

                                eth_ledc;

output  [4:0]    eth_mf;

output  [1:0]    eth_cfg;

output                  eth_mddis, eth_fde;

`define LO 1'b0

`define HI 1'b1

`define FLOAT 1'bz

reg     [3:0]            clk_cnt;

wire                    cclk;

wire                    programb;

reg                     cs;

reg     [`ADDR_LEN-1:0]  addr;

wire    [`ADDR_LEN-1:0]  next_addr;

reg                     poweron_reset;

reg     [19:0]           poweron_cnt;

wire                    V_busy;

wire                    button_progb;

// JTAG pins between CPLD and FPGA

wire                    jtag_tdo;

wire                    jtag_tdi;

wire                    jtag_tms;

wire                    jtag_trst;

wire                    jtag_tck;

wire                    tdmfrm;

wire                    tdmrx;

wire                    tdmtx;

wire                    tdm_dout_2;

wire                    tdm_dout_3;

wire                    tdm_dout_4;

wire                    tdm_dout_5;

wire                    tdm_dout_6;

wire                    tdm_dout_7;

assign V_busy = V_dout;         // give this signal a better name

// set Virtex mode to SelectMAP so it can be configured from Flash

//assign V_m = 3'b110;

assign V_m = V_done ? 3'b111 : 3'b110;    // SelectMAP before it is configured, slave-serial mode after configuration

                                          // We need this to get more pins

// Flash is enabled for reading while Virtex is not yet configured

// and then the Flash pins float when configuration is done

assign oeb = V_done ? `FLOAT : `LO;

assign ceb = V_done ? `FLOAT : `LO;

assign web = V_done ? `FLOAT : `HI;     // disable Flash writes

assign resetb = `HI;                    // remove Flash reset

// generate configuration clock for Virtex from the XSV clock.

// The XSV clock could be as much as 100 MHz, so divide by 16

// to exceed the access time of the Flash.

always @(posedge clk)

        clk_cnt <= #1 clk_cnt + 1;

assign cclk = clk_cnt[3];       // internal configuration clock

assign V_cclk = cclk;           // also send config. clock to Virtex

// Apply reset when the power to the XSV Board is first applied.

// Remove the power-on reset after the counter reaches 0.

always @(posedge cclk)

        if (poweron_cnt == 0)

                poweron_reset <= #1 `LO;        // remove reset when timeout expires

        else begin

                poweron_cnt <= #1 poweron_cnt - 1;

                poweron_reset <= #1 `HI;

        end

// initiate Virtex configuration by lowering the /PROGRAM pin

// during the initial power-on reset and then raising it when

// the power-on timeout expires and the manual program control is high

assign programb = !poweron_reset;

assign V_progb = programb;

// Select the Virtex for configuration as long as the /PROGRAM pin

// is not held low and the INIT pin is not low.

always @(posedge cclk or negedge programb)

        if (!programb)

                cs <= #1 `LO;

        else

                cs <= #1 V_initb;

// Select the Virtex for configuration by lowering its chip-select

// and write inputs when the internal chip-select is high.  Then

// float these pins after the Virtex configuration is done.

//assign V_csb = V_done ? `FLOAT : !cs;

assign V_csb = V_done ? tdmfrm : !cs;   // UART

assign V_wrb = V_done ? tdmtx : !cs;

// increment the Flash address so the next byte of configuration

// data is presented to the Virtex.  Stop incrementing if the

// Virtex is not selected, signals a config. error (INIT=0), or

// is busy.  Reset the address counter to zero whenever the

// /PROGRAM pin goes low and a new configuration sequence begins.

always @(posedge cclk)

        if (cs && V_initb && !V_busy)

                addr <= #1 addr + 1;

        else if (!programb)

                addr <= #1 {`ADDR_LEN{`LO}};

// pass the Flash address out to the Flash chip.  Float the address

// lines once configuration is done.

assign a = V_done ? {`ADDR_LEN{`FLOAT}} : addr;

// connect tdmrx to virtex FPGA

assign tdmrx = V_initb;

// Aliases for GDB JTAG signals.

assign pps[5] = jtag_tdo;

assign jtag_tdi = ppd[4];

assign jtag_tms = ppd[5];

assign jtag_trst = ppd[3];

assign jtag_tck = ppd[2];

tdm_master_if i_tdm_master_if

    (.clk       ( clk  ),

     .rst       (~V_done ),

     .tdmfrm    ( tdmfrm                ),

     .tdmrx     ( tdmrx                 ),

     .tdmtx     ( tdmtx                 ),

     .din       ({jtag_tms,

                  jtag_tck,

                  jtag_trst,

                  jtag_tdi,

                  rxd,

                  3'b000               }),

     .dout      ({jtag_tdo,

                  txd,

                  tdm_dout_2,

                  tdm_dout_3,

                  tdm_dout_4,

                  tdm_dout_5,

                  tdm_dout_6,

                  tdm_dout_7           }));

// Ethernet control

assign eth_mf[0] = 1'b0; // A/N disabled, addr 0

assign eth_mf[1] = 1'b0;        // DTE mode, addr 0

assign eth_mf[2] = 1'b0;        // nibble mode, addr 0

assign eth_mf[3] = 1'b0;        // scrambler enabled, addr 0

assign eth_mf[4] = 1'b0;        // TP mode, addr 0

assign eth_cfg[0] = 1'b0;        // 10Mbps mode

assign eth_cfg[1] = 1'b0;       // In 10Mbps mode, enable Link Test

assign eth_mddis = 1'b0;        // enable management

assign eth_fde = 1'b0;          // disable full-duplex

endmodule