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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [debug/] [debug_unit.h] - Blame information for rev 1771

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1 221 markom
/* debug_unit.h -- Simulation of Or1k debug unit
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   Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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typedef enum {
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  JTAG_CHAIN_GLOBAL = 0,
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  JTAG_CHAIN_DEBUG_UNIT = 1,
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  JTAG_CHAIN_TEST = 2,
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  JTAG_CHAIN_TRACE = 3,
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  JTAG_CHAIN_DEVELOPMENT = 4,
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  JTAG_CHAIN_WISHBONE = 5,
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  JTAG_CHAIN_BLOCK1 = 6,
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  JTAG_CHAIN_BLOCK2 = 7,
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  JTAG_CHAIN_OPTIONAL0 = 8,
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  JTAG_CHAIN_OPTIONAL1 = 9,
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  JTAG_CHAIN_OPTIONAL2 = 10,
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  JTAG_CHAIN_OPTIONAL3 = 11,
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  JTAG_CHAIN_OPTIONAL4 = 12,
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  JTAG_CHAIN_OPTIONAL5 = 13,
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  JTAG_CHAIN_OPTIONAL6 = 14,
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  JTAG_CHAIN_OPTIONAL7 = 15,
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} DebugScanChainIDs;
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typedef struct {
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  unsigned int DCR_hit;
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  unsigned int watchpoint;
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} DebugUnit;
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typedef enum {
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  DebugInstructionFetch = 1,
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  DebugLoadAddress = 2,
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  DebugStoreAddress = 3,
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  DebugLoadData = 4,
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  DebugStoreData = 5,
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} DebugUnitAction;
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/* Debug registers and their bits */
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typedef struct {
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  unsigned long moder;
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  unsigned long tsel;
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  unsigned long qsel;
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  unsigned long ssel;
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  unsigned long riscop;
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  unsigned long recwp[11];
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  unsigned long recbp;
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} DevelopmentInterface;
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typedef enum {
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  DEVELOPINT_MODER = 0,
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  DEVELOPINT_TSEL = 1,
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  DEVELOPINT_QSEL = 2,
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  DEVELOPINT_SSEL = 3,
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  DEVELOPINT_RISCOP = 4,
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  DEVELOPINT_RECWP0 = 16,
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  DEVELOPINT_RECWP1 = 17,
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  DEVELOPINT_RECWP2 = 18,
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  DEVELOPINT_RECWP3 = 19,
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  DEVELOPINT_RECWP4 = 20,
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  DEVELOPINT_RECWP5 = 21,
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  DEVELOPINT_RECWP6 = 22,
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  DEVELOPINT_RECWP7 = 23,
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  DEVELOPINT_RECWP8 = 24,
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  DEVELOPINT_RECWP9 = 25,
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  DEVELOPINT_RECWP10 = 26,
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  DEVELOPINT_RECBP0 = 27,
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} DevelopmentInterfaceAddressSpace;
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#define RISCOP_STALL  0x00000001
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#define RISCOP_RESET  0x00000002
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/* Resets the debug unit */
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void du_reset(void);
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/* do cycle-related initialisation (watchpoints etc.) */
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void du_clock();
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/* set cpu_stalled flag */
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void set_stall_state (int state);
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/* Whether debug unit should ignore exception */
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int debug_ignore_exception (unsigned long except);
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/* Gets development interface register */
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int get_devint_reg(unsigned int addr, unsigned long *data);
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/* Sets development interface register */
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int set_devint_reg(unsigned int addr, unsigned long data);
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/* Reads from bus address */
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int debug_get_mem(unsigned int address, unsigned long *data);
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/* Writes to bus address */
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int debug_set_mem(unsigned int address, unsigned long data);
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int DebugGetRegister(unsigned int address, unsigned long *data);
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int DebugSetRegister(unsigned int address, unsigned long data);
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int DebugSetChain(int chain);
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#ifdef DEBUGMOD_OFF
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#define CheckDebugUnit(x,y) 0
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#else
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int CheckDebugUnit(DebugUnitAction, unsigned long);
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#endif

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