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rherveille |
/*
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atahost.h -- ATA Host code simulation
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*
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* Definitions for the Opencores ATA Host Controller Core
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*/
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#ifndef __OR1KSIM_ATAH_H
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#define __OR1KSIM_ATAH_H
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#include "atadevice.h"
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/* --- Register definitions --- */
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/* ----- Core Registers */
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#define ATA_CTRL 0x00 /* Control register */
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#define ATA_STAT 0x04 /* Status register */
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#define ATA_PCTR 0x08 /* PIO command timing register */
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#define ATA_PFTR0 0x0c /* PIO Fast Timing register Device0 */
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#define ATA_PFTR1 0x10 /* PIO Fast Timing register Device1 */
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#define ATA_DTR0 0x14 /* DMA Timing register Device2 */
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#define ATA_DTR1 0x18 /* DMA Timing register Device1 */
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#define ATA_TXB 0x3c /* DMA Transmit buffer */
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#define ATA_RXB 0x3c /* DMA Receive buffer */
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/* ---------------------------- */
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/* ----- Bits definitions ----- */
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/* ---------------------------- */
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/* ----- Core Control register */
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/* bits 31-16 are reserved */
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#define ATA_DMA_EN (0<<15) /* DMAen, DMA enable bit */
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/* bit 14 is reserved */
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#define ATA_DMA_WR (1<<14) /* DMA Write transaction */
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#define ATA_DMA_RD (0<<14) /* DMA Read transaction */
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/* bits 13-10 are reserved */
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#define ATA_BELEC1 (1<< 9) /* Big-Little endian conversion */
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/* enable bit for Device1 */
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#define ATA_BELEC0 (1<< 8) /* Big-Little endian conversion */
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/* enable bit for Device0 */
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#define ATA_IDE_EN (1<< 7) /* IDE core enable bit */
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#define ATA_FTE1 (1<< 6) /* Device1 Fast PIO Timing Enable bit */
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#define ATA_FTE0 (1<< 5) /* Device0 Fast PIO Timing Enable bit */
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#define ATA_PWPP (1<< 4) /* PIO Write Ping-Pong Enable bit */
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#define ATA_IORDY_FTE1 (1<< 3) /* Device1 Fast PIO Timing IORDY */
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/* enable bit */
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#define ATA_IORDY_FTE0 (1<< 2) /* Device0 Fast PIO Timing IORDY */
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/* enable bit */
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#define ATA_IORDY (1<< 1) /* PIO Command Timing IORDY enable bit*/
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#define ATA_RST (1<< 0) /* ATA Reset bit */
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/* ----- Core Status register */
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#define ATA_DEVID 0xf0000000 /* bits 31-28 Device-ID */
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#define ATA_REVNO 0x0f000000 /* bits 27-24 Revision number */
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/* bits 23-16 are reserved */
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#define ATA_DMA_TIP (1<<15) /* DMA Transfer in progress */
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/* bits 14-10 are reserved */
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#define ATA_DRBE (1<<10) /* DMA Receive buffer empty */
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#define ATA_DTBF (1<< 9) /* DMA Transmit buffer full */
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#define ATA_DMARQ (1<< 8) /* DMARQ Line status */
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#define ATA_PIO_TIP (1<< 7 /* PIO Transfer in progress */
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#define ATA_PWPPF (1<< 6) /* PIO write ping-pong full */
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/* bits 5-1 are reserved */
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#define ATA_IDEIS (1<< 0) /* IDE Interrupt status */
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/* ----- Core Timing registers */
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#define ATA_TEOC 24 /* End of cycle time DMA/PIO */
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#define ATA_T4 16 /* DIOW- data hold time PIO */
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#define ATA_T2 8 /* DIOR-/DIOW- pulse width PIO */
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#define ATA_TD 8 /* DIOR-/DIOW- pulse width DMA */
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#define ATA_T1 0 /* Address valid to DIOR-/DIOW- PIO */
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#define ATA_TM 0 /* CS[1:0]valid to DIOR-/DIOW- DMA */
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/* ----------------------------- */
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/* ----- Simulator defines ----- */
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/* ----------------------------- */
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#define ATA_ADDR_SPACE 0x80
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/* ---------------------------- */
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/* ----- Structs ----- */
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/* ---------------------------- */
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typedef struct{
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/* Base address in memory */
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1350 |
nogj |
oraddr_t baseaddr;
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876 |
rherveille |
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/* Which IRQ to generate */
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int irq;
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/* Which ATA host is this? */
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unsigned ata_number;
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/* ata host registers */
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struct {
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int ctrl;
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int stat;
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int pctr;
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int pftr0;
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int pftr1;
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int dtr0;
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int dtr1;
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int txb;
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int rxb;
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} regs;
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/* connected ATA devices (slaves) */
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ata_devices devices;
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} ata_host;
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/* ---------------------------- */
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/* ----- Prototypes ----- */
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/* ---------------------------- */
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void ata_reset(void);
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1350 |
nogj |
uint32_t ata_read32( oraddr_t addr );
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void ata_write32( oraddr_t addr, uint32_t value );
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phoenix |
void ata_status(void);
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876 |
rherveille |
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/* ---------------------------- */
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/* ----- Macros ----- */
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/* ---------------------------- */
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#define is_ata_hostadr(adr) (!(adr & 0x40))
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rherveille |
// FIXME
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#define ata_pio_delay(pioreg) ( (((pioreg >> ATA_T1) & 0xff) +1) + (((pioreg >> ATA_T2) & 0xff) +1) + (((pioreg >> ATA_T4) & 0xff) +1) +1 )
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#define ata_dma_delay(dmareg) ( (((dmareg >> ATA_TD) & 0xff) +1) + (((pioreg >> ATA_TM) & 0xff) +1) +1 )
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876 |
rherveille |
#endif
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