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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [peripheral/] [dma.h] - Blame information for rev 1771

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/* dma.h -- Definition of types and structures for DMA
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   Copyright (C) 2001 by Erez Volk, erez@opencores.org
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 2 of the License, or
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   (at your option) any later version.
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   This program is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program; if not, write to the Free Software
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   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "dma_defs.h"
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/* Exported function prototypes */
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void dma_reset( void );
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void dma_clock( void );
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void dma_status( void );
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void set_dma_req_i( unsigned dma_controller, unsigned channel );
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void clear_dma_req_i( unsigned dma_controller, unsigned channel );
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void set_dma_nd_i( unsigned dma_controller, unsigned channel );
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void clear_dma_nd_i( unsigned dma_controller, unsigned channel );
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unsigned check_dma_ack_o( unsigned dma_controller, unsigned channel );
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/* Implementation of DMA Channel Registers and State */
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struct dma_channel
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{
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  /* The controller we belong to */
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  struct dma_controller *controller;
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  /* Our channel number and bit mask */
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  unsigned channel_number;
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  unsigned long channel_mask;
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  /* Used for dump, to save dumping all 32 channels */
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  unsigned referenced;
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  /* Inner state of transfer etc. */
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  unsigned load_next_descriptor_when_done;
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  unsigned long current_descriptor;
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  unsigned long source, destination, source_mask, destination_mask;
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  unsigned long chunk_size, total_size, words_transferred;
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  /* The interface registers */
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  struct
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  {
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    unsigned long csr;
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    unsigned long sz;
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    unsigned long a0;
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    unsigned long am0;
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    unsigned long a1;
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    unsigned long am1;
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    unsigned long desc;
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    unsigned long swptr;
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  } regs;
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  /* Some control signals */
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  unsigned dma_req_i;
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  unsigned dma_ack_o;
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  unsigned dma_nd_i;
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};
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/* Implementation of DMA Controller Registers and State */
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struct dma_controller
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{
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  /* Base address in memory */
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  oraddr_t baseaddr;
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  /* Which interrupt number we generate */
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  unsigned irq;
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  /* Controller Registers */
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  struct
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  {
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    unsigned long csr;
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    unsigned long int_msk_a;
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    unsigned long int_msk_b;
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    unsigned long int_src_a;
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    unsigned long int_src_b;
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  } regs;
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  /* Channels */
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  struct dma_channel ch[DMA_NUM_CHANNELS];
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};

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