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/* ethernet.c -- Simulation of Ethernet MAC

   Copyright (C) 2001 by Erez Volk, erez@opencores.org

                         Ivan Guzvinec, ivang@opencores.org

   This file is part of OpenRISC 1000 Architectural Simulator.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 2 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software

   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

*/

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <sys/types.h>

#include <sys/stat.h>   

#include <fcntl.h>      

#include <sys/poll.h>   

#include <sys/time.h>   

#include <unistd.h>     

#include <errno.h>

#include <netinet/in.h>

#include "config.h"

#ifdef HAVE_INTTYPES_H

#include <inttypes.h>

#endif

#include "port.h"

#include "arch.h"

#include "config.h"

#include "abstract.h"

#include "ethernet_i.h"

#include "dma.h"

#include "sim-config.h"

#include "fields.h"

#include "crc32.h"

#include "vapi.h"

#include "pic.h"

#include "debug.h"

static struct eth_device eths[MAX_ETHERNETS];

/* simulator interface */

static void eth_reset_controller( struct eth_device *eth);

static void eth_vapi_read( unsigned long id, unsigned long data);

/* register interface */

static void eth_write32( oraddr_t addr, uint32_t value );

static uint32_t eth_read32( oraddr_t addr );

/* clock */

static void eth_controller_tx_clock( struct eth_device * );

static void eth_controller_rx_clock( struct eth_device * );

/* utility functions */

static int eth_find_controller( oraddr_t addr, struct eth_device **eth, oraddr_t *reladdr );

struct eth_device *eth_find_vapi_device (unsigned long id, unsigned long *which);

static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );

static void eth_skip_rx_file( struct eth_device *, off_t );

static void eth_rewind_rx_file( struct eth_device *, off_t );

static void eth_rx_next_packet( struct eth_device * );

static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );

/* ========================================================================= */

/*  TX LOGIC                                                                 */

/*---------------------------------------------------------------------------*/

/*

 * TX clock

 * Responsible for starting and finishing TX

 */

void eth_controller_tx_clock( struct eth_device *eth )

{

    int breakpoint = 0;

    int bAdvance   = 1;

#if HAVE_ETH_PHY

    struct sockaddr_ll sll;

#endif /* HAVE_ETH_PHY */

    long nwritten;

    unsigned long read_word;

    switch (eth->tx.state) {

        case ETH_TXSTATE_IDLE:

        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {

            /* wait for TxBuffer to be ready */

                debug (3, "TX - entering state WAIT4BD (%ld)\n", eth->tx.bd_index);

            eth->tx.state = ETH_TXSTATE_WAIT4BD;

        }

        break;

    case ETH_TXSTATE_WAIT4BD:

        /* Read buffer descriptor */

        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];

        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];

        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {

            /*****************/

            /* initialize TX */

            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );

            eth->tx.bytes_sent = 0;

            /*   Initialize error status bits */

            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );

            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );

            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );

            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );

            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );

            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );

            /* Find out minimum length */

            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||

                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )

                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );

            else

                eth->tx.minimum_length = eth->tx.packet_length;

            /* Find out maximum length */

            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )

                eth->tx.maximum_length = eth->tx.packet_length;

            else

                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );

            /* Do we need CRC on this packet? */

            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||

                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&

                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )

                eth->tx.add_crc = 1;

            else

                eth->tx.add_crc = 0;

            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )

                eth->tx.crc_dly = 1;

            else

                eth->tx.crc_dly = 0;

            /* XXX - For now we skip CRC calculation */

            debug( 3, "Ethernet: Starting TX of %lu bytes (min. %u, max. %u)\n",

                   eth->tx.packet_length, eth->tx.minimum_length,

                   eth->tx.maximum_length );

            if (eth->rtx_type == ETH_RTX_FILE) {

                /* write packet length to file */

                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );

            }

            /************************************************/

            /* start transmit with reading packet into FIFO */

                debug (3, "TX - entering state READFIFO\n");

            eth->tx.state = ETH_TXSTATE_READFIFO;

        }

        else if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {

            /* stop TX logic */

                debug (3, "TX - entering state IDLE\n");

            eth->tx.state = ETH_TXSTATE_IDLE;

        }

        /* stay in this state if (TXEN && !READY) */

        break;

    case ETH_TXSTATE_READFIFO:

#if 1

        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {

            read_word = eval_direct32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);

            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);

            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);

            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);

            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);

            eth->tx.bytes_sent += 4;

        }

#else

        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {

            eth->tx_buff[eth->tx.bytes_sent] = eval_direct8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);

            eth->tx.bytes_sent += 1;

        }

#endif

        else {

            debug (3, "TX - entering state TRANSMIT\n");

            eth->tx.state = ETH_TXSTATE_TRANSMIT;

        }

        break;

    case ETH_TXSTATE_TRANSMIT:

        /* send packet */

        switch (eth->rtx_type) {

        case ETH_RTX_FILE:

            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );

            break;

#if HAVE_ETH_PHY

        case ETH_RTX_SOCK:

            memset(&sll, 0, sizeof(sll));

            sll.sll_ifindex = eth->ifr.ifr_ifindex;

            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));

#endif /* HAVE_ETH_PHY */

        }

        /* set BD status */

        if (nwritten == eth->tx.packet_length) {

            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);

            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);

            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);

            debug (3, "TX - entering state IDLE\n");

            eth->tx.state = ETH_TXSTATE_IDLE;

            debug (3, "send (%ld)bytes OK\n", nwritten);

        }

        else {

            /* XXX - implement retry mechanism here! */

            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);

            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);

            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);

            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);

            debug (3, "TX - entering state IDLE\n");

            eth->tx.state = ETH_TXSTATE_IDLE;

            debug (3, "send FAILED!\n");

        }

        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;

        /* generate OK interrupt */

        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||

             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )

        {

            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, IRQ ) )

                report_interrupt( eth->mac_int );

        }

        /* advance to next BD */

        if (bAdvance) {

            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||

                            eth->tx.bd_index >= ETH_BD_COUNT )

                eth->tx.bd_index = 0;

            else

                eth->tx.bd_index += 2;

        }

        break;

    }

}

/* ========================================================================= */

/* ========================================================================= */

/*  RX LOGIC                                                                 */

/*---------------------------------------------------------------------------*/

/*

 * RX clock

 * Responsible for starting and finishing RX

 */

void eth_controller_rx_clock( struct eth_device *eth )

{

    int breakpoint = 0;

    long nread;

    unsigned long send_word;

    switch (eth->rx.state) {

    case ETH_RXSTATE_IDLE:

        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) ) {

                debug (3, "RX - entering state WAIT4BD (%ld)\n", eth->rx.bd_index);

            eth->rx.state = ETH_RXSTATE_WAIT4BD;

        }

        break;

    case ETH_RXSTATE_WAIT4BD:

        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];

        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];

        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {

            /*****************/

            /* Initialize RX */

            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );

            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );

            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );

            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );

            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );

            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );

            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );

            debug( 3,  "Ethernet: Starting RX\n" );

            /* Setup file to read from */

            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {

                eth->rx.fd = eth->txfd;

                eth->rx.offset = &(eth->loopback_offset);

            } else {

                eth->rx.fd = eth->rxfd;

                eth->rx.offset = 0;

            }

            debug (3, "RX - entering state RECV\n");

            eth->rx.state = ETH_RXSTATE_RECV;

        }

        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {

          debug (3, "RX - entering state IDLE\n");

          eth->rx.state = ETH_RXSTATE_IDLE;

        }

        else {

            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);

            if (nread > 0) {

                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);

                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )

                  report_interrupt(eth->mac_int);

            }

        }

        break;

    case ETH_RXSTATE_RECV:

        switch (eth->rtx_type) {

        case ETH_RTX_FILE:

            /* Read packet length */

            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )

                     < sizeof(eth->rx.packet_length) ) {

                /* TODO: just do what real ethernet would do (some kind of error state) */

                debug (4, "eth_start_rx(): File does not have a packet ready for RX (len = %ld)\n", eth->rx.packet_length );

                runtime.sim.cont_run = 0;

                break;

            }

            /* Packet must be big enough to hold a header */

            if ( eth->rx.packet_length < ETHER_HDR_LEN ){

                debug( 3,  "eth_start_rx(): Packet too small\n" );

                eth_rx_next_packet( eth );

                debug (3, "RX - entering state IDLE\n");

                eth->rx.state = ETH_RXSTATE_IDLE;

                break;

            }

            eth->rx.bytes_read = 0;

            eth->rx.bytes_left = eth->rx.packet_length;

            /* for now Read entire packet into memory */

            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );

            if ( nread < eth->rx.bytes_left ) {

                debug (3, "Read %ld from %ld. Error!\n", nread, eth->rx.bytes_left);

                eth->rx.error = 1;

                break;

            }

            eth->rx.packet_length = nread;

            eth->rx.bytes_left = nread;

            eth->rx.bytes_read = 0;

            debug (3, "RX - entering state WRITEFIFO\n");

            eth->rx.state = ETH_RXSTATE_WRITEFIFO;

            break;

        case ETH_RTX_SOCK:

            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);

            if (nread == 0)

                break;

            else if (nread < 0) {

                if ( errno != EAGAIN ) {

                    debug (3, "recv() FAILED!\n");

                    break;

                }

                else break;

            }

            /* If not promiscouos mode, check the destination address */

            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {

                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {

                /* Nothing for now */

                }

                if (eth->mac_address[5] != eth->rx_buff[0] ||

                    eth->mac_address[4] != eth->rx_buff[1] ||

                    eth->mac_address[3] != eth->rx_buff[2] ||

                    eth->mac_address[2] != eth->rx_buff[3] ||

                    eth->mac_address[1] != eth->rx_buff[4] ||

                    eth->mac_address[0] != eth->rx_buff[5])

                    break;

            }

            eth->rx.packet_length = nread;

            eth->rx.bytes_left = nread;

            eth->rx.bytes_read = 0;

            debug (3, "RX - entering state WRITEFIFO\n");

            eth->rx.state = ETH_RXSTATE_WRITEFIFO;

            break;

        case ETH_RTX_VAPI:

          break;

        }

        break;

    case ETH_RXSTATE_WRITEFIFO:

#if 1

        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |

                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |

                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |

                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );

        set_direct32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint, 0, 0);

        /* update counters */

        debug (3, "Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,

               eth->rx.bytes_left, send_word);

        eth->rx.bytes_left -= 4;

        eth->rx.bytes_read += 4;

#else

        set_direct8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint, 0, 0);

        eth->rx.bytes_left -= 1;

        eth->rx.bytes_read += 1;

#endif

        if ( eth->rx.bytes_left <= 0 ) {

            /* Write result to bd */

            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );

            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);

            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);

            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);

            if ( eth->rx.packet_length < (GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) - 4) )

                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);

            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )

                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);

            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;

            /* advance to next BD */

            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )

                eth->rx.bd_index = eth->regs.tx_bd_num << 1;

            else

                eth->rx.bd_index += 2;

            if ( ( TEST_FLAG( eth->regs.int_mask, ETH_INT_MASK, RXB_M ) ) &&

                 ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, IRQ )              ) ) {

                report_interrupt( eth->mac_int );

            }

            /* ready to receive next packet */

                debug (3, "RX - entering state IDLE\n");

            eth->rx.state = ETH_RXSTATE_IDLE;

        }

        break;

    }

}

/* ========================================================================= */

/* Move to next RX BD */

void eth_rx_next_packet( struct eth_device *eth )

{

    /* Skip any possible leftovers */

    if ( eth->rx.bytes_left )

        eth_skip_rx_file( eth, eth->rx.bytes_left );

}

/* "Skip" bytes in RX file */

void eth_skip_rx_file( struct eth_device *eth, off_t count )

{

    eth->rx.offset += count;

}

/* Move RX file position back */

void eth_rewind_rx_file( struct eth_device *eth, off_t count )

{

    eth->rx.offset -= count;

}

/*

 * Utility function to read from the ethernet RX file

 * This function moves the file pointer to the current place in the packet before reading

 */

ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )

{

    ssize_t result;

    if ( eth->rx.fd <= 0 ) {

        debug( 3,  "Ethernet: No RX file\n" );

        return 0;

    }

    if ( eth->rx.offset )

        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {

            debug( 3,  "Ethernet: Error seeking RX file\n" );

            return 0;

        }

    result = read( eth->rx.fd, buf, count );

    debug (4, "Ethernet: read result = %d \n", result);

    if ( eth->rx.offset && result >= 0 )

        *(eth->rx.offset) += result;

    return result;

}

/* ========================================================================= */

/*

  Reset. Initializes all registers to default and places devices in

         memory address space.

*/

void eth_reset()

{

    static int first_time = 1;

    unsigned i;

    if (!config.nethernets)

        return;

    if ( first_time )

        memset( eths, 0, sizeof(eths) );

    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {

        struct eth_device *eth = &(eths[i]);

        if (!HAVE_ETH_PHY && eth->rtx_type == ETH_RTX_SOCK) {

          fprintf (stderr, "Ethernet phy not enabled in this configuration.  Configure with --enable-ethphy.\n");

          exit (1);

        }

        eth->eth_number = i;

        eth_reset_controller( eth );

        if ( eth->baseaddr && first_time )

            register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, 0, eth_read32, eth_write32 );

    }

    if ( first_time )

        first_time = 0;

}

/* ========================================================================= */

static void eth_reset_controller(struct eth_device *eth)

{

    int i = eth->eth_number;

#if HAVE_ETH_PHY

    int j;

    struct sockaddr_ll sll;

#endif /* HAVE_ETH_PHY */

    eth->baseaddr = config.ethernets[i].baseaddr;

    if ( eth->baseaddr != 0 ) {

        /* Mark which DMA controller and channels */

        eth->dma        = config.ethernets[i].dma;

        eth->mac_int    = config.ethernets[i].irq;

        eth->tx_channel = config.ethernets[i].tx_channel;

        eth->rx_channel = config.ethernets[i].rx_channel;

        eth->rtx_type   = config.ethernets[i].rtx_type;

        switch (eth->rtx_type) {

        case ETH_RTX_FILE:

            /* (Re-)open TX/RX files */

            eth->rxfile = config.ethernets[i].rxfile;

            eth->txfile = config.ethernets[i].txfile;

            if ( eth->rxfd > 0 )

                close( eth->rxfd );

            if ( eth->txfd > 0 )

                close( eth->txfd );

            eth->rxfd = eth->txfd = -1;

            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )

                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );

            if ( (eth->txfd = open( eth->txfile,

                                    O_RDWR | O_CREAT | O_APPEND

#if defined(O_SYNC)     /* BSD / Mac OS X manual doesn't know about O_SYNC */

                                                                        | O_SYNC

#endif

                                                                        ,

                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )

                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );

            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );

            break;

#if HAVE_ETH_PHY

        case ETH_RTX_SOCK:

            /* (Re-)open TX/RX sockets */

            if (eth->rtx_sock != 0)

                break;

            debug (3, "RTX oppening socket...\n");

            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));

            if (eth->rtx_sock == -1) {

                fprintf( stderr, "Cannot open rtx_sock.\n");

                return;

            }

            /* get interface index number */

            debug (3, "RTX getting interface...\n");

            memset(&(eth->ifr), 0, sizeof(eth->ifr));