Subversion Repositories or1k

What is this stuff?

===================

This is OpenRISC 1000 and DLX architectural simulator. It was written by

Damjan Lampret and it is free software. See the file COPYING for copying

permission. To contact the author, send mail to .

I use it to define OR1K system architecture. An implementation simulator

for OR1K will be also available, probably in Mar/2000 or later.

Initially this software was not meant to be released to public because it

was developed just to analyze program flow of GCC generated assembly code.

With the time it became bigger and was able to generate statistics about

superscalar issuing of multiple instructions. I've used it as a test simulator

to test OR1K GCC port. Perhaps some day I will (or perhaps someone else would

like to do that ??) clean-up the code and reorganize it.

This simulator loads an assembly file for one of the both architectures

and it simulates the operation of instructions. Because it was meant to be used

only to test characteristics of various RISC architectures and various GCC

optimization methods, it has a bit strange memory model. It is abstract and

physical at the same time. I can't really explain, just check the sources if

interested. Some other things are strange or incomplete too (like

C library emulation, currently supports only printf via simprintf).

MMU directory is not functional. Someday it will be filled with code for

virtual memory simulation.

Installation

============

To compile, run the configure script and specify the target architecture.

Example:

  $ ./configure --target=or32

After that, just issue "make all" command. By default there should be no

warnings. There is no "make install". Just use it from default location

or copy it to your bin directory (usually something like /usr/local/bin

or ~/bin).

This program hasn't been written with security in mind. It has many static

buffers and it does not check the size of input strings (user commands

or whatever). So don't setuid it. If it kills your dog, don't blame it on me.

To select DLX simulation, change the target to the configure script to 'dlx'

and recompile everything (do 'make all' again).

Simulator test

==============

Issue 'sim testbench/dhry.or32' or 'sim testbench/dhry.dlx' to

test simulator. See testbench/README for details about Dhrystone 2.1

benchmark.

For microkernel test (exception test) undefine ONLY_VIRTUAL_MACHINE (you want

exceptions, right !) in cpu/or1k/except.h and recompile simulator. A compiled

and linked version should already exist in testbench/uos. Just issue

'sim testbench/uos/uos.or32' from the top level sim directory. Currently only

OR32 is supported by UOS.

OpenRISC and open cores

=======================

About the same idea as with GNU project except we want free and open source

IP (intellectual property) cores. We design open source, synthesizable

cores. OpenRISC is one such core. It is a 32-bit RISC microprocessor that

will run GNU/Linux.

For more information visit us at http://www.opencores.org.

--

29/Feb/2000, Damjan Lampret email:lampret@opencores.org

03/Mar/2000, Johan Rydberg email:johan.rydberg@netinsight.net

04/May/2000, Jimmy Chen-Min Chen email:jimmy@ee.nctu.edu.tw