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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cache/] [dcache_model.c] - Blame information for rev 1486

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1 5 lampret
/* dcache_model.c -- data cache simulation
2
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
This program is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 2 of the License, or
9
(at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20
/* Cache functions.
21
   At the moment this functions only simulate functionality of data
22
   caches and do not influence on fetche/decode/execute stages and timings.
23
   They are here only to verify performance of various cache configurations.
24
 */
25
 
26
#include <stdio.h>
27
#include <string.h>
28
#include <errno.h>
29
#include <stdarg.h>
30
 
31 1350 nogj
#include "config.h"
32
 
33
#ifdef HAVE_INTTYPES_H
34
#include <inttypes.h>
35
#endif
36
 
37
#include "port.h"
38
#include "arch.h"
39 5 lampret
#include "dcache_model.h"
40
#include "abstract.h"
41 992 simons
#include "except.h"
42 1344 nogj
#include "opcode/or32.h"
43 1432 nogj
#include "spr_defs.h"
44
#include "execute.h"
45 5 lampret
#include "stats.h"
46 102 lampret
#include "sprs.h"
47 428 markom
#include "sim-config.h"
48 5 lampret
 
49
/* Data cache */
50
 
51
struct dc_set {
52 428 markom
  struct {
53 1350 nogj
    uint32_t line[MAX_DC_BLOCK_SIZE];
54
    oraddr_t tagaddr;  /* tag address */
55 428 markom
    int lru;    /* least recently used */
56
  } way[MAX_DC_WAYS];
57
} dc[MAX_DC_SETS];
58 5 lampret
 
59
void dc_info()
60
{
61 428 markom
  if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
62 997 markom
    PRINTF("DCache not implemented. Set UPR[DCP].\n");
63 428 markom
    return;
64
  }
65
 
66 997 markom
  PRINTF("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
67
  PRINTF("%d ways, %d sets, block size %d bytes\n", config.dc.nways, config.dc.nsets, config.dc.blocksize);
68 5 lampret
}
69
 
70
/* First check if data is already in the cache and if it is:
71
    - increment DC read hit stats,
72 428 markom
    - set 'lru' at this way to config.dc.ustates - 1 and
73 5 lampret
      decrement 'lru' of other ways unless they have reached 0,
74
   and if not:
75
    - increment DC read miss stats
76
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
77 428 markom
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
78 5 lampret
      ways unless they have reached 0
79 631 simons
    - refill cache line
80 5 lampret
*/
81
 
82 1486 nogj
uint32_t dc_simulate_read(oraddr_t dataaddr, oraddr_t virt_addr, int width)
83 5 lampret
{
84 428 markom
  int set, way = -1;
85
  int i;
86 1350 nogj
  oraddr_t tagaddr;
87
  uint32_t tmp;
88 102 lampret
 
89 638 simons
  if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
90
      (!testsprbits(SPR_SR, SPR_SR_DCE))   ||
91
      data_ci) {
92 631 simons
    if (width == 4)
93 1486 nogj
      tmp = evalsim_mem32(dataaddr, virt_addr);
94 631 simons
    else if (width == 2)
95 1486 nogj
      tmp = evalsim_mem16(dataaddr, virt_addr);
96 631 simons
    else if (width == 1)
97 1486 nogj
      tmp = evalsim_mem8(dataaddr, virt_addr);
98 992 simons
 
99 1486 nogj
    if (cur_area && cur_area->log)
100 1350 nogj
      fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,
101
               tmp);
102 992 simons
 
103
    return tmp;
104 631 simons
  }
105 102 lampret
 
106 428 markom
  /* Which set to check out? */
107
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
108
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
109
 
110
  /* Scan all ways and try to find a matching way. */
111
  for (i = 0; i < config.dc.nways; i++)
112
    if (dc[set].way[i].tagaddr == tagaddr)
113
      way = i;
114
 
115
  /* Did we find our cached data? */
116
  if (way >= 0) { /* Yes, we did. */
117
    dc_stats.readhit++;
118 541 markom
 
119 428 markom
    for (i = 0; i < config.dc.nways; i++)
120 631 simons
      if (dc[set].way[i].lru > dc[set].way[way].lru)
121 428 markom
        dc[set].way[i].lru--;
122
    dc[set].way[way].lru = config.dc.ustates - 1;
123 884 markom
    runtime.sim.mem_cycles += config.dc.load_hitdelay;
124 631 simons
 
125
    tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
126
    if (width == 4)
127
      return tmp;
128
    else if (width == 2) {
129 1350 nogj
      tmp = ((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
130 631 simons
      return tmp;
131
    }
132
    else if (width == 1) {
133 1350 nogj
      tmp = ((tmp  >> (8 * (3 - (dataaddr & 3)))) & 0xff);
134 631 simons
      return tmp;
135
    }
136 541 markom
  } else {  /* No, we didn't. */
137 428 markom
    int minlru = config.dc.ustates - 1;
138
    int minway = 0;
139 5 lampret
 
140 631 simons
    dc_stats.readmiss++;
141 5 lampret
 
142 1085 simons
    for (i = 0; i < config.dc.nways; i++) {
143
      if (dc[set].way[i].lru < minlru) {
144 428 markom
        minway = i;
145 1085 simons
        minlru = dc[set].way[i].lru;
146
      }
147
    }
148 428 markom
 
149 631 simons
    for (i = 0; i < (config.dc.blocksize); i += 4) {
150
      dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
151 1486 nogj
        /* FIXME: What is the virtual address meant to be? (ie. What happens if
152
         * we read out of memory while refilling a cache line?) */
153
        evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~ADDR_C(3)) + i) & (config.dc.blocksize - 1)), 0);
154 638 simons
      if(!cur_area) {
155
        dc[set].way[minway].tagaddr = -1;
156
        dc[set].way[minway].lru = 0;
157 631 simons
        return 0;
158 1386 nogj
      } else if (cur_area->log)
159 1350 nogj
        fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", dataaddr,
160
                 tmp);
161 631 simons
    }
162
 
163 428 markom
    dc[set].way[minway].tagaddr = tagaddr;
164
    for (i = 0; i < config.dc.nways; i++)
165
      if (dc[set].way[i].lru)
166
        dc[set].way[i].lru--;
167
    dc[set].way[minway].lru = config.dc.ustates - 1;
168 884 markom
    runtime.sim.mem_cycles += config.dc.load_missdelay;
169 631 simons
 
170
    tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
171
    if (width == 4)
172
      return tmp;
173
    else if (width == 2) {
174 1350 nogj
      tmp = (tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff;
175 631 simons
      return tmp;
176
    }
177
    else if (width == 1) {
178 1350 nogj
      tmp = (tmp  >> (8 * (3 - (dataaddr & 3)))) & 0xff;
179 631 simons
      return tmp;
180
    }
181 428 markom
  }
182 5 lampret
}
183
 
184
/* First check if data is already in the cache and if it is:
185
    - increment DC write hit stats,
186 428 markom
    - set 'lru' at this way to config.dc.ustates - 1 and
187 5 lampret
      decrement 'lru' of other ways unless they have reached 0,
188
   and if not:
189
    - increment DC write miss stats
190
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
191 428 markom
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
192 5 lampret
      ways unless they have reached 0
193
*/
194
 
195 1486 nogj
void dc_simulate_write(oraddr_t dataaddr, oraddr_t virt_addr, uint32_t data,
196
                       int width)
197 5 lampret
{
198 428 markom
  int set, way = -1;
199
  int i;
200 1350 nogj
  oraddr_t tagaddr;
201
  uint32_t tmp;
202 102 lampret
 
203 631 simons
  if (width == 4)
204 1486 nogj
    setsim_mem32(dataaddr, virt_addr, data);
205 631 simons
  else if (width == 2)
206 1486 nogj
    setsim_mem16(dataaddr, virt_addr, data);
207 631 simons
  else if (width == 1)
208 1486 nogj
    setsim_mem8(dataaddr, virt_addr, data);
209 631 simons
 
210 638 simons
  if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
211
      (!testsprbits(SPR_SR, SPR_SR_DCE)) ||
212
      data_ci ||
213
      (!cur_area))
214 631 simons
    return;
215 428 markom
 
216
  /* Which set to check out? */
217
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
218
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
219
 
220
  /* Scan all ways and try to find a matching way. */
221
  for (i = 0; i < config.dc.nways; i++)
222
    if (dc[set].way[i].tagaddr == tagaddr)
223
      way = i;
224
 
225
  /* Did we find our cached data? */
226
  if (way >= 0) { /* Yes, we did. */
227
    dc_stats.writehit++;
228
 
229
    for (i = 0; i < config.dc.nways; i++)
230 631 simons
      if (dc[set].way[i].lru > dc[set].way[way].lru)
231 428 markom
        dc[set].way[i].lru--;
232
    dc[set].way[way].lru = config.dc.ustates - 1;
233 884 markom
    runtime.sim.mem_cycles += config.dc.store_hitdelay;
234 631 simons
 
235
    tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
236
    if (width == 4)
237
      tmp = data;
238
    else if (width == 2) {
239
      tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
240 1350 nogj
      tmp |= (data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
241 631 simons
    }
242
    else if (width == 1) {
243
      tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
244 1350 nogj
      tmp |= (data & 0xff) << (8 * (3 - (dataaddr & 3)));
245 631 simons
    }
246
    dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] = tmp;
247 428 markom
  }
248
  else {  /* No, we didn't. */
249
    int minlru = config.dc.ustates - 1;
250
    int minway = 0;
251 5 lampret
 
252 631 simons
    dc_stats.writemiss++;
253 5 lampret
 
254 428 markom
    for (i = 0; i < config.dc.nways; i++)
255 631 simons
      if (dc[set].way[i].lru < minlru)
256 428 markom
        minway = i;
257
 
258 631 simons
    for (i = 0; i < (config.dc.blocksize); i += 4) {
259
      dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
260 1486 nogj
        /* FIXME: Same comment as in dc_simulate_read */
261
        evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)), 0);
262 638 simons
      if(!cur_area) {
263
        dc[set].way[minway].tagaddr = -1;
264
        dc[set].way[minway].lru = 0;
265 631 simons
        return;
266 638 simons
      }
267 631 simons
    }
268
 
269 428 markom
    dc[set].way[minway].tagaddr = tagaddr;
270
    for (i = 0; i < config.dc.nways; i++)
271
      if (dc[set].way[i].lru)
272
        dc[set].way[i].lru--;
273
    dc[set].way[minway].lru = config.dc.ustates - 1;
274 884 markom
    runtime.sim.mem_cycles += config.dc.store_missdelay;
275 428 markom
  }
276 5 lampret
}
277 102 lampret
 
278
/* First check if data is already in the cache and if it is:
279
    - invalidate block if way isn't locked
280
   otherwise don't do anything.
281
*/
282
 
283 1350 nogj
void dc_inv(oraddr_t dataaddr)
284 102 lampret
{
285 428 markom
  int set, way = -1;
286
  int i;
287 1350 nogj
  oraddr_t tagaddr;
288 102 lampret
 
289 428 markom
  if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
290
    return;
291 102 lampret
 
292 428 markom
  /* Which set to check out? */
293
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
294
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
295
 
296 631 simons
  if (!testsprbits(SPR_SR, SPR_SR_DCE)) {
297
    for (i = 0; i < config.dc.nways; i++) {
298
      dc[set].way[i].tagaddr = -1;
299
      dc[set].way[i].lru = 0;
300
    }
301
    return;
302
  }
303
   /* Scan all ways and try to find a matching way. */
304 428 markom
  for (i = 0; i < config.dc.nways; i++)
305
    if (dc[set].way[i].tagaddr == tagaddr)
306
      way = i;
307
 
308
  /* Did we find our cached data? */
309 631 simons
  if (way >= 0) { /* Yes, we did. */
310 428 markom
    dc[set].way[way].tagaddr = -1;
311 631 simons
    dc[set].way[way].lru = 0;
312 428 markom
  }
313 102 lampret
}
314
 
315 1358 nogj
/*-----------------------------------------------------[ DC configuration ]---*/
316
void dc_enabled(union param_val val, void *dat)
317
{
318
  config.dc.enabled = val.int_val;
319
  setsprbits (SPR_UPR, SPR_UPR_DCP, val.int_val ? 1 : 0);
320
}
321
 
322
void dc_nsets(union param_val val, void *dat)
323
{
324 1382 nogj
  if (is_power2(val.int_val) && val.int_val <= MAX_DC_SETS){
325 1358 nogj
    config.dc.nsets = val.int_val;
326 1382 nogj
    setsprbits (SPR_DCCFGR, SPR_DCCFGR_NCS, log2(val.int_val));
327
  }
328 1358 nogj
  else {
329
    char tmp[200];
330
    sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_DC_SETS);
331
    CONFIG_ERROR(tmp);
332
  }
333
}
334
 
335
void dc_nways(union param_val val, void *dat)
336
{
337 1382 nogj
  if (is_power2(val.int_val) && val.int_val <= MAX_DC_WAYS){
338 1358 nogj
    config.dc.nways = val.int_val;
339 1382 nogj
    setsprbits (SPR_DCCFGR, SPR_DCCFGR_NCW, log2(val.int_val));
340
  }
341
  else{
342
    char tmp[200];
343
    sprintf (tmp, "value of power of two and lower or equal than %i expected.",
344
    MAX_DC_WAYS);
345
    CONFIG_ERROR(tmp);
346
  }
347 1358 nogj
}
348
 
349
void dc_blocksize(union param_val val, void *dat)
350
{
351 1382 nogj
  if (is_power2(val.int_val)) {
352 1358 nogj
    config.dc.blocksize = val.int_val;
353 1382 nogj
    setsprbits (SPR_DCCFGR, SPR_DCCFGR_CBS,log2(val.int_val));
354
  } else
355 1358 nogj
    CONFIG_ERROR("value of power of two expected.");
356
}
357
 
358
void dc_ustates(union param_val val, void *dat)
359
{
360
  if (val.int_val >= 2 && val.int_val <= 4)
361
    config.dc.ustates = val.int_val;
362
  else
363
    CONFIG_ERROR("invalid USTATE.");
364
}
365
 
366
void dc_load_missdelay(union param_val val, void *dat)
367
{
368
  config.dc.load_missdelay = val.int_val;
369
}
370
 
371
void dc_load_hitdelay(union param_val val, void *dat)
372
{
373
  config.dc.load_hitdelay = val.int_val;
374
}
375
 
376
void dc_store_missdelay(union param_val val, void *dat)
377
{
378
  config.dc.store_missdelay = val.int_val;
379
}
380
 
381
void dc_store_hitdelay(union param_val val, void *dat)
382
{
383
  config.dc.store_hitdelay = val.int_val;
384
}
385
 
386
void reg_dc_sec(void)
387
{
388
  struct config_section *sec = reg_config_sec("dc", NULL, NULL);
389
 
390
  reg_config_param(sec, "enabled", paramt_int, dc_enabled);
391
  reg_config_param(sec, "nsets", paramt_int, dc_nsets);
392
  reg_config_param(sec, "nways", paramt_int, dc_nways);
393
  reg_config_param(sec, "blocksize", paramt_int, dc_blocksize);
394
  reg_config_param(sec, "ustates", paramt_int, dc_ustates);
395
  reg_config_param(sec, "load_missdelay", paramt_int, dc_load_missdelay);
396
  reg_config_param(sec, "load_hitdelay", paramt_int, dc_load_hitdelay);
397
  reg_config_param(sec, "store_missdelay", paramt_int, dc_store_missdelay);
398
  reg_config_param(sec, "store_hitdelay", paramt_int, dc_store_hitdelay);
399
}

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