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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cache/] [dcache_model.c] - Blame information for rev 638

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1 5 lampret
/* dcache_model.c -- data cache simulation
2
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
This program is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
9
(at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20
/* Cache functions.
21
   At the moment this functions only simulate functionality of data
22
   caches and do not influence on fetche/decode/execute stages and timings.
23
   They are here only to verify performance of various cache configurations.
24
 */
25
 
26
#include <stdio.h>
27
#include <string.h>
28
#include <errno.h>
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#include <stdarg.h>
30
 
31
#include "dcache_model.h"
32
#include "abstract.h"
33
#include "stats.h"
34 102 lampret
#include "spr_defs.h"
35
#include "sprs.h"
36 428 markom
#include "sim-config.h"
37 5 lampret
 
38
/* Data cache */
39
 
40
struct dc_set {
41 428 markom
  struct {
42 631 simons
    unsigned long line[MAX_DC_BLOCK_SIZE];
43 428 markom
    unsigned long tagaddr;  /* tag address */
44
    int lru;    /* least recently used */
45
  } way[MAX_DC_WAYS];
46
} dc[MAX_DC_SETS];
47 5 lampret
 
48
void dc_info()
49
{
50 428 markom
  if (!testsprbits(SPR_UPR, SPR_UPR_DCP)) {
51
    printf("DCache not implemented. Set UPR[DCP].\n");
52
    return;
53
  }
54
 
55
  printf("Data cache %dKB: ", config.dc.nsets * config.dc.blocksize * config.dc.nways / 1024);
56
  printf("%d ways, %d sets, block size %d bytes\n", config.dc.nways, config.dc.nsets, config.dc.blocksize);
57 5 lampret
}
58
 
59
/* First check if data is already in the cache and if it is:
60
    - increment DC read hit stats,
61 428 markom
    - set 'lru' at this way to config.dc.ustates - 1 and
62 5 lampret
      decrement 'lru' of other ways unless they have reached 0,
63
   and if not:
64
    - increment DC read miss stats
65
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
66 428 markom
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
67 5 lampret
      ways unless they have reached 0
68 631 simons
    - refill cache line
69 5 lampret
*/
70
 
71 631 simons
unsigned long dc_simulate_read(unsigned long dataaddr, int width)
72 5 lampret
{
73 428 markom
  int set, way = -1;
74
  int i;
75
  unsigned long tagaddr;
76 541 markom
  extern int mem_cycles;
77 631 simons
  unsigned long tmp;
78 102 lampret
 
79 638 simons
  if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
80
      (!testsprbits(SPR_SR, SPR_SR_DCE))   ||
81
      data_ci) {
82 631 simons
    if (width == 4)
83
      return evalsim_mem32(dataaddr);
84
    else if (width == 2)
85
      return (unsigned long)evalsim_mem16(dataaddr);
86
    else if (width == 1)
87
      return (unsigned long)evalsim_mem8(dataaddr);
88
  }
89 102 lampret
 
90 428 markom
  /* Which set to check out? */
91
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
92
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
93
 
94
  /* Scan all ways and try to find a matching way. */
95
  for (i = 0; i < config.dc.nways; i++)
96
    if (dc[set].way[i].tagaddr == tagaddr)
97
      way = i;
98
 
99
  /* Did we find our cached data? */
100
  if (way >= 0) { /* Yes, we did. */
101
    dc_stats.readhit++;
102 541 markom
 
103 428 markom
    for (i = 0; i < config.dc.nways; i++)
104 631 simons
      if (dc[set].way[i].lru > dc[set].way[way].lru)
105 428 markom
        dc[set].way[i].lru--;
106
    dc[set].way[way].lru = config.dc.ustates - 1;
107 541 markom
    mem_cycles += config.dc.load_hitdelay;
108 631 simons
 
109
    tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
110
    if (width == 4)
111
      return tmp;
112
    else if (width == 2) {
113
      tmp = (unsigned long)((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
114
      return tmp;
115
    }
116
    else if (width == 1) {
117
      tmp = (unsigned long)((tmp  >> (8 * (3 - (dataaddr & 3)))) & 0xff);
118
      return tmp;
119
    }
120 541 markom
  } else {  /* No, we didn't. */
121 428 markom
    int minlru = config.dc.ustates - 1;
122
    int minway = 0;
123 5 lampret
 
124 631 simons
    dc_stats.readmiss++;
125 5 lampret
 
126 428 markom
    for (i = 0; i < config.dc.nways; i++)
127 631 simons
      if (dc[set].way[i].lru < minlru)
128 428 markom
        minway = i;
129
 
130 631 simons
    for (i = 0; i < (config.dc.blocksize); i += 4) {
131
      dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
132
        evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
133 638 simons
      if(!cur_area) {
134
        dc[set].way[minway].tagaddr = -1;
135
        dc[set].way[minway].lru = 0;
136 631 simons
        return 0;
137 638 simons
      }
138 631 simons
    }
139
 
140 428 markom
    dc[set].way[minway].tagaddr = tagaddr;
141
    for (i = 0; i < config.dc.nways; i++)
142
      if (dc[set].way[i].lru)
143
        dc[set].way[i].lru--;
144
    dc[set].way[minway].lru = config.dc.ustates - 1;
145 541 markom
    mem_cycles += config.dc.load_missdelay;
146 631 simons
 
147
    tmp = dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
148
    if (width == 4)
149
      return tmp;
150
    else if (width == 2) {
151
      tmp = (unsigned long)((tmp >> ((dataaddr & 2) ? 0 : 16)) & 0xffff);
152
      return tmp;
153
    }
154
    else if (width == 1) {
155
      tmp = (unsigned long)((tmp  >> (8 * (3 - (dataaddr & 3)))) & 0xff);
156
      return tmp;
157
    }
158 428 markom
  }
159 5 lampret
}
160
 
161
/* First check if data is already in the cache and if it is:
162
    - increment DC write hit stats,
163 428 markom
    - set 'lru' at this way to config.dc.ustates - 1 and
164 5 lampret
      decrement 'lru' of other ways unless they have reached 0,
165
   and if not:
166
    - increment DC write miss stats
167
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
168 428 markom
    - set 'lru' with config.dc.ustates - 1 and decrement 'lru' of other
169 5 lampret
      ways unless they have reached 0
170
*/
171
 
172 631 simons
void dc_simulate_write(unsigned long dataaddr, unsigned long data, int width)
173 5 lampret
{
174 428 markom
  int set, way = -1;
175
  int i;
176
  unsigned long tagaddr;
177 541 markom
  extern int mem_cycles;
178 631 simons
  unsigned long tmp;
179 102 lampret
 
180 631 simons
  if (width == 4)
181
    setsim_mem32(dataaddr, data);
182
  else if (width == 2)
183
    setsim_mem16(dataaddr, (unsigned short)data);
184
  else if (width == 1)
185
    setsim_mem8(dataaddr, (unsigned char)data);
186
 
187 638 simons
  if ((!testsprbits(SPR_UPR, SPR_UPR_DCP)) ||
188
      (!testsprbits(SPR_SR, SPR_SR_DCE)) ||
189
      data_ci ||
190
      (!cur_area))
191 631 simons
    return;
192 428 markom
 
193
  /* Which set to check out? */
194
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
195
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
196
 
197
  /* Scan all ways and try to find a matching way. */
198
  for (i = 0; i < config.dc.nways; i++)
199
    if (dc[set].way[i].tagaddr == tagaddr)
200
      way = i;
201
 
202
  /* Did we find our cached data? */
203
  if (way >= 0) { /* Yes, we did. */
204
    dc_stats.writehit++;
205
 
206
    for (i = 0; i < config.dc.nways; i++)
207 631 simons
      if (dc[set].way[i].lru > dc[set].way[way].lru)
208 428 markom
        dc[set].way[i].lru--;
209
    dc[set].way[way].lru = config.dc.ustates - 1;
210 541 markom
    mem_cycles += config.dc.store_hitdelay;
211 631 simons
 
212
    tmp = dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2];
213
    if (width == 4)
214
      tmp = data;
215
    else if (width == 2) {
216
      tmp &= 0xffff << ((dataaddr & 2) ? 16 : 0);
217
      tmp |= (unsigned long)(data & 0xffff) << ((dataaddr & 2) ? 0 : 16);
218
    }
219
    else if (width == 1) {
220
      tmp &= ~(0xff << (8 * (3 - (dataaddr & 3))));
221
      tmp |= (unsigned long)(data & 0xff) << (8 * (3 - (dataaddr & 3)));
222
    }
223
    dc[set].way[way].line[(dataaddr & (config.dc.blocksize - 1)) >> 2] = tmp;
224 428 markom
  }
225
  else {  /* No, we didn't. */
226
    int minlru = config.dc.ustates - 1;
227
    int minway = 0;
228 5 lampret
 
229 631 simons
    dc_stats.writemiss++;
230 5 lampret
 
231 428 markom
    for (i = 0; i < config.dc.nways; i++)
232 631 simons
      if (dc[set].way[i].lru < minlru)
233 428 markom
        minway = i;
234
 
235 631 simons
    for (i = 0; i < (config.dc.blocksize); i += 4) {
236
      dc[set].way[minway].line[((dataaddr + i) & (config.dc.blocksize - 1)) >> 2] =
237
        evalsim_mem32((dataaddr & ~(config.dc.blocksize - 1)) + (((dataaddr & ~3ul)+ i) & (config.dc.blocksize - 1)));
238 638 simons
      if(!cur_area) {
239
        dc[set].way[minway].tagaddr = -1;
240
        dc[set].way[minway].lru = 0;
241 631 simons
        return;
242 638 simons
      }
243 631 simons
    }
244
 
245 428 markom
    dc[set].way[minway].tagaddr = tagaddr;
246
    for (i = 0; i < config.dc.nways; i++)
247
      if (dc[set].way[i].lru)
248
        dc[set].way[i].lru--;
249
    dc[set].way[minway].lru = config.dc.ustates - 1;
250 541 markom
    mem_cycles += config.dc.store_missdelay;
251 428 markom
  }
252 5 lampret
}
253 102 lampret
 
254
/* First check if data is already in the cache and if it is:
255
    - invalidate block if way isn't locked
256
   otherwise don't do anything.
257
*/
258
 
259
void dc_inv(unsigned long dataaddr)
260
{
261 428 markom
  int set, way = -1;
262
  int i;
263
  unsigned long tagaddr;
264 102 lampret
 
265 428 markom
  if (!testsprbits(SPR_UPR, SPR_UPR_DCP))
266
    return;
267 102 lampret
 
268 428 markom
  /* Which set to check out? */
269
  set = (dataaddr / config.dc.blocksize) % config.dc.nsets;
270
  tagaddr = (dataaddr / config.dc.blocksize) / config.dc.nsets;
271
 
272 631 simons
  if (!testsprbits(SPR_SR, SPR_SR_DCE)) {
273
    for (i = 0; i < config.dc.nways; i++) {
274
      dc[set].way[i].tagaddr = -1;
275
      dc[set].way[i].lru = 0;
276
    }
277
    return;
278
  }
279
   /* Scan all ways and try to find a matching way. */
280 428 markom
  for (i = 0; i < config.dc.nways; i++)
281
    if (dc[set].way[i].tagaddr == tagaddr)
282
      way = i;
283
 
284
  /* Did we find our cached data? */
285 631 simons
  if (way >= 0) { /* Yes, we did. */
286 428 markom
    dc[set].way[way].tagaddr = -1;
287 631 simons
    dc[set].way[way].lru = 0;
288 428 markom
  }
289 102 lampret
}
290
 
291 261 markom
inline void dc_clock()
292 102 lampret
{
293 428 markom
  unsigned long addr;
294
 
295
  if (addr = mfspr(SPR_DCBPR)) {
296 631 simons
    dc_simulate_read(addr, 4);
297 428 markom
    mtspr(SPR_DCBPR, 0);
298
  }
299 631 simons
  if ((addr = mfspr(SPR_DCBFR)) != -1) {
300 428 markom
    dc_inv(addr);
301 631 simons
    mtspr(SPR_DCBFR, -1);
302 428 markom
  }
303
  if (addr = mfspr(SPR_DCBIR)) {
304
    dc_inv(addr);
305
    mtspr(SPR_DCBIR, 0);
306
  }
307
  if (addr = mfspr(SPR_DCBWR)) {
308
    mtspr(SPR_DCBWR, 0);
309
  }
310
  if (addr = mfspr(SPR_DCBLR)) {
311
    mtspr(SPR_DCBLR, 0);
312
  }
313 102 lampret
}

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