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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cache/] [icache_model.h] - Blame information for rev 1350

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Line No. Rev Author Line
1 5 lampret
/* icache_model.h -- instruction cache header file
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   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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   This file is part of OpenRISC 1000 Architectural Simulator.
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License as published by
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   the Free Software Foundation; either version 2 of the License, or
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   (at your option) any later version.
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   This program is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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   GNU General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program; if not, write to the Free Software
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   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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20 429 markom
#define MAX_IC_SETS 8192
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#define MAX_IC_WAYS 4
22 631 simons
#define MAX_IC_BLOCK_SIZE 4 /* In words */
23 5 lampret
 
24 1350 nogj
uint32_t ic_simulate_fetch(oraddr_t fetchaddr);
25 1308 phoenix
void ic_info();
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void ic_clock();

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