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/* abstract.c -- Abstract entities
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Abstract memory and routines that go with this. I need to
add all sorts of other abstract entities. Currently we have
only memory. */
 
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
 
#include "arch.h"
#include "parse.h"
#include "abstract.h"
#include "sim-config.h"
#include "labels.h"
#include "execute.h"
#include "sprs.h"
#include "except.h"
#include "debug_unit.h"
#include "opcode/or32.h"
#include "support/profile.h"
#include "dmmu.h"
#include "dcache_model.h"
#include "icache_model.h"
#include "debug.h"
#include "stats.h"
 
extern char *disassembled;
 
/* Pointer to memory area descriptions that are assigned to individual
   peripheral devices. */
struct dev_memarea *dev_list;
 
/* Temporary variable to increase speed.  */
struct dev_memarea *cur_area;
 
/* Pointer to memory controller device descriptor.  */
struct dev_memarea *mc_area = (struct dev_memarea *)0;
 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
int data_ci, insn_ci;
 
/* Virtual address of current access. */
oraddr_t cur_vadd;
 
/* Calculates bit mask to fit the data */
unsigned int bit_mask (uint32_t data) {
  int i = 0;
  data--;
  while (data >> i)
    data |= 1 << i++;
  return data;
}
 
/* Register read and write function for a memory area.
   addr is inside the area, if addr & addr_mask == addr_compare
   (used also by peripheral devices like 16450 UART etc.) */
void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,
                         uint32_t size, unsigned granularity, unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  struct dev_memarea **pptmp;
  unsigned int size_mask = bit_mask (size);
  int found_error = 0;
  addr_compare &= addr_mask;
 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",
        addr_mask, addr_compare, addr_compare | bit_mask (size), size,
        granularity);
  /* Go to the end of the list. */
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
      if (!found_error) {
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                         ", size %08"PRIx32", gran %iB\n",
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size,
                 granularity);
      }
      found_error = 1;
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                       ", size %08"PRIx32", gran %iB\n",
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
               (*pptmp)->addr_compare | (*pptmp)->size_mask,
               (*pptmp)->size, (*pptmp)->granularity);
    }
 
  if (found_error)
    exit (-1);
 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
 
  if (mc_dev)
    mc_area = *pptmp;
 
  (*pptmp)->addr_mask = addr_mask;
  (*pptmp)->addr_compare = addr_compare;
  (*pptmp)->size = size;
  (*pptmp)->size_mask = size_mask;
  (*pptmp)->granularity = granularity;
  (*pptmp)->readfunc = readfunc;
  (*pptmp)->writefunc = writefunc;
  (*pptmp)->log = 0;
  (*pptmp)->delayr = 2;
  (*pptmp)->delayw = 2;
  (*pptmp)->priv_dat = dat;
  (*pptmp)->next = NULL;
}
 
/* Register read and write function for a memory area.
   Memory areas should be aligned. Memory area is rounded up to
   fit the nearest 2^n aligment.
   (used also by peripheral devices like 16450 UART etc.)
   If mc_dev is 1, this means that this device will be checked first for match
   and will be accessed in case of overlaping memory spaces.
   Only one device can have this set to 1 (used for memory controller) */
void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,
                         unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  unsigned int size_mask = bit_mask (size);
  unsigned int addr_mask = ~size_mask;
  register_memoryarea_mask (addr_mask, addr & addr_mask,
                      size_mask + 1, granularity, mc_dev,
                      readfunc, writefunc, dat);
}
 
 
/* Check if access is to registered area of memory. */
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
{
  struct dev_memarea *ptmp;
 
  /* Check memory controller space first */
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
    return cur_area = mc_area;
 
  /* Check cached value */
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
    return cur_area;
 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
  IFF (config.mc.enabled) {
    /* Check list of registered devices. */
    for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
      if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
        return cur_area = ptmp;
  } else {
    /* Check list of registered devices. */
    for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
      if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask))
        return cur_area = ptmp;
  }
  return cur_area = NULL;
}
 
/* Finds the memory area for the address and adjust the read and write delays for it. */
void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)
{
  if (verify_memoryarea(memaddr)) {
    cur_area->delayr = delayr;
    cur_area->delayw = delayw;
  }
}
 
/* for cpu accesses
 *
 * STATISTICS: check cpu/common/parse.c
 */
inline uint32_t evalsim_mem32(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint32_t evalsim_mem32_void(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 0));
}
 
uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      break;
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
    if (cpu_access)
      runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);
  }
  return temp;
}
 
/* for cpu accesses */
inline uint16_t evalsim_mem16(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint16_t evalsim_mem16_void(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 0));
}
 
uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr * 2;
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);
      if (memaddr & 2)
        temp &= 0xffff;
      else
        temp >>= 16;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline uint8_t evalsim_mem8(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint8_t evalsim_mem8_void(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 0));
}
 
uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 2:
      temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);
      if (memaddr & 1)
        temp &= 0xff;
      else
        temp >>= 8;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);
      temp >>= 8 * (3 - (memaddr & 3));
      temp &= 0xff;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * this function is only used in dumpmemory() below, so it's
 * safe to asume it's for simulator purposes access only,
 * hence the use of eval_mem32_void()
 *
 * STATISTICS OK.
 */
static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  cur_vadd = memaddr;
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
  temp = evalsim_mem32_void(memaddr);
  if (!cur_area) {
    PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
    temp = 0;
  }
 
  if (!pending.valid && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_READ);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (pending.valid)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK
 */
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR
             ") in eval_direct32()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_insn(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
//  memaddr = simulate_ic_mmu_fetch(memaddr);
  cur_vadd = pc;
 
  // I think this does not belong into eval_insn() 2004-01-30 HP
//  if (config.debug.enabled)
//    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  // We could place the CheckDebugUnit(DebugInstructionFetch) here, but it is currently done
  // in decode_execute_wrapper, so I leave it like this. 2004-01-30 HP
 
  if (config.ic.enabled)
    temp = ic_simulate_fetch(memaddr);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  // I think this does not belong into eval_insn() 2004-01-30 HP
//  if (config.debug.enabled)
//    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* Returns 16-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
{
  uint16_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_READ);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (pending.valid)
    return 0;
 
  if (config.dc.enabled)
    temp = (unsigned short)dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR
             ") in eval_direct16()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 8-bit values from mem array.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
{
  uint8_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (pending.valid)
    return 0;
 
  if (config.dc.enabled)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
                     int through_dc)
{
  uint8_t temp;
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR
             ") in eval_direct8()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline void setsim_mem32(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem32_void(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 0));
}
 
void setsim_mem32_atomic(oraddr_t memaddr, uint32_t value, int cpu_access)
{
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 1:
      cur_area->writefunc(memaddr    , (value >> 24) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, (value >>  8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 3, (value      ) & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 4;
      break;
    case 2:
      cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem16(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem16_void(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 0));
}
 
void setsim_mem16_atomic(oraddr_t memaddr, uint16_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, (value >> 8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, value & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    case 2:
      cur_area->writefunc(memaddr, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 4:
      temp = evalsim_mem32_void(memaddr & ~ADDR_C(3));
      temp &= 0xffff << ((memaddr & 2) ? 16 : 0);
      temp |= (unsigned long)(value & 0xffff) << ((memaddr & 2) ? 0 : 16);
      setsim_mem32_atomic(memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem8(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem8_void(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 0));
}
 
void setsim_mem8_atomic(oraddr_t memaddr, uint8_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch (cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 2:
      temp = evalsim_mem16_void (memaddr & ~ADDR_C(1));
      temp &= 0xff << ((memaddr & 1) ? 8 : 0);
      temp |= (unsigned short)(value & 0xff) << ((memaddr & 1) ? 0 : 8);
      setsim_mem16_atomic (memaddr & ~ADDR_C(1), temp, cpu_access);
      break;
    case 4:
      temp = evalsim_mem32_void (memaddr & ~ADDR_C(3));
      temp &= ~(0xff << (8 * (3 - (memaddr & 3))));
      temp |= (unsigned long)(value & 0xff) << (8 * (3 - (memaddr & 3)));
      setsim_mem32_atomic (memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* Set mem, 32-bit. Big endian version.
 *
 * STATISTICS OK. (the only suspicious usage is in toplevel.c,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 */
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (pending.valid)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 1, through_dc);
  }
 
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
             memaddr, value);
}
 
 
/* Set mem, 16-bit. Big endian version. */
 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (pending.valid)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, (unsigned long)value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
             memaddr, value);
}
 
/* Set mem, 8-bit. */
 
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (pending.valid) return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, (unsigned long)value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
                 int through_mmu, int through_dc)
{
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
             memaddr, value);
}
 
 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
{
  oraddr_t i, j;
  struct label_entry *tmp;
  int ilen = disasm ? 4 : 16;
 
  for(i = from; i < to; i += ilen) {
    PRINTF("%"PRIxADDR": ", i);
    for (j = 0; j < ilen;) {
      if (!disasm) {
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
          PRINTF("%02"PRIx8" ", evalsim_mem8(i + j));
        } else PRINTF("XX ");
        j++;
      } else {
        int breakpoint;
        uint32_t _insn = read_mem(i, &breakpoint);
        int index = insn_decode (_insn);
        int len = insn_len (index);
 
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
 
          PRINTF(": %08"PRIx32" ", _insn);
          if (index >= 0) {
            disassemble_insn (_insn);
            PRINTF(" %s", disassembled);
          } else
            PRINTF("<invalid>");
        } else PRINTF("XXXXXXXX");
        j += len;
      }
    }
    if (nl)
      PRINTF ("\n");
  }
}
 
uint32_t simmem_read_word(oraddr_t addr, void *priv_dat) {
  return *(uint32_t *)(priv_dat + (addr & cur_area->size_mask));
}
 
void simmem_write_word(oraddr_t addr, uint32_t value, void *priv_dat) {
  *(uint32_t *)(priv_dat + (addr & cur_area->size_mask)) = value;
}
 
uint32_t simmem_read_zero(oraddr_t addr, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory read from non-read memory area 0x%"
                     PRIxADDR".\n", addr);
  return 0;
}
 
void simmem_write_null(oraddr_t addr, uint32_t value, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory write to 0x%"PRIxADDR", non-write memory area (value 0x%08"PRIx32").\n", addr, value);
}
 
/* Initialize memory table from a config struct */
 
void init_memory_table ()
{
  /* If nothing was defined, use default memory block */
  if (config.memory.nmemories) {
    int i;
    for (i = 0; i < config.memory.nmemories; i++) {
      oraddr_t start = config.memory.table[i].baseaddr;
      uint32_t length = config.memory.table[i].size;
      char *type = config.memory.table[i].name;
      int rd = config.memory.table[i].delayr;
      int wd = config.memory.table[i].delayw;
      int ce = config.memory.table[i].ce;
      void *mem = malloc (length);
 
      if (config.sim.verbose)
        debug (1, "%"PRIxADDR" %08"PRIx32" (%"PRIi32" KB): %s (activated by CE%i; read delay = %icyc, write delay = %icyc)\n",
          start, length, length >> 10, type, ce, rd, wd);
 
      if (!mem) {
        fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
        exit (-1);
      }
 
      register_memoryarea(start, length, 4, 0, &simmem_read_word,
                          &simmem_write_word, mem);
      cur_area->chip_select = ce;
      cur_area->valid = 1;
      cur_area->delayw = wd;
      cur_area->delayr = rd;
      if (config.memory.table[i].log[0] != '\0') {
        if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
          fprintf (stderr, "WARNING: Cannot open '%s'.\n",
                   config.memory.table[i].log);
      } else
        cur_area->log = NULL;
    }
    PRINTF ("\n");
  } else {
    void *mem = malloc (DEFAULT_MEMORY_LEN);
    if (config.sim.verbose)
      fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
 
    if (!mem) {
      fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
      exit (-1);
    }
 
    register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, 0,
                        &simmem_read_word, &simmem_write_word, mem);
    cur_area->chip_select = 0;
    cur_area->valid = 1;
    cur_area->delayw = 1;
    cur_area->delayr = 1;
    cur_area->log = NULL;
  }
}
 
/* Changes read/write memory in read/write only */
 
void lock_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->delayr < 0 && ptmp->readfunc == &simmem_read_word)
      ptmp->readfunc = &simmem_read_zero;
    if (ptmp->delayw < 0 && ptmp->writefunc == &simmem_write_word)
      ptmp->writefunc = &simmem_write_null;
 
    /* If this mem area is not for memory chip under MC control
       then this area is valid all the time */
    if (ptmp->readfunc != &simmem_read_word) {
      ptmp->valid = 1;
      ptmp->chip_select = -1;
    }
  }
}
 
/* Closes files, etc. */
 
void done_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->log)
      fclose (ptmp->log);
  }
}
 
/* Displays current memory configuration */
 
void memory_table_status ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32
            ", gran %iB\n",
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
      ptmp->size, ptmp->granularity);
    PRINTF ("\t");
    if (ptmp->delayr >= 0)
      PRINTF ("read delay = %i cycles, ", ptmp->delayr);
    else
      PRINTF ("reads not possible, ");
 
    if (ptmp->delayw >= 0)
      PRINTF ("write delay = %i cycles", ptmp->delayw);
    else
      PRINTF ("writes not possible");
 
    if (ptmp->log)
      PRINTF (", (logged)\n");
    else
      PRINTF ("\n");
  }
}
 
/* Outputs time in pretty form to dest string */
 
char *generate_time_pretty (char *dest, long time_ps)
{
  int exp3 = 0;
  if (time_ps) {
    while ((time_ps % 1000) == 0) {
      time_ps /= 1000;
      exp3++;
    }
  }
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
  return dest;
}

Line No.	Rev	Author	Line
1	2	cvs	`/* abstract.c -- Abstract entities`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20	66	lampret	`/* Abstract memory and routines that go with this. I need to`
21	2	cvs	`add all sorts of other abstract entities. Currently we have`
22			`only memory. */`
23
24	221	markom	`#include <stdlib.h>`
25	2	cvs	`#include <stdio.h>`
26			`#include <ctype.h>`
27			`#include <string.h>`
28
29	6	lampret	`#include "config.h"`
30	1350	nogj
31			`#ifdef HAVE_INTTYPES_H`
32			`#include <inttypes.h>`
33			`#endif`
34
35			`#include "port.h"`
36	6	lampret
37	1350	nogj	`#include "arch.h"`
38	2	cvs	`#include "parse.h"`
39			`#include "abstract.h"`
40	1358	nogj	`#include "sim-config.h"`
41	261	markom	`#include "labels.h"`
42	2	cvs	`#include "execute.h"`
43	32	lampret	`#include "sprs.h"`
44			`#include "except.h"`
45	123	markom	`#include "debug_unit.h"`
46	134	markom	`#include "opcode/or32.h"`
47	547	markom	`#include "support/profile.h"`
48	1308	phoenix	`#include "dmmu.h"`
49			`#include "dcache_model.h"`
50			`#include "icache_model.h"`
51			`#include "debug.h"`
52	1344	nogj	`#include "stats.h"`
53	2	cvs
54	138	markom	`extern char *disassembled;`
55	2	cvs
56	30	lampret	`/* Pointer to memory area descriptions that are assigned to individual`
57			`peripheral devices. */`
58			`struct dev_memarea *dev_list;`
59
60	221	markom	`/* Temporary variable to increase speed. */`
61			`struct dev_memarea *cur_area;`
62
63	970	simons	`/* Pointer to memory controller device descriptor. */`
64			`struct dev_memarea mc_area = (struct dev_memarea )0;`
65
66	638	simons	`/* These are set by mmu if cache inhibit bit is set for current acces. */`
67			`int data_ci, insn_ci;`
68
69	525	simons	`/* Virtual address of current access. */`
70	1350	nogj	`oraddr_t cur_vadd;`
71	525	simons
72	261	markom	`/* Calculates bit mask to fit the data */`
73	1350	nogj	`unsigned int bit_mask (uint32_t data) {`
74	261	markom	`int i = 0;`
75			`data--;`
76	382	markom	`while (data >> i)`
77	261	markom	`data \|= 1 << i++;`
78			`return data;`
79			`}`
80
81			`/* Register read and write function for a memory area.`
82			`addr is inside the area, if addr & addr_mask == addr_compare`
83			`(used also by peripheral devices like 16450 UART etc.) */`
84	1350	nogj	`void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,`
85			`uint32_t size, unsigned granularity, unsigned mc_dev,`
86	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
87			`void (writefunc)(oraddr_t, uint32_t, void *),`
88			`void *dat)`
89	30	lampret	`{`
90	239	markom	`struct dev_memarea **pptmp;`
91	1350	nogj	`unsigned int size_mask = bit_mask (size);`
92	261	markom	`int found_error = 0;`
93			`addr_compare &= addr_mask;`
94	221	markom
95	1350	nogj	`debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",`
96			`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
97			`granularity);`
98	239	markom	`/* Go to the end of the list. */`
99	261	markom	`for(pptmp = &dev_list; pptmp; pptmp = &(pptmp)->next)`
100			`if ((addr_compare >= (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)`
101			`\|\| (addr_compare + size > (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)) {`
102	262	markom	`if (!found_error) {`
103	261	markom	`fprintf (stderr, "ERROR: Overlapping memory area(s):\n");`
104	1350	nogj	`fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
105			`", size %08"PRIx32", gran %iB\n",`
106	1308	phoenix	`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
107			`granularity);`
108	262	markom	`}`
109	261	markom	`found_error = 1;`
110	1350	nogj	`fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
111			`", size %08"PRIx32", gran %iB\n",`
112	1308	phoenix	`(pptmp)->addr_mask, (pptmp)->addr_compare,`
113			`(pptmp)->addr_compare \| (pptmp)->size_mask,`
114			`(pptmp)->size, (pptmp)->granularity);`
115	261	markom	`}`
116
117			`if (found_error)`
118			`exit (-1);`
119	537	markom
120	239	markom	`cur_area = pptmp = (struct dev_memarea )malloc(sizeof(struct dev_memarea));`
121	970	simons
122			`if (mc_dev)`
123			`mc_area = *pptmp;`
124
125	261	markom	`(*pptmp)->addr_mask = addr_mask;`
126			`(*pptmp)->addr_compare = addr_compare;`
127	239	markom	`(*pptmp)->size = size;`
128	261	markom	`(*pptmp)->size_mask = size_mask;`
129	239	markom	`(*pptmp)->granularity = granularity;`
130			`(*pptmp)->readfunc = readfunc;`
131			`(*pptmp)->writefunc = writefunc;`
132	479	markom	`(*pptmp)->log = 0;`
133	882	simons	`(*pptmp)->delayr = 2;`
134			`(*pptmp)->delayw = 2;`
135	1359	nogj	`(*pptmp)->priv_dat = dat;`
136	239	markom	`(*pptmp)->next = NULL;`
137	261	markom	`}`
138	221	markom
139	261	markom	`/* Register read and write function for a memory area.`
140			`Memory areas should be aligned. Memory area is rounded up to`
141			`fit the nearest 2^n aligment.`
142	970	simons	`(used also by peripheral devices like 16450 UART etc.)`
143			`If mc_dev is 1, this means that this device will be checked first for match`
144	1359	nogj	`and will be accessed in case of overlaping memory spaces.`
145	970	simons	`Only one device can have this set to 1 (used for memory controller) */`
146	1350	nogj	`void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,`
147			`unsigned mc_dev,`
148	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
149			`void (writefunc)(oraddr_t, uint32_t, void *),`
150			`void *dat)`
151	261	markom	`{`
152	1350	nogj	`unsigned int size_mask = bit_mask (size);`
153			`unsigned int addr_mask = ~size_mask;`
154	261	markom	`register_memoryarea_mask (addr_mask, addr & addr_mask,`
155	970	simons	`size_mask + 1, granularity, mc_dev,`
156	1359	nogj	`readfunc, writefunc, dat);`
157	30	lampret	`}`
158
159	261	markom
160	30	lampret	`/* Check if access is to registered area of memory. */`
161	1350	nogj	`inline struct dev_memarea *verify_memoryarea(oraddr_t addr)`
162	30	lampret	`{`
163	239	markom	`struct dev_memarea *ptmp;`
164	221	markom
165	970	simons	`/* Check memory controller space first */`
166			`if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))`
167			`return cur_area = mc_area;`
168
169			`/* Check cached value */`
170	560	markom	`if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))`
171			`return cur_area;`
172
173			`/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */`
174			`IFF (config.mc.enabled) {`
175			`/* Check list of registered devices. */`
176			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
177			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)`
178			`return cur_area = ptmp;`
179			`} else {`
180			`/* Check list of registered devices. */`
181			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
182			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask))`
183			`return cur_area = ptmp;`
184			`}`
185	239	markom	`return cur_area = NULL;`
186	30	lampret	`}`
187
188	882	simons	`/* Finds the memory area for the address and adjust the read and write delays for it. */`
189	1350	nogj	`void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)`
190	882	simons	`{`
191			`if (verify_memoryarea(memaddr)) {`
192			`cur_area->delayr = delayr;`
193			`cur_area->delayw = delayw;`
194			`}`
195			`}`
196
197	1319	phoenix	`/* for cpu accesses`
198			`*`
199			`* STATISTICS: check cpu/common/parse.c`
200			`*/`
201	1350	nogj	`inline uint32_t evalsim_mem32(oraddr_t memaddr)`
202	560	markom	`{`
203	1319	phoenix	`return(evalsim_mem32_atomic(memaddr, 1));`
204			`}`
205	560	markom
206	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
207	1350	nogj	`inline uint32_t evalsim_mem32_void(oraddr_t memaddr)`
208	1319	phoenix	`{`
209			`return(evalsim_mem32_atomic(memaddr, 0));`
210			`}`
211
212	1350	nogj	`uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)`
213	1319	phoenix	`{`
214	1350	nogj	`uint32_t temp = 0;`
215	1319	phoenix
216	560	markom	`if (verify_memoryarea(memaddr)) {`
217			`switch(cur_area->granularity) {`
218			`case 4:`
219	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
220	560	markom	`break;`
221			`case 1:`
222	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;`
223			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;`
224			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;`
225			`temp \|= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);`
226	560	markom	`break;`
227			`case 2:`
228	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;`
229			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);`
230	560	markom	`break;`
231	1319	phoenix	`default:`
232			`/* if you add new memory granularity be sure to check the formula`
233			`* below for the read delay and fix it if necessery`
234			`*/`
235			`PRINTF("unknown/unhandled memory granularuty\n");`
236			`exit(-1);`
237	560	markom	`}`
238	1319	phoenix	`if (cpu_access)`
239			`runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);`
240	560	markom	`}`
241			`return temp;`
242			`}`
243
244	1319	phoenix	`/* for cpu accesses */`
245	1350	nogj	`inline uint16_t evalsim_mem16(oraddr_t memaddr)`
246	560	markom	`{`
247	1319	phoenix	`return(evalsim_mem16_atomic(memaddr, 1));`
248			`}`
249	560	markom
250	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
251	1350	nogj	`inline uint16_t evalsim_mem16_void(oraddr_t memaddr)`
252	1319	phoenix	`{`
253			`return(evalsim_mem16_atomic(memaddr, 0));`
254			`}`
255
256	1350	nogj	`uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)`
257	1319	phoenix	`{`
258	1350	nogj	`uint32_t temp = 0;`
259	1319	phoenix
260	560	markom	`if (verify_memoryarea(memaddr)) {`
261			`switch(cur_area->granularity) {`
262			`case 1:`
263	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;`
264			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);`
265	1319	phoenix	`if (cpu_access)`
266			`runtime.sim.mem_cycles += cur_area->delayr * 2;`
267	560	markom	`break;`
268			`case 2:`
269	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
270	1319	phoenix	`if (cpu_access)`
271			`runtime.sim.mem_cycles += cur_area->delayr;`
272	560	markom	`break;`
273			`case 4:`
274	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);`
275	560	markom	`if (memaddr & 2)`
276			`temp &= 0xffff;`
277			`else`
278			`temp >>= 16;`
279			`break;`
280	1319	phoenix	`default:`
281			`/* if you add new memory granularity be sure to check the formula`
282			`* below for the read delay and fix it if necessery`
283			`*/`
284			`PRINTF("unknown/unhandled memory granularuty\n");`
285			`exit(-1);`
286	560	markom	`}`
287			`}`
288			`return temp;`
289			`}`
290
291	1319	phoenix	`/* for cpu accesses */`
292	1350	nogj	`inline uint8_t evalsim_mem8(oraddr_t memaddr)`
293	560	markom	`{`
294	1319	phoenix	`return(evalsim_mem8_atomic(memaddr, 1));`
295			`}`
296	560	markom
297	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
298	1350	nogj	`inline uint8_t evalsim_mem8_void(oraddr_t memaddr)`
299	1319	phoenix	`{`
300			`return(evalsim_mem8_atomic(memaddr, 0));`
301			`}`
302
303	1350	nogj	`uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)`
304	1319	phoenix	`{`
305	1350	nogj	`uint32_t temp = 0;`
306	1319	phoenix
307	560	markom	`if (verify_memoryarea(memaddr)) {`
308			`switch(cur_area->granularity) {`
309			`case 1:`
310	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
311	1319	phoenix	`if (cpu_access)`
312			`runtime.sim.mem_cycles += cur_area->delayr;`
313	560	markom	`break;`
314			`case 2:`
315	1350	nogj	`temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);`
316	560	markom	`if (memaddr & 1)`
317			`temp &= 0xff;`
318			`else`
319			`temp >>= 8;`
320			`break;`
321			`case 4:`
322	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);`
323	560	markom	`temp >>= 8 * (3 - (memaddr & 3));`
324			`temp &= 0xff;`
325			`break;`
326	1319	phoenix	`default:`
327			`/* if you add new memory granularity be sure to check the formula`
328			`* below for the read delay and fix it if necessery`
329			`*/`
330			`PRINTF("unknown/unhandled memory granularuty\n");`
331			`exit(-1);`
332	560	markom	`}`
333			`}`
334			`return temp;`
335			`}`
336
337	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
338			`*`
339	1350	nogj	`* this function is only used in dumpmemory() below, so it's`
340	1319	phoenix	`* safe to asume it's for simulator purposes access only,`
341			`* hence the use of eval_mem32_void()`
342			`*`
343			`* STATISTICS OK.`
344			`*/`
345	1350	nogj	`static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)`
346	349	simons	`{`
347	1350	nogj	`uint32_t temp;`
348	349	simons
349	525	simons	`cur_vadd = memaddr;`
350	550	markom	`if (config.debug.enabled)`
351	349	simons	`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
352	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
353	611	simons	`if (!cur_area) {`
354	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
355			`memaddr);`
356	611	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
357			`temp = 0;`
358			`}`
359
360	599	simons	`if (!pending.valid && cur_area->log)`
361	1350	nogj	`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);`
362	550	markom	`if (config.debug.enabled)`
363	349	simons	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
364			`return temp;`
365	537	markom	`}`
366	349	simons
367	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
368			`*`
369			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
370			`*/`
371	1350	nogj	`uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)`
372	2	cvs	`{`
373	1350	nogj	`uint32_t temp;`
374	123	markom
375	547	markom	`if (config.sim.mprofile)`
376			`mprofile (memaddr, MPROF_32 \| MPROF_READ);`
377
378	538	markom	`if (memaddr & 3) {`
379			`except_handle (EXCEPT_ALIGN, memaddr);`
380			`return 0;`
381			`}`
382	557	markom
383	631	simons	`if (config.debug.enabled)`
384			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
385
386	574	markom	`cur_vadd = memaddr;`
387	631	simons
388			`memaddr = dmmu_translate(memaddr, 0);`
389	574	markom	`if (pending.valid)`
390			`return 0;`
391
392	992	simons	`if (config.dc.enabled)`
393			`temp = dc_simulate_read(memaddr, 4);`
394			`else {`
395			`temp = evalsim_mem32(memaddr);`
396			`if (!cur_area) {`
397	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
398			`memaddr);`
399	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
400			`temp = 0;`
401			`}`
402	611	simons	`}`
403
404	550	markom	`if (config.debug.enabled)`
405	270	markom	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
406	239	markom	`return temp;`
407	66	lampret	`}`
408
409	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do`
410			`*`
411			`* STATISTICS OK`
412			`*/`
413	1350	nogj	`uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,`
414			`int through_dc)`
415	1240	phoenix	`{`
416	1350	nogj	`uint32_t temp;`
417	1240	phoenix
418			`if (memaddr & 3) {`
419			`PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);`
420			`return 0;`
421			`}`
422
423			`cur_vadd = memaddr;`
424
425			`if (through_mmu)`
426			`memaddr = peek_into_dtlb(memaddr, 0, through_dc);`
427
428			`if (through_dc)`
429			`temp = dc_simulate_read(memaddr, 4);`
430			`else {`
431	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
432	1240	phoenix	`if (!cur_area) {`
433	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR`
434			`") in eval_direct32()\n", memaddr);`
435	1240	phoenix	`except_handle(EXCEPT_BUSERR, cur_vadd);`
436			`temp = 0;`
437			`}`
438			`}`
439
440			`return temp;`
441			`}`
442
443
444	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
445			`*`
446			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
447			`*/`
448	1350	nogj	`uint32_t eval_insn(oraddr_t memaddr,int* breakpoint)`
449	349	simons	`{`
450	1350	nogj	`uint32_t temp;`
451	349	simons
452	547	markom	`if (config.sim.mprofile)`
453			`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`
454	532	markom	`// memaddr = simulate_ic_mmu_fetch(memaddr);`
455	525	simons	`cur_vadd = pc;`
456	1244	hpanther
457			`// I think this does not belong into eval_insn() 2004-01-30 HP`
458			`// if (config.debug.enabled)`
459			`// breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
460
461			`// We could place the CheckDebugUnit(DebugInstructionFetch) here, but it is currently done`
462			`// in decode_execute_wrapper, so I leave it like this. 2004-01-30 HP`
463
464	631	simons	`if (config.ic.enabled)`
465			`temp = ic_simulate_fetch(memaddr);`
466	992	simons	`else {`
467	631	simons	`temp = evalsim_mem32(memaddr);`
468	992	simons	`if (!cur_area) {`
469	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
470			`memaddr);`
471	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
472			`temp = 0;`
473			`}`
474	611	simons	`}`
475
476	1244	hpanther	`// I think this does not belong into eval_insn() 2004-01-30 HP`
477			`// if (config.debug.enabled)`
478			`// breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
479	349	simons	`return temp;`
480			`}`
481
482	1319	phoenix	`/* Returns 16-bit values from mem array. Big endian version.`
483			`*`
484			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
485			`*/`
486	1350	nogj	`uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)`
487	2	cvs	`{`
488	1350	nogj	`uint16_t temp;`
489	547	markom
490			`if (config.sim.mprofile)`
491			`mprofile (memaddr, MPROF_16 \| MPROF_READ);`
492
493	538	markom	`if (memaddr & 1) {`
494			`except_handle (EXCEPT_ALIGN, memaddr);`
495			`return 0;`
496			`}`
497	574	markom
498	631	simons	`if (config.debug.enabled)`
499			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
500

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