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/* abstract.c -- Abstract entities
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Abstract memory and routines that go with this. I need to
add all sorts of other abstract entities. Currently we have
only memory. */
 
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
 
#include "arch.h"
#include "parse.h"
#include "abstract.h"
#include "sim-config.h"
#include "labels.h"
#include "except.h"
#include "debug_unit.h"
#include "opcode/or32.h"
#include "spr_defs.h"
#include "execute.h"
#include "sprs.h"
#include "support/profile.h"
#include "dmmu.h"
#include "dcache_model.h"
#include "icache_model.h"
#include "debug.h"
#include "stats.h"
 
extern char *disassembled;
 
/* Pointer to memory area descriptions that are assigned to individual
   peripheral devices. */
struct dev_memarea *dev_list;
 
/* Temporary variable to increase speed.  */
struct dev_memarea *cur_area;
 
/* Pointer to memory controller device descriptor.  */
struct dev_memarea *mc_area = (struct dev_memarea *)0;
 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
int data_ci, insn_ci;
 
/* Virtual address of current access. */
oraddr_t cur_vadd;
 
/* Calculates bit mask to fit the data */
unsigned int bit_mask (uint32_t data) {
  int i = 0;
  data--;
  while (data >> i)
    data |= 1 << i++;
  return data;
}
 
/* Register read and write function for a memory area.
   addr is inside the area, if addr & addr_mask == addr_compare
   (used also by peripheral devices like 16450 UART etc.) */
void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,
                         uint32_t size, unsigned granularity, unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  struct dev_memarea **pptmp;
  unsigned int size_mask = bit_mask (size);
  int found_error = 0;
  addr_compare &= addr_mask;
 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",
        addr_mask, addr_compare, addr_compare | bit_mask (size), size,
        granularity);
  /* Go to the end of the list. */
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
      if (!found_error) {
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                         ", size %08"PRIx32", gran %iB\n",
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size,
                 granularity);
      }
      found_error = 1;
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                       ", size %08"PRIx32", gran %iB\n",
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
               (*pptmp)->addr_compare | (*pptmp)->size_mask,
               (*pptmp)->size, (*pptmp)->granularity);
    }
 
  if (found_error)
    exit (-1);
 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
 
  if (mc_dev)
    mc_area = *pptmp;
 
  (*pptmp)->addr_mask = addr_mask;
  (*pptmp)->addr_compare = addr_compare;
  (*pptmp)->size = size;
  (*pptmp)->size_mask = size_mask;
  (*pptmp)->granularity = granularity;
  (*pptmp)->readfunc = readfunc;
  (*pptmp)->writefunc = writefunc;
  (*pptmp)->log = 0;
  (*pptmp)->delayr = 2;
  (*pptmp)->delayw = 2;
  (*pptmp)->priv_dat = dat;
  (*pptmp)->chip_select = -1;
  (*pptmp)->next = NULL;
}
 
/* Register read and write function for a memory area.
   Memory areas should be aligned. Memory area is rounded up to
   fit the nearest 2^n aligment.
   (used also by peripheral devices like 16450 UART etc.)
   If mc_dev is 1, this means that this device will be checked first for match
   and will be accessed in case of overlaping memory spaces.
   Only one device can have this set to 1 (used for memory controller) */
void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,
                         unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  unsigned int size_mask = bit_mask (size);
  unsigned int addr_mask = ~size_mask;
  register_memoryarea_mask (addr_mask, addr & addr_mask,
                      size_mask + 1, granularity, mc_dev,
                      readfunc, writefunc, dat);
}
 
 
/* Check if access is to registered area of memory. */
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
{
  struct dev_memarea *ptmp;
 
  /* Check memory controller space first */
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
    return cur_area = mc_area;
 
  /* Check cached value */
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
    return cur_area;
 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
    if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
      return cur_area = ptmp;
  return cur_area = NULL;
}
 
/* Finds the memory area for the address and adjust the read and write delays for it. */
void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)
{
  if (verify_memoryarea(memaddr)) {
    cur_area->delayr = delayr;
    cur_area->delayw = delayw;
  }
}
 
/* for cpu accesses
 *
 * STATISTICS: check cpu/common/parse.c
 */
inline uint32_t evalsim_mem32(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint32_t evalsim_mem32_void(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 0));
}
 
uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      break;
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
    if (cpu_access)
      runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);
  }
  return temp;
}
 
/* for cpu accesses */
inline uint16_t evalsim_mem16(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint16_t evalsim_mem16_void(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 0));
}
 
uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr * 2;
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);
      if (memaddr & 2)
        temp &= 0xffff;
      else
        temp >>= 16;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline uint8_t evalsim_mem8(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint8_t evalsim_mem8_void(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 0));
}
 
uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 2:
      temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);
      if (memaddr & 1)
        temp &= 0xff;
      else
        temp >>= 8;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);
      temp >>= 8 * (3 - (memaddr & 3));
      temp &= 0xff;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * this function is only used in dumpmemory() below, so it's
 * safe to asume it's for simulator purposes access only,
 * hence the use of eval_mem32_void()
 *
 * STATISTICS OK.
 */
static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  cur_vadd = memaddr;
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
  temp = evalsim_mem32_void(memaddr);
  if (!cur_area) {
    PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
    temp = 0;
  } else if (cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_READ);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK
 */
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR
             ") in eval_direct32()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
//  memaddr = simulate_ic_mmu_fetch(memaddr);
 
  cur_vadd = memaddr;
 
  memaddr = immu_translate(memaddr);
 
  if (except_pending)
    return 0;
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
 
  if (config.ic.enabled)
    temp = ic_simulate_fetch(memaddr);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);
  return temp;
}
 
/* Returns 16-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
{
  uint16_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_READ);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = (uint16_t)dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR
             ") in eval_direct16()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 8-bit values from mem array.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
{
  uint8_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = (uint8_t)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
                     int through_dc)
{
  uint8_t temp;
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR
             ") in eval_direct8()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline void setsim_mem32(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem32_void(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 0));
}
 
void setsim_mem32_atomic(oraddr_t memaddr, uint32_t value, int cpu_access)
{
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 1:
      cur_area->writefunc(memaddr    , (value >> 24) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, (value >>  8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 3, (value      ) & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 4;
      break;
    case 2:
      cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem16(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem16_void(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 0));
}
 
void setsim_mem16_atomic(oraddr_t memaddr, uint16_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, (value >> 8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, value & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    case 2:
      cur_area->writefunc(memaddr, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 4:
      temp = evalsim_mem32_void(memaddr & ~ADDR_C(3));
      temp &= 0xffff << ((memaddr & 2) ? 16 : 0);
      temp |= (unsigned long)(value & 0xffff) << ((memaddr & 2) ? 0 : 16);
      setsim_mem32_atomic(memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem8(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem8_void(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 0));
}
 
void setsim_mem8_atomic(oraddr_t memaddr, uint8_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch (cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 2:
      temp = evalsim_mem16_void (memaddr & ~ADDR_C(1));
      temp &= 0xff << ((memaddr & 1) ? 8 : 0);
      temp |= (unsigned short)(value & 0xff) << ((memaddr & 1) ? 0 : 8);
      setsim_mem16_atomic (memaddr & ~ADDR_C(1), temp, cpu_access);
      break;
    case 4:
      temp = evalsim_mem32_void (memaddr & ~ADDR_C(3));
      temp &= ~(0xff << (8 * (3 - (memaddr & 3))));
      temp |= (unsigned long)(value & 0xff) << (8 * (3 - (memaddr & 3)));
      setsim_mem32_atomic (memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* Set mem, 32-bit. Big endian version.
 *
 * STATISTICS OK. (the only suspicious usage is in toplevel.c,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 */
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 1, through_dc);
  }
 
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
             memaddr, value);
}
 
 
/* Set mem, 16-bit. Big endian version. */
 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, (unsigned long)value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
             memaddr, value);
}
 
/* Set mem, 8-bit. */
 
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending) return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
                 int through_mmu, int through_dc)
{
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
             memaddr, value);
}
 
 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
{
  oraddr_t i, j;
  struct label_entry *tmp;
  int ilen = disasm ? 4 : 16;
 
  for(i = from; i < to; i += ilen) {
    PRINTF("%"PRIxADDR": ", i);
    for (j = 0; j < ilen;) {
      if (!disasm) {
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
          PRINTF("%02"PRIx8" ", evalsim_mem8(i + j));
        } else PRINTF("XX ");
        j++;
      } else {
        int breakpoint;
        uint32_t _insn = read_mem(i, &breakpoint);
        int index = insn_decode (_insn);
        int len = insn_len (index);
 
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
 
          PRINTF(": %08"PRIx32" ", _insn);
          if (index >= 0) {
            disassemble_insn (_insn);
            PRINTF(" %s", disassembled);
          } else
            PRINTF("<invalid>");
        } else PRINTF("XXXXXXXX");
        j += len;
      }
    }
    if (nl)
      PRINTF ("\n");
  }
}
 
uint32_t simmem_read_word(oraddr_t addr, void *priv_dat) {
  return *(uint32_t *)(priv_dat + (addr & cur_area->size_mask));
}
 
void simmem_write_word(oraddr_t addr, uint32_t value, void *priv_dat) {
  *(uint32_t *)(priv_dat + (addr & cur_area->size_mask)) = value;
}
 
uint32_t simmem_read_zero(oraddr_t addr, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory read from non-read memory area 0x%"
                     PRIxADDR".\n", addr);
  return 0;
}
 
void simmem_write_null(oraddr_t addr, uint32_t value, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory write to 0x%"PRIxADDR", non-write memory area (value 0x%08"PRIx32").\n", addr, value);
}
 
/* Initialize memory table from a config struct */
 
void init_memory_table ()
{
  /* If nothing was defined, use default memory block */
  if (config.memory.nmemories) {
    int i;
    for (i = 0; i < config.memory.nmemories; i++) {
      oraddr_t start = config.memory.table[i].baseaddr;
      uint32_t length = config.memory.table[i].size;
      char *type = config.memory.table[i].name;
      int rd = config.memory.table[i].delayr;
      int wd = config.memory.table[i].delayw;
      int ce = config.memory.table[i].ce;
      void *mem = malloc (length);
 
      if (config.sim.verbose)
        debug (1, "%"PRIxADDR" %08"PRIx32" (%"PRIi32" KB): %s (activated by CE%i; read delay = %icyc, write delay = %icyc)\n",
          start, length, length >> 10, type, ce, rd, wd);
 
      if (!mem) {
        fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
        exit (-1);
      }
 
      register_memoryarea(start, length, 4, 0, &simmem_read_word,
                          &simmem_write_word, mem);
      cur_area->chip_select = ce;
      cur_area->valid = 1;
      cur_area->delayw = wd;
      cur_area->delayr = rd;
      if (config.memory.table[i].log[0] != '\0') {
        if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
          fprintf (stderr, "WARNING: Cannot open '%s'.\n",
                   config.memory.table[i].log);
      } else
        cur_area->log = NULL;
    }
    PRINTF ("\n");
  } else {
    void *mem = malloc (DEFAULT_MEMORY_LEN);
    if (config.sim.verbose)
      fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
 
    if (!mem) {
      fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
      exit (-1);
    }
 
    register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, 0,
                        &simmem_read_word, &simmem_write_word, mem);
    cur_area->chip_select = 0;
    cur_area->valid = 1;
    cur_area->delayw = 1;
    cur_area->delayr = 1;
    cur_area->log = NULL;
  }
}
 
/* Changes read/write memory in read/write only */
 
void lock_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->delayr < 0 && ptmp->readfunc == &simmem_read_word)
      ptmp->readfunc = &simmem_read_zero;
    if (ptmp->delayw < 0 && ptmp->writefunc == &simmem_write_word)
      ptmp->writefunc = &simmem_write_null;
 
    /* If this mem area is not for memory chip under MC control
       then this area is valid all the time */
    if (ptmp->readfunc != &simmem_read_word) {
      ptmp->valid = 1;
      ptmp->chip_select = -1;
    }
  }
}
 
/* Closes files, etc. */
 
void done_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->log)
      fclose (ptmp->log);
  }
}
 
/* Displays current memory configuration */
 
void memory_table_status ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32
            ", gran %iB\n",
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
      ptmp->size, ptmp->granularity);
    PRINTF ("\t");
    if (ptmp->delayr >= 0)
      PRINTF ("read delay = %i cycles, ", ptmp->delayr);
    else
      PRINTF ("reads not possible, ");
 
    if (ptmp->delayw >= 0)
      PRINTF ("write delay = %i cycles", ptmp->delayw);
    else
      PRINTF ("writes not possible");
 
    if (ptmp->log)
      PRINTF (", (logged)\n");
    else
      PRINTF ("\n");
  }
}
 
/* Outputs time in pretty form to dest string */
 
char *generate_time_pretty (char *dest, long time_ps)
{
  int exp3 = 0;
  if (time_ps) {
    while ((time_ps % 1000) == 0) {
      time_ps /= 1000;
      exp3++;
    }
  }
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
  return dest;
}

Line No.	Rev	Author	Line
1	2	cvs	`/* abstract.c -- Abstract entities`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20	66	lampret	`/* Abstract memory and routines that go with this. I need to`
21	2	cvs	`add all sorts of other abstract entities. Currently we have`
22			`only memory. */`
23
24	221	markom	`#include <stdlib.h>`
25	2	cvs	`#include <stdio.h>`
26			`#include <ctype.h>`
27			`#include <string.h>`
28
29	6	lampret	`#include "config.h"`
30	1350	nogj
31			`#ifdef HAVE_INTTYPES_H`
32			`#include <inttypes.h>`
33			`#endif`
34
35			`#include "port.h"`
36	6	lampret
37	1350	nogj	`#include "arch.h"`
38	2	cvs	`#include "parse.h"`
39			`#include "abstract.h"`
40	1358	nogj	`#include "sim-config.h"`
41	261	markom	`#include "labels.h"`
42	32	lampret	`#include "except.h"`
43	123	markom	`#include "debug_unit.h"`
44	134	markom	`#include "opcode/or32.h"`
45	1432	nogj	`#include "spr_defs.h"`
46			`#include "execute.h"`
47			`#include "sprs.h"`
48	547	markom	`#include "support/profile.h"`
49	1308	phoenix	`#include "dmmu.h"`
50			`#include "dcache_model.h"`
51			`#include "icache_model.h"`
52			`#include "debug.h"`
53	1344	nogj	`#include "stats.h"`
54	2	cvs
55	138	markom	`extern char *disassembled;`
56	2	cvs
57	30	lampret	`/* Pointer to memory area descriptions that are assigned to individual`
58			`peripheral devices. */`
59			`struct dev_memarea *dev_list;`
60
61	221	markom	`/* Temporary variable to increase speed. */`
62			`struct dev_memarea *cur_area;`
63
64	970	simons	`/* Pointer to memory controller device descriptor. */`
65			`struct dev_memarea mc_area = (struct dev_memarea )0;`
66
67	638	simons	`/* These are set by mmu if cache inhibit bit is set for current acces. */`
68			`int data_ci, insn_ci;`
69
70	525	simons	`/* Virtual address of current access. */`
71	1350	nogj	`oraddr_t cur_vadd;`
72	525	simons
73	261	markom	`/* Calculates bit mask to fit the data */`
74	1350	nogj	`unsigned int bit_mask (uint32_t data) {`
75	261	markom	`int i = 0;`
76			`data--;`
77	382	markom	`while (data >> i)`
78	261	markom	`data \|= 1 << i++;`
79			`return data;`
80			`}`
81
82			`/* Register read and write function for a memory area.`
83			`addr is inside the area, if addr & addr_mask == addr_compare`
84			`(used also by peripheral devices like 16450 UART etc.) */`
85	1350	nogj	`void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,`
86			`uint32_t size, unsigned granularity, unsigned mc_dev,`
87	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
88			`void (writefunc)(oraddr_t, uint32_t, void *),`
89			`void *dat)`
90	30	lampret	`{`
91	239	markom	`struct dev_memarea **pptmp;`
92	1350	nogj	`unsigned int size_mask = bit_mask (size);`
93	261	markom	`int found_error = 0;`
94			`addr_compare &= addr_mask;`
95	221	markom
96	1350	nogj	`debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",`
97			`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
98			`granularity);`
99	239	markom	`/* Go to the end of the list. */`
100	261	markom	`for(pptmp = &dev_list; pptmp; pptmp = &(pptmp)->next)`
101			`if ((addr_compare >= (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)`
102			`\|\| (addr_compare + size > (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)) {`
103	262	markom	`if (!found_error) {`
104	261	markom	`fprintf (stderr, "ERROR: Overlapping memory area(s):\n");`
105	1350	nogj	`fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
106			`", size %08"PRIx32", gran %iB\n",`
107	1308	phoenix	`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
108			`granularity);`
109	262	markom	`}`
110	261	markom	`found_error = 1;`
111	1350	nogj	`fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
112			`", size %08"PRIx32", gran %iB\n",`
113	1308	phoenix	`(pptmp)->addr_mask, (pptmp)->addr_compare,`
114			`(pptmp)->addr_compare \| (pptmp)->size_mask,`
115			`(pptmp)->size, (pptmp)->granularity);`
116	261	markom	`}`
117
118			`if (found_error)`
119			`exit (-1);`
120	537	markom
121	239	markom	`cur_area = pptmp = (struct dev_memarea )malloc(sizeof(struct dev_memarea));`
122	970	simons
123			`if (mc_dev)`
124			`mc_area = *pptmp;`
125
126	261	markom	`(*pptmp)->addr_mask = addr_mask;`
127			`(*pptmp)->addr_compare = addr_compare;`
128	239	markom	`(*pptmp)->size = size;`
129	261	markom	`(*pptmp)->size_mask = size_mask;`
130	239	markom	`(*pptmp)->granularity = granularity;`
131			`(*pptmp)->readfunc = readfunc;`
132			`(*pptmp)->writefunc = writefunc;`
133	479	markom	`(*pptmp)->log = 0;`
134	882	simons	`(*pptmp)->delayr = 2;`
135			`(*pptmp)->delayw = 2;`
136	1359	nogj	`(*pptmp)->priv_dat = dat;`
137	1362	nogj	`(*pptmp)->chip_select = -1;`
138	239	markom	`(*pptmp)->next = NULL;`
139	261	markom	`}`
140	221	markom
141	261	markom	`/* Register read and write function for a memory area.`
142			`Memory areas should be aligned. Memory area is rounded up to`
143			`fit the nearest 2^n aligment.`
144	970	simons	`(used also by peripheral devices like 16450 UART etc.)`
145			`If mc_dev is 1, this means that this device will be checked first for match`
146	1359	nogj	`and will be accessed in case of overlaping memory spaces.`
147	970	simons	`Only one device can have this set to 1 (used for memory controller) */`
148	1350	nogj	`void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,`
149			`unsigned mc_dev,`
150	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
151			`void (writefunc)(oraddr_t, uint32_t, void *),`
152			`void *dat)`
153	261	markom	`{`
154	1350	nogj	`unsigned int size_mask = bit_mask (size);`
155			`unsigned int addr_mask = ~size_mask;`
156	261	markom	`register_memoryarea_mask (addr_mask, addr & addr_mask,`
157	970	simons	`size_mask + 1, granularity, mc_dev,`
158	1359	nogj	`readfunc, writefunc, dat);`
159	30	lampret	`}`
160
161	261	markom
162	30	lampret	`/* Check if access is to registered area of memory. */`
163	1350	nogj	`inline struct dev_memarea *verify_memoryarea(oraddr_t addr)`
164	30	lampret	`{`
165	239	markom	`struct dev_memarea *ptmp;`
166	221	markom
167	970	simons	`/* Check memory controller space first */`
168			`if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))`
169			`return cur_area = mc_area;`
170
171			`/* Check cached value */`
172	560	markom	`if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))`
173			`return cur_area;`
174
175			`/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */`
176	1375	nogj	`/* Check list of registered devices. */`
177			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
178			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)`
179			`return cur_area = ptmp;`
180	239	markom	`return cur_area = NULL;`
181	30	lampret	`}`
182
183	882	simons	`/* Finds the memory area for the address and adjust the read and write delays for it. */`
184	1350	nogj	`void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)`
185	882	simons	`{`
186			`if (verify_memoryarea(memaddr)) {`
187			`cur_area->delayr = delayr;`
188			`cur_area->delayw = delayw;`
189			`}`
190			`}`
191
192	1319	phoenix	`/* for cpu accesses`
193			`*`
194			`* STATISTICS: check cpu/common/parse.c`
195			`*/`
196	1350	nogj	`inline uint32_t evalsim_mem32(oraddr_t memaddr)`
197	560	markom	`{`
198	1319	phoenix	`return(evalsim_mem32_atomic(memaddr, 1));`
199			`}`
200	560	markom
201	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
202	1350	nogj	`inline uint32_t evalsim_mem32_void(oraddr_t memaddr)`
203	1319	phoenix	`{`
204			`return(evalsim_mem32_atomic(memaddr, 0));`
205			`}`
206
207	1350	nogj	`uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)`
208	1319	phoenix	`{`
209	1350	nogj	`uint32_t temp = 0;`
210	1319	phoenix
211	560	markom	`if (verify_memoryarea(memaddr)) {`
212			`switch(cur_area->granularity) {`
213			`case 4:`
214	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
215	560	markom	`break;`
216			`case 1:`
217	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;`
218			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;`
219			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;`
220			`temp \|= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);`
221	560	markom	`break;`
222			`case 2:`
223	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;`
224			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);`
225	560	markom	`break;`
226	1319	phoenix	`default:`
227			`/* if you add new memory granularity be sure to check the formula`
228			`* below for the read delay and fix it if necessery`
229			`*/`
230			`PRINTF("unknown/unhandled memory granularuty\n");`
231			`exit(-1);`
232	560	markom	`}`
233	1319	phoenix	`if (cpu_access)`
234			`runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);`
235	560	markom	`}`
236			`return temp;`
237			`}`
238
239	1319	phoenix	`/* for cpu accesses */`
240	1350	nogj	`inline uint16_t evalsim_mem16(oraddr_t memaddr)`
241	560	markom	`{`
242	1319	phoenix	`return(evalsim_mem16_atomic(memaddr, 1));`
243			`}`
244	560	markom
245	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
246	1350	nogj	`inline uint16_t evalsim_mem16_void(oraddr_t memaddr)`
247	1319	phoenix	`{`
248			`return(evalsim_mem16_atomic(memaddr, 0));`
249			`}`
250
251	1350	nogj	`uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)`
252	1319	phoenix	`{`
253	1350	nogj	`uint32_t temp = 0;`
254	1319	phoenix
255	560	markom	`if (verify_memoryarea(memaddr)) {`
256			`switch(cur_area->granularity) {`
257			`case 1:`
258	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;`
259			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);`
260	1319	phoenix	`if (cpu_access)`
261			`runtime.sim.mem_cycles += cur_area->delayr * 2;`
262	560	markom	`break;`
263			`case 2:`
264	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
265	1319	phoenix	`if (cpu_access)`
266			`runtime.sim.mem_cycles += cur_area->delayr;`
267	560	markom	`break;`
268			`case 4:`
269	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);`
270	560	markom	`if (memaddr & 2)`
271			`temp &= 0xffff;`
272			`else`
273			`temp >>= 16;`
274			`break;`
275	1319	phoenix	`default:`
276			`/* if you add new memory granularity be sure to check the formula`
277			`* below for the read delay and fix it if necessery`
278			`*/`
279			`PRINTF("unknown/unhandled memory granularuty\n");`
280			`exit(-1);`
281	560	markom	`}`
282			`}`
283			`return temp;`
284			`}`
285
286	1319	phoenix	`/* for cpu accesses */`
287	1350	nogj	`inline uint8_t evalsim_mem8(oraddr_t memaddr)`
288	560	markom	`{`
289	1319	phoenix	`return(evalsim_mem8_atomic(memaddr, 1));`
290			`}`
291	560	markom
292	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
293	1350	nogj	`inline uint8_t evalsim_mem8_void(oraddr_t memaddr)`
294	1319	phoenix	`{`
295			`return(evalsim_mem8_atomic(memaddr, 0));`
296			`}`
297
298	1350	nogj	`uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)`
299	1319	phoenix	`{`
300	1350	nogj	`uint32_t temp = 0;`
301	1319	phoenix
302	560	markom	`if (verify_memoryarea(memaddr)) {`
303			`switch(cur_area->granularity) {`
304			`case 1:`
305	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
306	1319	phoenix	`if (cpu_access)`
307			`runtime.sim.mem_cycles += cur_area->delayr;`
308	560	markom	`break;`
309			`case 2:`
310	1350	nogj	`temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);`
311	560	markom	`if (memaddr & 1)`
312			`temp &= 0xff;`
313			`else`
314			`temp >>= 8;`
315			`break;`
316			`case 4:`
317	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);`
318	560	markom	`temp >>= 8 * (3 - (memaddr & 3));`
319			`temp &= 0xff;`
320			`break;`
321	1319	phoenix	`default:`
322			`/* if you add new memory granularity be sure to check the formula`
323			`* below for the read delay and fix it if necessery`
324			`*/`
325			`PRINTF("unknown/unhandled memory granularuty\n");`
326			`exit(-1);`
327	560	markom	`}`
328			`}`
329			`return temp;`
330			`}`
331
332	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
333			`*`
334	1350	nogj	`* this function is only used in dumpmemory() below, so it's`
335	1319	phoenix	`* safe to asume it's for simulator purposes access only,`
336			`* hence the use of eval_mem32_void()`
337			`*`
338			`* STATISTICS OK.`
339			`*/`
340	1350	nogj	`static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)`
341	349	simons	`{`
342	1350	nogj	`uint32_t temp;`
343	349	simons
344	525	simons	`cur_vadd = memaddr;`
345	550	markom	`if (config.debug.enabled)`
346	349	simons	`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
347	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
348	611	simons	`if (!cur_area) {`
349	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
350			`memaddr);`
351	611	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
352			`temp = 0;`
353	1386	nogj	`} else if (cur_area->log)`
354			`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);`
355	611	simons
356	550	markom	`if (config.debug.enabled)`
357	349	simons	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
358			`return temp;`
359	537	markom	`}`
360	349	simons
361	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
362			`*`
363			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
364			`*/`
365	1350	nogj	`uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)`
366	2	cvs	`{`
367	1350	nogj	`uint32_t temp;`
368	123	markom
369	547	markom	`if (config.sim.mprofile)`
370			`mprofile (memaddr, MPROF_32 \| MPROF_READ);`
371
372	538	markom	`if (memaddr & 3) {`
373			`except_handle (EXCEPT_ALIGN, memaddr);`
374			`return 0;`
375			`}`
376	557	markom
377	631	simons	`if (config.debug.enabled)`
378			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
379
380	574	markom	`cur_vadd = memaddr;`
381	631	simons
382			`memaddr = dmmu_translate(memaddr, 0);`
383	1386	nogj	`if (except_pending)`
384	574	markom	`return 0;`
385
386	992	simons	`if (config.dc.enabled)`
387			`temp = dc_simulate_read(memaddr, 4);`
388			`else {`
389			`temp = evalsim_mem32(memaddr);`
390			`if (!cur_area) {`
391	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
392			`memaddr);`
393	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
394			`temp = 0;`
395			`}`
396	611	simons	`}`
397
398	550	markom	`if (config.debug.enabled)`
399	270	markom	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
400	239	markom	`return temp;`
401	66	lampret	`}`
402
403	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do`
404			`*`
405			`* STATISTICS OK`
406			`*/`
407	1350	nogj	`uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,`
408			`int through_dc)`
409	1240	phoenix	`{`
410	1350	nogj	`uint32_t temp;`
411	1240	phoenix
412			`if (memaddr & 3) {`
413			`PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);`
414			`return 0;`
415			`}`
416
417			`cur_vadd = memaddr;`
418
419			`if (through_mmu)`
420			`memaddr = peek_into_dtlb(memaddr, 0, through_dc);`
421
422			`if (through_dc)`
423			`temp = dc_simulate_read(memaddr, 4);`
424			`else {`
425	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
426	1240	phoenix	`if (!cur_area) {`
427	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR`
428			`") in eval_direct32()\n", memaddr);`
429	1240	phoenix	`except_handle(EXCEPT_BUSERR, cur_vadd);`
430			`temp = 0;`
431			`}`
432			`}`
433
434			`return temp;`
435			`}`
436
437
438	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
439			`*`
440			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
441			`*/`
442	1386	nogj	`uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)`
443	349	simons	`{`
444	1350	nogj	`uint32_t temp;`
445	349	simons
446	547	markom	`if (config.sim.mprofile)`
447			`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`
448	532	markom	`// memaddr = simulate_ic_mmu_fetch(memaddr);`
449	1244	hpanther
450	1386	nogj	`cur_vadd = memaddr;`
451	1244	hpanther
452	1386	nogj	`memaddr = immu_translate(memaddr);`
453
454			`if (except_pending)`
455			`return 0;`
456
457			`if (config.debug.enabled)`
458			`*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);`
459
460	631	simons	`if (config.ic.enabled)`
461			`temp = ic_simulate_fetch(memaddr);`
462	992	simons	`else {`
463	631	simons	`temp = evalsim_mem32(memaddr);`
464	992	simons	`if (!cur_area) {`
465	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
466			`memaddr);`
467	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
468			`temp = 0;`
469			`}`
470	611	simons	`}`
471
472	1386	nogj	`if (config.debug.enabled)`
473			`*breakpoint += CheckDebugUnit(DebugLoadData,temp);`
474	349	simons	`return temp;`
475			`}`
476
477	1319	phoenix	`/* Returns 16-bit values from mem array. Big endian version.`
478			`*`
479			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
480			`*/`
481	1350	nogj	`uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)`
482	2	cvs	`{`
483	1350	nogj	`uint16_t temp;`
484	547	markom
485			`if (config.sim.mprofile)`
486			`mprofile (memaddr, MPROF_16 \| MPROF_READ);`
487
488	538	markom	`if (memaddr & 1) {`
489			`except_handle (EXCEPT_ALIGN, memaddr);`
490			`return 0;`
491			`}`
492	574	markom
493	631	simons	`if (config.debug.enabled)`
494			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
495
496	574	markom	`cur_vadd = memaddr;`
497	631	simons
498			`memaddr = dmmu_translate(memaddr, 0);`
499	1386	nogj	`if (except_pending)`
500	574	markom	`return 0;`

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