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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1556

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1 2 cvs 
/* abstract.c -- Abstract entities
2 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3 1486 nogj 
   Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
4 2 cvs 
 
5 
This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 
 
21 66 lampret 
/* Abstract memory and routines that go with this. I need to
22 2 cvs 
add all sorts of other abstract entities. Currently we have
23 
only memory. */
24 
 
25 221 markom 
#include <stdlib.h>
26 2 cvs 
#include <stdio.h>
27 
#include <ctype.h>
28 
#include <string.h>
29 
 
30 6 lampret 
#include "config.h"
31 1350 nogj 
 
32 
#ifdef HAVE_INTTYPES_H
33 
#include <inttypes.h>
34 
#endif
35 
 
36 
#include "port.h"
37 6 lampret 
 
38 1350 nogj 
#include "arch.h"
39 2 cvs 
#include "parse.h"
40 
#include "abstract.h"
41 1358 nogj 
#include "sim-config.h"
42 261 markom 
#include "labels.h"
43 32 lampret 
#include "except.h"
44 123 markom 
#include "debug_unit.h"
45 134 markom 
#include "opcode/or32.h"
46 1432 nogj 
#include "spr_defs.h"
47 
#include "execute.h"
48 
#include "sprs.h"
49 547 markom 
#include "support/profile.h"
50 1308 phoenix 
#include "dmmu.h"
51 1446 nogj 
#include "immu.h"
52 1308 phoenix 
#include "dcache_model.h"
53 
#include "icache_model.h"
54 
#include "debug.h"
55 1344 nogj 
#include "stats.h"
56 2 cvs 
 
57 1452 nogj 
#if DYNAMIC_EXECUTION
58 
#include "dyn_rec.h"
59 
#endif
60 
 
61 138 markom 
extern char *disassembled;
62 2 cvs 
 
63 30 lampret 
/* Pointer to memory area descriptions that are assigned to individual
64 
   peripheral devices. */
65 
struct dev_memarea *dev_list;
66 
 
67 221 markom 
/* Temporary variable to increase speed.  */
68 
struct dev_memarea *cur_area;
69 
 
70 970 simons 
/* Pointer to memory controller device descriptor.  */
71 1486 nogj 
struct dev_memarea *mc_area = NULL;
72 970 simons 
 
73 638 simons 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
74 
int data_ci, insn_ci;
75 
 
76 525 simons 
/* Virtual address of current access. */
77 1486 nogj 
static oraddr_t cur_vadd;
78 525 simons 
 
79 1486 nogj 
/* Read functions */
80 
uint32_t eval_mem_32_inv(oraddr_t, void *);
81 
uint16_t eval_mem_16_inv(oraddr_t, void *);
82 
uint8_t eval_mem_8_inv(oraddr_t, void *);
83 
uint32_t eval_mem_32_inv_direct(oraddr_t, void *);
84 
uint16_t eval_mem_16_inv_direct(oraddr_t, void *);
85 
uint8_t eval_mem_8_inv_direct(oraddr_t, void *);
86 
 
87 
/* Write functions */
88 
void set_mem_32_inv(oraddr_t, uint32_t, void *);
89 
void set_mem_16_inv(oraddr_t, uint16_t, void *);
90 
void set_mem_8_inv(oraddr_t, uint8_t, void *);
91 
void set_mem_32_inv_direct(oraddr_t, uint32_t, void *);
92 
void set_mem_16_inv_direct(oraddr_t, uint16_t, void *);
93 
void set_mem_8_inv_direct(oraddr_t, uint8_t, void *);
94 
 
95 261 markom 
/* Calculates bit mask to fit the data */
96 1486 nogj 
static unsigned int bit_mask (uint32_t data) {
97 261 markom 
  int i = 0;
98 
  data--;
99 382 markom 
  while (data >> i)
100 261 markom 
    data |= 1 << i++;
101 
  return data;
102 
}
103 
 
104 
/* Register read and write function for a memory area.
105 
   addr is inside the area, if addr & addr_mask == addr_compare
106 
   (used also by peripheral devices like 16450 UART etc.) */
107 1486 nogj 
struct dev_memarea *register_memoryarea_mask(oraddr_t addr_mask,
108 
                                             oraddr_t addr_compare,
109 
                                             uint32_t size, unsigned mc_dev)
110 30 lampret 
{
111 239 markom 
  struct dev_memarea **pptmp;
112 1350 nogj 
  unsigned int size_mask = bit_mask (size);
113 261 markom 
  int found_error = 0;
114 
  addr_compare &= addr_mask;
115 221 markom 
 
116 1486 nogj 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32"\n",
117 
        addr_mask, addr_compare, addr_compare | bit_mask (size), size);
118 239 markom 
  /* Go to the end of the list. */
119 261 markom 
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
120 
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
121 
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
122 262 markom 
      if (!found_error) {
123 261 markom 
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
124 1350 nogj 
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
125 1486 nogj 
                         ", size %08"PRIx32"\n",
126 
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size);
127 262 markom 
      }
128 261 markom 
      found_error = 1;
129 1350 nogj 
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
130 1486 nogj 
                       ", size %08"PRIx32"\n",
131 1308 phoenix 
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
132 1486 nogj 
               (*pptmp)->addr_compare | (*pptmp)->size_mask, (*pptmp)->size);
133 261 markom 
    }
134 
 
135 
  if (found_error)
136 
    exit (-1);
137 537 markom 
 
138 239 markom 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
139 970 simons 
 
140 
  if (mc_dev)
141 
    mc_area = *pptmp;
142 
 
143 261 markom 
  (*pptmp)->addr_mask = addr_mask;
144 
  (*pptmp)->addr_compare = addr_compare;
145 239 markom 
  (*pptmp)->size = size;
146 261 markom 
  (*pptmp)->size_mask = size_mask;
147 1486 nogj 
  (*pptmp)->log = NULL;
148 
  (*pptmp)->valid = 1;
149 239 markom 
  (*pptmp)->next = NULL;
150 1486 nogj 
 
151 
  return *pptmp;
152 261 markom 
}
153 221 markom 
 
154 261 markom 
/* Register read and write function for a memory area.
155 
   Memory areas should be aligned. Memory area is rounded up to
156 
   fit the nearest 2^n aligment.
157 970 simons 
   (used also by peripheral devices like 16450 UART etc.)
158 1486 nogj 
   If mc_dev is 1, this device will be checked first for a match
159 
   and will be accessed in case of overlaping memory areas.
160 970 simons 
   Only one device can have this set to 1 (used for memory controller) */
161 1486 nogj 
struct dev_memarea *reg_mem_area(oraddr_t addr, uint32_t size, unsigned mc_dev,
162 
                                 struct mem_ops *ops)
163 261 markom 
{
164 1350 nogj 
  unsigned int size_mask = bit_mask (size);
165 
  unsigned int addr_mask = ~size_mask;
166 1486 nogj 
  struct dev_memarea *mem;
167 
 
168 
  mem = register_memoryarea_mask(addr_mask, addr & addr_mask, size_mask + 1,
169 
                                 mc_dev);
170 
 
171 
  memcpy(&mem->ops, ops, sizeof(struct mem_ops));
172 
  memcpy(&mem->direct_ops, ops, sizeof(struct mem_ops));
173 
 
174 
  if(!ops->readfunc32) {
175 
    mem->ops.readfunc32 = eval_mem_32_inv;
176 
    mem->direct_ops.readfunc32 = eval_mem_32_inv_direct;
177 
    mem->direct_ops.read_dat32 = mem;
178 
  }
179 
  if(!ops->readfunc16) {
180 
    mem->ops.readfunc16 = eval_mem_16_inv;
181 
    mem->direct_ops.readfunc16 = eval_mem_16_inv_direct;
182 
    mem->direct_ops.read_dat16 = mem;
183 
  }
184 
  if(!ops->readfunc8) {
185 
    mem->ops.readfunc8 = eval_mem_8_inv;
186 
    mem->direct_ops.readfunc8 = eval_mem_8_inv_direct;
187 
    mem->direct_ops.read_dat8 = mem;
188 
  }
189 
 
190 
  if(!ops->writefunc32) {
191 
    mem->ops.writefunc32 = set_mem_32_inv;
192 
    mem->direct_ops.writefunc32 = set_mem_32_inv_direct;
193 
    mem->direct_ops.write_dat32 = mem;
194 
  }
195 
  if(!ops->writefunc16) {
196 
    mem->ops.writefunc16 = set_mem_16_inv;
197 
    mem->direct_ops.writefunc16 = set_mem_16_inv_direct;
198 
    mem->direct_ops.write_dat16 = mem;
199 
  }
200 
  if(!ops->writefunc8) {
201 
    mem->ops.writefunc8 = set_mem_8_inv;
202 
    mem->direct_ops.writefunc8 = set_mem_8_inv_direct;
203 
    mem->direct_ops.write_dat8 = mem;
204 
  }
205 
 
206 1556 nogj 
  if(!ops->writeprog8) {
207 
    mem->ops.writeprog8 = mem->ops.writefunc8;
208 
    mem->ops.writeprog8_dat = mem->ops.write_dat8;
209 1486 nogj 
  }
210 
 
211 1556 nogj 
  if(!ops->writeprog32) {
212 
    mem->ops.writeprog32 = mem->ops.writefunc32;
213 
    mem->ops.writeprog32_dat = mem->ops.write_dat32;
214 
  }
215 
 
216 1486 nogj 
  if(ops->log) {
217 
    if(!(mem->log = fopen(ops->log, "w")))
218 
      PRINTF("ERR: Unable to open %s to log memory acesses to\n", ops->log);
219 
  }
220 
 
221 
  return mem;
222 30 lampret 
}
223 
 
224 
/* Check if access is to registered area of memory. */
225 1350 nogj 
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
226 30 lampret 
{
227 239 markom 
  struct dev_memarea *ptmp;
228 221 markom 
 
229 970 simons 
  /* Check memory controller space first */
230 
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
231 
    return cur_area = mc_area;
232 
 
233 
  /* Check cached value */
234 560 markom 
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
235 
    return cur_area;
236 
 
237 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
238 1375 nogj 
  /* Check list of registered devices. */
239 
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
240 
    if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
241 
      return cur_area = ptmp;
242 239 markom 
  return cur_area = NULL;
243 30 lampret 
}
244 
 
245 1486 nogj 
/* Sets the valid bit (Used only by memory controllers) */
246 
void set_mem_valid(struct dev_memarea *mem, int valid)
247 882 simons 
{
248 1486 nogj 
  mem->valid = valid;
249 882 simons 
}
250 
 
251 1486 nogj 
/* Adjusts the read and write delays for the memory area pointed to by mem. */
252 
void adjust_rw_delay(struct dev_memarea *mem, int delayr, int delayw)
253 560 markom 
{
254 1486 nogj 
  mem->ops.delayr = delayr;
255 
  mem->ops.delayw = delayw;
256 1319 phoenix 
}
257 560 markom 
 
258 1486 nogj 
uint8_t eval_mem_8_inv(oraddr_t memaddr, void *dat)
259 1319 phoenix 
{
260 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
261 
  return 0;
262 1319 phoenix 
}
263 
 
264 1486 nogj 
uint16_t eval_mem_16_inv(oraddr_t memaddr, void *dat)
265 1319 phoenix 
{
266 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
267 
  return 0;
268 
}
269 1319 phoenix 
 
270 1486 nogj 
uint32_t eval_mem_32_inv(oraddr_t memaddr, void *dat)
271 
{
272 
  except_handle(EXCEPT_BUSERR, cur_vadd);
273 
  return 0;
274 560 markom 
}
275 
 
276 1486 nogj 
void set_mem_8_inv(oraddr_t memaddr, uint8_t val, void *dat)
277 560 markom 
{
278 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
279 1319 phoenix 
}
280 560 markom 
 
281 1486 nogj 
void set_mem_16_inv(oraddr_t memaddr, uint16_t val, void *dat)
282 1319 phoenix 
{
283 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
284 1319 phoenix 
}
285 
 
286 1486 nogj 
void set_mem_32_inv(oraddr_t memaddr, uint32_t val, void *dat)
287 1319 phoenix 
{
288 1486 nogj 
  except_handle(EXCEPT_BUSERR, cur_vadd);
289 
}
290 1319 phoenix 
 
291 1486 nogj 
uint8_t eval_mem_8_inv_direct(oraddr_t memaddr, void *dat)
292 
{
293 
  struct dev_memarea *mem = dat;
294 
 
295 
  PRINTF("ERROR: Invalid 8-bit direct read from memory %"PRIxADDR"\n",
296 
         mem->addr_compare | memaddr);
297 
  return 0;
298 560 markom 
}
299 
 
300 1486 nogj 
uint16_t eval_mem_16_inv_direct(oraddr_t memaddr, void *dat)
301 560 markom 
{
302 1486 nogj 
  struct dev_memarea *mem = dat;
303 
 
304 
  PRINTF("ERROR: Invalid 16-bit direct read from memory %"PRIxADDR"\n",
305 
         mem->addr_compare | memaddr);
306 
  return 0;
307 1319 phoenix 
}
308 560 markom 
 
309 1486 nogj 
uint32_t eval_mem_32_inv_direct(oraddr_t memaddr, void *dat)
310 1319 phoenix 
{
311 1486 nogj 
  struct dev_memarea *mem = dat;
312 
 
313 
  PRINTF("ERROR: Invalid 32-bit direct read from memory %"PRIxADDR"\n",
314 
         mem->addr_compare | memaddr);
315 
  return 0;
316 1319 phoenix 
}
317 
 
318 1486 nogj 
void set_mem_8_inv_direct(oraddr_t memaddr, uint8_t val, void *dat)
319 1319 phoenix 
{
320 1486 nogj 
  struct dev_memarea *mem = dat;
321 1319 phoenix 
 
322 1486 nogj 
  PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
323 
         mem->addr_compare | memaddr);
324 
}
325 
 
326 
void set_mem_16_inv_direct(oraddr_t memaddr, uint16_t val, void *dat)
327 
{
328 
  struct dev_memarea *mem = dat;
329 
 
330 
  PRINTF("ERROR: Invalid 16-bit direct write to memory %"PRIxADDR"\n",
331 
         mem->addr_compare | memaddr);
332 
}
333 
 
334 
void set_mem_32_inv_direct(oraddr_t memaddr, uint32_t val, void *dat)
335 
{
336 
  struct dev_memarea *mem = dat;
337 
 
338 
  PRINTF("ERROR: Invalid 32-bit direct write to memory %"PRIxADDR"\n",
339 
         mem->addr_compare | memaddr);
340 
}
341 
 
342 
/* For cpu accesses
343 
 *
344 
 * NOTE: This function _is_ only called from eval_mem32 below and
345 
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
346 
 */
347 
inline uint32_t evalsim_mem32(oraddr_t memaddr, oraddr_t vaddr)
348 
{
349 
  struct dev_memarea *mem;
350 
 
351 
  if((mem = verify_memoryarea(memaddr))) {
352 
    runtime.sim.mem_cycles += mem->ops.delayr;
353 
    return mem->ops.readfunc32(memaddr & mem->size_mask, mem->ops.read_dat32);
354 
  } else {
355 
    PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
356 
           memaddr);
357 
    except_handle(EXCEPT_BUSERR, vaddr);
358 560 markom 
  }
359 1486 nogj 
 
360 
  return 0;
361 560 markom 
}
362 
 
363 1486 nogj 
/* For cpu accesses
364 
 *
365 
 * NOTE: This function _is_ only called from eval_mem16 below and
366 
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
367 
 */
368 
inline uint16_t evalsim_mem16(oraddr_t memaddr, oraddr_t vaddr)
369 
{
370 
  struct dev_memarea *mem;
371 
 
372 
  if((mem = verify_memoryarea(memaddr))) {
373 
    runtime.sim.mem_cycles += mem->ops.delayr;
374 
    return mem->ops.readfunc16(memaddr & mem->size_mask, mem->ops.read_dat16);
375 
  } else {
376 
    PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
377 
           memaddr);
378 
    except_handle(EXCEPT_BUSERR, vaddr);
379 
  }
380 
 
381 
  return 0;
382 
}
383 
 
384 
/* For cpu accesses
385 
 *
386 
 * NOTE: This function _is_ only called from eval_mem8 below and
387 
 * {i,d}c_simulate_read.  _Don't_ call it from anywere else.
388 
 */
389 
inline uint8_t evalsim_mem8(oraddr_t memaddr, oraddr_t vaddr)
390 
{
391 
  struct dev_memarea *mem;
392 
 
393 
  if((mem = verify_memoryarea(memaddr))) {
394 
    runtime.sim.mem_cycles += mem->ops.delayr;
395 
    return mem->ops.readfunc8(memaddr & mem->size_mask, mem->ops.read_dat8);
396 
  } else {
397 
    PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
398 
           memaddr);
399 
    except_handle(EXCEPT_BUSERR, vaddr);
400 
  }
401 
 
402 
  return 0;
403 
}
404 
 
405 1319 phoenix 
/* Returns 32-bit values from mem array. Big endian version.
406 
 *
407 
 * STATISTICS OK (only used for cpu_access, that is architectural access)
408 
 */
409 1350 nogj 
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
410 2 cvs 
{
411 1350 nogj 
  uint32_t temp;
412 1486 nogj 
  oraddr_t phys_memaddr;
413 123 markom 
 
414 547 markom 
  if (config.sim.mprofile)
415 
    mprofile (memaddr, MPROF_32 | MPROF_READ);
416 
 
417 538 markom 
  if (memaddr & 3) {
418 
    except_handle (EXCEPT_ALIGN, memaddr);
419 
    return 0;
420 
  }
421 557 markom 
 
422 631 simons 
  if (config.debug.enabled)
423 
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
424 
 
425 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 0);
426 1386 nogj 
  if (except_pending)
427 574 markom 
    return 0;
428 
 
429 992 simons 
  if (config.dc.enabled)
430 1486 nogj 
    temp = dc_simulate_read(phys_memaddr, memaddr, 4);
431 
  else
432 
    temp = evalsim_mem32(phys_memaddr, memaddr);
433 611 simons 
 
434 550 markom 
  if (config.debug.enabled)
435 270 markom 
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
436 1486 nogj 
 
437 239 markom 
  return temp;
438 66 lampret 
}
439 
 
440 1319 phoenix 
/* for simulator accesses, the ones that cpu wouldn't do
441 
 *
442 
 * STATISTICS OK
443 
 */
444 1487 nogj 
uint32_t eval_direct32(oraddr_t memaddr, int through_mmu, int through_dc)
445 1240 phoenix 
{
446 1486 nogj 
  oraddr_t phys_memaddr;
447 
  struct dev_memarea *mem;
448 1240 phoenix 
 
449 
  if (memaddr & 3) {
450 
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
451 1486 nogj 
    return 0;
452 1240 phoenix 
  }
453 
 
454 1486 nogj 
  phys_memaddr = memaddr;
455 1240 phoenix 
 
456 
  if (through_mmu)
457 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
458 1240 phoenix 
 
459 
  if (through_dc)
460 1486 nogj 
    return dc_simulate_read(phys_memaddr, memaddr, 4);
461 1240 phoenix 
  else {
462 1486 nogj 
    if((mem = verify_memoryarea(phys_memaddr)))
463 
      return mem->direct_ops.readfunc32(phys_memaddr & mem->size_mask,
464 
                                        mem->direct_ops.read_dat32);
465 
    else
466 
      PRINTF("ERR: 32-bit read out of memory area: %"PRIxADDR" (physical: %"
467 
             PRIxADDR"\n", memaddr, phys_memaddr);
468 1240 phoenix 
  }
469 
 
470 1486 nogj 
  return 0;
471 1240 phoenix 
}
472 
 
473 
 
474 1319 phoenix 
/* Returns 32-bit values from mem array. Big endian version.
475 
 *
476 
 * STATISTICS OK (only used for cpu_access, that is architectural access)
477 
 */
478 1386 nogj 
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
479 349 simons 
{
480 1350 nogj 
  uint32_t temp;
481 1486 nogj 
  oraddr_t phys_memaddr;
482 349 simons 
 
483 547 markom 
  if (config.sim.mprofile)
484 
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
485 532 markom 
//  memaddr = simulate_ic_mmu_fetch(memaddr);
486 1244 hpanther 
 
487 1486 nogj 
  phys_memaddr = memaddr;
488 1452 nogj 
#if !(DYNAMIC_EXECUTION)
489 1486 nogj 
  phys_memaddr = immu_translate(memaddr);
490 1386 nogj 
 
491 
  if (except_pending)
492 
    return 0;
493 1452 nogj 
#endif
494 1386 nogj 
 
495 
  if (config.debug.enabled)
496 
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
497 
 
498 631 simons 
  if (config.ic.enabled)
499 1486 nogj 
    temp = ic_simulate_fetch(phys_memaddr, memaddr);
500 
  else
501 
    temp = evalsim_mem32(phys_memaddr, memaddr);
502 611 simons 
 
503 1386 nogj 
  if (config.debug.enabled)
504 
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);
505 349 simons 
  return temp;
506 
}
507 
 
508 1452 nogj 
/* Returns 32-bit values from mem array. Big endian version.
509 
 *
510 
 * STATISTICS OK
511 
 */
512 1487 nogj 
uint32_t eval_insn_direct(oraddr_t memaddr, int through_mmu)
513 1452 nogj 
{
514 
  if(through_mmu)
515 
    memaddr = peek_into_itlb(memaddr);
516 
 
517 1487 nogj 
  return eval_direct32(memaddr, 0, 0);
518 1452 nogj 
}
519 
 
520 
 
521 1319 phoenix 
/* Returns 16-bit values from mem array. Big endian version.
522 
 *
523 
 * STATISTICS OK (only used for cpu_access, that is architectural access)
524 
 */
525 1350 nogj 
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
526 2 cvs 
{
527 1350 nogj 
  uint16_t temp;
528 1486 nogj 
  oraddr_t phys_memaddr;
529 547 markom 
 
530 
  if (config.sim.mprofile)
531 
    mprofile (memaddr, MPROF_16 | MPROF_READ);
532 
 
533 538 markom 
  if (memaddr & 1) {
534 
    except_handle (EXCEPT_ALIGN, memaddr);
535 
    return 0;
536 
  }
537 574 markom 
 
538 631 simons 
  if (config.debug.enabled)
539 
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
540 
 
541 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 0);
542 1386 nogj 
  if (except_pending)
543 574 markom 
    return 0;
544 66 lampret 
 
545 992 simons 
  if (config.dc.enabled)
546 1486 nogj 
    temp = dc_simulate_read(phys_memaddr, memaddr, 2);
547 
  else
548 
    temp = evalsim_mem16(phys_memaddr, memaddr);
549 611 simons 
 
550 550 markom 
  if (config.debug.enabled)
551 270 markom 
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
552 1486 nogj 
 
553 239 markom 
  return temp;
554 66 lampret 
}
555 
 
556 1319 phoenix 
/* for simulator accesses, the ones that cpu wouldn't do
557 
 *
558 
 * STATISTICS OK.
559 
 */
560 1487 nogj 
uint16_t eval_direct16(oraddr_t memaddr, int through_mmu, int through_dc)
561 1240 phoenix 
{
562 1486 nogj 
  oraddr_t phys_memaddr;
563 
  struct dev_memarea *mem;
564 1240 phoenix 
 
565 1324 phoenix 
  if (memaddr & 1) {
566 1240 phoenix 
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
567 1486 nogj 
    return 0;
568 1240 phoenix 
  }
569 
 
570 1486 nogj 
  phys_memaddr = memaddr;
571 1240 phoenix 
 
572 
  if (through_mmu)
573 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
574 1240 phoenix 
 
575 
  if (through_dc)
576 1486 nogj 
    return dc_simulate_read(phys_memaddr, memaddr, 2);
577 1240 phoenix 
  else {
578 1486 nogj 
    if((mem = verify_memoryarea(phys_memaddr)))
579 
      return mem->direct_ops.readfunc16(phys_memaddr & mem->size_mask,
580 
                                        mem->direct_ops.read_dat16);
581 
    else
582 
      PRINTF("ERR: 16-bit read out of memory area: %"PRIxADDR" (physical: %"
583 
             PRIxADDR"\n", memaddr, phys_memaddr);
584 1240 phoenix 
  }
585 
 
586 1486 nogj 
  return 0;
587 1240 phoenix 
}
588 
 
589 1319 phoenix 
/* Returns 8-bit values from mem array.
590 
 *
591 
 * STATISTICS OK (only used for cpu_access, that is architectural access)
592 
 */
593 1350 nogj 
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
594 221 markom 
{
595 1350 nogj 
  uint8_t temp;
596 1486 nogj 
  oraddr_t phys_memaddr;
597 547 markom 
 
598 
  if (config.sim.mprofile)
599 
    mprofile (memaddr, MPROF_8 | MPROF_READ);
600 
 
601 631 simons 
  if (config.debug.enabled)
602 
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
603 
 
604 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 0);
605 1386 nogj 
  if (except_pending)
606 458 simons 
    return 0;
607 6 lampret 
 
608 992 simons 
  if (config.dc.enabled)
609 1486 nogj 
    temp = dc_simulate_read(phys_memaddr, memaddr, 1);
610 
  else
611 
    temp = evalsim_mem8(phys_memaddr, memaddr);
612 611 simons 
 
613 550 markom 
  if (config.debug.enabled)
614 270 markom 
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
615 239 markom 
  return temp;
616 66 lampret 
}
617 
 
618 1319 phoenix 
/* for simulator accesses, the ones that cpu wouldn't do
619 
 *
620 
 * STATISTICS OK.
621 
 */
622 1487 nogj 
uint8_t eval_direct8(oraddr_t memaddr, int through_mmu, int through_dc)
623 1240 phoenix 
{
624 1486 nogj 
  oraddr_t phys_memaddr;
625 
  struct dev_memarea *mem;
626 1240 phoenix 
 
627 1486 nogj 
  phys_memaddr = memaddr;
628 1240 phoenix 
 
629 
  if (through_mmu)
630 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
631 1240 phoenix 
 
632 
  if (through_dc)
633 1486 nogj 
    return dc_simulate_read(phys_memaddr, memaddr, 1);
634 1240 phoenix 
  else {
635 1486 nogj 
    if((mem = verify_memoryarea(phys_memaddr)))
636 
      return mem->direct_ops.readfunc8(phys_memaddr & mem->size_mask,
637 
                                       mem->direct_ops.read_dat8);
638 
    else
639 
      PRINTF("ERR: 8-bit read out of memory area: %"PRIxADDR" (physical: %"
640 
             PRIxADDR"\n", memaddr, phys_memaddr);
641 1240 phoenix 
  }
642 
 
643 1486 nogj 
  return 0;
644 1319 phoenix 
}
645 1240 phoenix 
 
646 1486 nogj 
/* For cpu accesses
647 
 *
648 
 * NOTE: This function _is_ only called from set_mem32 below and
649 
 * dc_simulate_write.  _Don't_ call it from anywere else.
650 
 */
651 
inline void setsim_mem32(oraddr_t memaddr, oraddr_t vaddr, uint32_t value)
652 66 lampret 
{
653 1486 nogj 
  struct dev_memarea *mem;
654 1319 phoenix 
 
655 1486 nogj 
  if((mem = verify_memoryarea(memaddr))) {
656 
    cur_vadd = vaddr;
657 
    runtime.sim.mem_cycles += mem->ops.delayw;
658 
    mem->ops.writefunc32(memaddr & mem->size_mask, value, mem->ops.write_dat32);
659 1452 nogj 
#if DYNAMIC_EXECUTION
660 1486 nogj 
    dyn_checkwrite(memaddr);
661 1452 nogj 
#endif
662 239 markom 
  } else {
663 1350 nogj 
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
664 
           memaddr);
665 1486 nogj 
    except_handle(EXCEPT_BUSERR, vaddr);
666 239 markom 
  }
667 2 cvs 
}
668 
 
669 1486 nogj 
/* For cpu accesses
670 
 *
671 
 * NOTE: This function _is_ only called from set_mem16 below and
672 
 * dc_simulate_write.  _Don't_ call it from anywere else.
673 
 */
674 
inline void setsim_mem16(oraddr_t memaddr, oraddr_t vaddr, uint16_t value)
675 66 lampret 
{
676 1486 nogj 
  struct dev_memarea *mem;
677 1319 phoenix 
 
678 1486 nogj 
  if((mem = verify_memoryarea(memaddr))) {
679 
    cur_vadd = vaddr;
680 
    runtime.sim.mem_cycles += mem->ops.delayw;
681 
    mem->ops.writefunc16(memaddr & mem->size_mask, value, mem->ops.write_dat16);
682 1452 nogj 
#if DYNAMIC_EXECUTION
683 1486 nogj 
    dyn_checkwrite(memaddr);
684 1452 nogj 
#endif
685 239 markom 
  } else {
686 1350 nogj 
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
687 
           memaddr);
688 1486 nogj 
    except_handle(EXCEPT_BUSERR, vaddr);
689 239 markom 
  }
690 2 cvs 
}
691 
 
692 1486 nogj 
/* For cpu accesses
693 
 *
694 
 * NOTE: This function _is_ only called from set_mem8 below and
695 
 * dc_simulate_write.  _Don't_ call it from anywere else.
696 
 */
697 
inline void setsim_mem8(oraddr_t memaddr, oraddr_t vaddr, uint8_t value)
698 66 lampret 
{
699 1486 nogj 
  struct dev_memarea *mem;
700 1319 phoenix 
 
701 1486 nogj 
  if((mem = verify_memoryarea(memaddr))) {
702 
    cur_vadd = vaddr;
703 
    runtime.sim.mem_cycles += mem->ops.delayw;
704 
    mem->ops.writefunc8(memaddr & mem->size_mask, value, mem->ops.write_dat8);
705 1452 nogj 
#if DYNAMIC_EXECUTION
706 1486 nogj 
    dyn_checkwrite(memaddr);
707 1452 nogj 
#endif
708 239 markom 
  } else {
709 1350 nogj 
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
710 
           memaddr);
711 1486 nogj 
    except_handle(EXCEPT_BUSERR, vaddr);
712 239 markom 
  }
713 2 cvs 
}
714 30 lampret 
 
715 1319 phoenix 
/* Set mem, 32-bit. Big endian version.
716 
 *
717 1446 nogj 
 * STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
718 1319 phoenix 
 *                 where this instruction is used for patching memory,
719 
 *                 wether this is cpu or architectual access is yet to
720 
 *                 be decided)
721 
 */
722 1350 nogj 
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
723 587 markom 
{
724 1486 nogj 
  oraddr_t phys_memaddr;
725 
 
726 587 markom 
  if (config.sim.mprofile)
727 
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
728 
 
729 
  if (memaddr & 3) {
730 
    except_handle (EXCEPT_ALIGN, memaddr);
731 
    return;
732 
  }
733 
 
734 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 1);;
735 587 markom 
  /* If we produced exception don't set anything */
736 1386 nogj 
  if (except_pending)
737 587 markom 
    return;
738 
 
739 
  if (config.debug.enabled) {
740 
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
741 
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
742 
  }
743 
 
744 1486 nogj 
  if(config.dc.enabled)
745 
    dc_simulate_write(phys_memaddr, memaddr, value, 4);
746 
  else
747 
    setsim_mem32(phys_memaddr, memaddr, value);
748 992 simons 
 
749 1218 phoenix 
  if (cur_area && cur_area->log)
750 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
751 
             value);
752 587 markom 
}
753 
 
754 1319 phoenix 
/*
755 
 * STATISTICS NOT OK.
756 
 */
757 1487 nogj 
void set_direct32(oraddr_t memaddr, uint32_t value, int through_mmu,
758 
                  int through_dc)
759 1240 phoenix 
{
760 1486 nogj 
  oraddr_t phys_memaddr;
761 
  struct dev_memarea *mem;
762 1240 phoenix 
 
763 
  if (memaddr & 3) {
764 
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
765 
    return;
766 
  }
767 
 
768 1486 nogj 
  phys_memaddr = memaddr;
769 1240 phoenix 
 
770 
  if (through_mmu) {
771 
    /* 0 - no write access, we do not want a DPF exception do we ;)
772 
     */
773 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 1, through_dc);
774 1240 phoenix 
  }
775 
 
776 1486 nogj 
  if(through_dc)
777 
    dc_simulate_write(memaddr, memaddr, value, 4);
778 
  else {
779 
    if((mem = verify_memoryarea(phys_memaddr)))
780 
      mem->direct_ops.writefunc32(phys_memaddr & mem->size_mask, value,
781 
                                  mem->direct_ops.write_dat32);
782 
    else
783 
      PRINTF("ERR: 32-bit write out of memory area: %"PRIxADDR" (physical: %"
784 
             PRIxADDR")\n", memaddr, phys_memaddr);
785 
  }
786 1240 phoenix 
 
787 
  if (cur_area && cur_area->log)
788 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
789 
             memaddr, value);
790 1240 phoenix 
}
791 
 
792 
 
793 587 markom 
/* Set mem, 16-bit. Big endian version. */
794 
 
795 1350 nogj 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
796 587 markom 
{
797 1486 nogj 
  oraddr_t phys_memaddr;
798 
 
799 587 markom 
  if (config.sim.mprofile)
800 
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
801 
 
802 
  if (memaddr & 1) {
803 
    except_handle (EXCEPT_ALIGN, memaddr);
804 
    return;
805 
  }
806 
 
807 1486 nogj 
  phys_memaddr = dmmu_translate(memaddr, 1);;
808 587 markom 
  /* If we produced exception don't set anything */
809 1386 nogj 
  if (except_pending)
810 587 markom 
    return;
811 
 
812 
  if (config.debug.enabled) {
813 
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
814 
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
815 
  }
816 
 
817 1486 nogj 
  if(config.dc.enabled)
818 
    dc_simulate_write(phys_memaddr, memaddr, value, 2);
819 
  else
820 
    setsim_mem16(phys_memaddr, memaddr, value);
821 992 simons 
 
822 1218 phoenix 
  if (cur_area && cur_area->log)
823 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
824 
             value);
825 587 markom 
}
826 
 
827 1319 phoenix 
/*
828 
 * STATISTICS NOT OK.
829 
 */
830 1487 nogj 
void set_direct16(oraddr_t memaddr, uint16_t value, int through_mmu,
831 
                  int through_dc)
832 1240 phoenix 
{
833 1486 nogj 
  oraddr_t phys_memaddr;
834 
  struct dev_memarea *mem;
835 1240 phoenix 
 
836 1324 phoenix 
  if (memaddr & 1) {
837 1240 phoenix 
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
838 
    return;
839 
  }
840 
 
841 1486 nogj 
  phys_memaddr = memaddr;
842 1240 phoenix 
 
843 
  if (through_mmu) {
844 
    /* 0 - no write access, we do not want a DPF exception do we ;)
845 
     */
846 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
847 1240 phoenix 
  }
848 
 
849 1486 nogj 
  if(through_dc)
850 
    dc_simulate_write(memaddr, memaddr, value, 2);
851 
  else {
852 
    if((mem = verify_memoryarea(phys_memaddr)))
853 
      mem->direct_ops.writefunc16(phys_memaddr & mem->size_mask, value,
854 
                                  mem->direct_ops.write_dat16);
855 
    else
856 
      PRINTF("ERR: 16-bit write out of memory area: %"PRIxADDR" (physical: %"
857 
             PRIxADDR"\n", memaddr, phys_memaddr);
858 
  }
859 1240 phoenix 
 
860 
  if (cur_area && cur_area->log)
861 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
862 
             memaddr, value);
863 1240 phoenix 
}
864 
 
865 587 markom 
/* Set mem, 8-bit. */
866 1350 nogj 
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
867 587 markom 
{
868 1486 nogj 
  oraddr_t phys_memaddr;
869 
 
870 587 markom 
  if (config.sim.mprofile)
871 
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
872 
 
873 1486 nogj 
  phys_memaddr = memaddr;
874 
 
875 
  phys_memaddr = dmmu_translate(memaddr, 1);;
876 587 markom 
  /* If we produced exception don't set anything */
877 1386 nogj 
  if (except_pending) return;
878 587 markom 
 
879 
  if (config.debug.enabled) {
880 
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
881 
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
882 
  }
883 
 
884 1486 nogj 
  if(config.dc.enabled)
885 
    dc_simulate_write(phys_memaddr, memaddr, value, 1);
886 
  else
887 
    setsim_mem8(phys_memaddr, memaddr, value);
888 992 simons 
 
889 1218 phoenix 
  if (cur_area && cur_area->log)
890 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
891 
             value);
892 587 markom 
}
893 
 
894 1319 phoenix 
/*
895 
 * STATISTICS NOT OK.
896 
 */
897 1487 nogj 
void set_direct8(oraddr_t memaddr, uint8_t value, int through_mmu,
898 
                 int through_dc)
899 1240 phoenix 
{
900 1486 nogj 
  oraddr_t phys_memaddr;
901 
  struct dev_memarea *mem;
902 1240 phoenix 
 
903 1486 nogj 
  phys_memaddr = memaddr;
904 1240 phoenix 
 
905 
  if (through_mmu) {
906 
    /* 0 - no write access, we do not want a DPF exception do we ;)
907 
     */
908 1486 nogj 
    phys_memaddr = peek_into_dtlb(memaddr, 0, through_dc);
909 1240 phoenix 
  }
910 
 
911 1486 nogj 
  if(through_dc)
912 
    dc_simulate_write(phys_memaddr, memaddr, value, 1);
913 
  else {
914 
    if((mem = verify_memoryarea(phys_memaddr)))
915 
      mem->direct_ops.writefunc8(phys_memaddr & mem->size_mask, value,
916 
                                 mem->direct_ops.write_dat8);
917 
    else
918 
      PRINTF("ERR: 8-bit write out of memory area: %"PRIxADDR" (physical: %"
919 
             PRIxADDR"\n", memaddr, phys_memaddr);
920 
  }
921 1240 phoenix 
 
922 
  if (cur_area && cur_area->log)
923 1350 nogj 
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
924 
             memaddr, value);
925 1240 phoenix 
}
926 
 
927 
 
928 1486 nogj 
/* set_program32 - same as set_direct32, but it also writes to memory that is
929 
 *                 non-writeable to the rest of the sim.  Used to do program
930 
 *                 loading.
931 
 */
932 
void set_program32(oraddr_t memaddr, uint32_t value)
933 
{
934 
  struct dev_memarea *mem;
935 
 
936 1556 nogj 
  if(memaddr & 3) {
937 
    PRINTF("%s(): ERR unaligned 32-bit program write\n", __FUNCTION__);
938 1486 nogj 
    return;
939 
  }
940 
 
941 
  if((mem = verify_memoryarea(memaddr))) {
942 1556 nogj 
    mem->ops.writeprog32(memaddr & mem->size_mask, value,
943 
                         mem->ops.writeprog32_dat);
944 1486 nogj 
  } else
945 
    PRINTF("ERR: 32-bit program load out of memory area: %"PRIxADDR"\n",
946 
           memaddr);
947 
}
948 
 
949 1556 nogj 
/* set_program8 - same as set_direct8, but it also writes to memory that is
950 
 *                non-writeable to the rest of the sim.  Used to do program
951 
 *                loading.
952 
 */
953 
void set_program8(oraddr_t memaddr, uint8_t value)
954 
{
955 
  struct dev_memarea *mem;
956 
 
957 
  if((mem = verify_memoryarea(memaddr))) {
958 
    mem->ops.writeprog8(memaddr & mem->size_mask, value,
959 
                        mem->ops.writeprog8_dat);
960 
  } else
961 
    PRINTF("ERR: 8-bit program load out of memory area: %"PRIxADDR"\n",
962 
           memaddr);
963 
}
964 
 
965 1350 nogj 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
966 361 markom 
{
967 1350 nogj 
  oraddr_t i, j;
968 361 markom 
  struct label_entry *tmp;
969 
  int ilen = disasm ? 4 : 16;
970 
 
971 
  for(i = from; i < to; i += ilen) {
972 1350 nogj 
    PRINTF("%"PRIxADDR": ", i);
973 361 markom 
    for (j = 0; j < ilen;) {
974 
      if (!disasm) {
975 
        tmp = NULL;
976 1350 nogj 
        if (verify_memoryarea(i + j)) {
977 361 markom 
          struct label_entry *entry;
978 
          entry = get_label(i + j);
979 
          if (entry)
980 997 markom 
            PRINTF("(%s)", entry->name);
981 1487 nogj 
          PRINTF("%02"PRIx8" ", eval_direct8(i + j, 0, 0));
982 997 markom 
        } else PRINTF("XX ");
983 361 markom 
        j++;
984 
      } else {
985 1487 nogj 
        uint32_t _insn = eval_direct32(i, 0, 0);
986 361 markom 
        int index = insn_decode (_insn);
987 
        int len = insn_len (index);
988 
 
989 
        tmp = NULL;
990 1350 nogj 
        if (verify_memoryarea(i + j)) {
991 361 markom 
          struct label_entry *entry;
992 
          entry = get_label(i + j);
993 
          if (entry)
994 997 markom 
            PRINTF("(%s)", entry->name);
995 361 markom 
 
996 1350 nogj 
          PRINTF(": %08"PRIx32" ", _insn);
997 361 markom 
          if (index >= 0) {
998 
            disassemble_insn (_insn);
999 997 markom 
            PRINTF(" %s", disassembled);
1000 361 markom 
          } else
1001 997 markom 
            PRINTF("<invalid>");
1002 
        } else PRINTF("XXXXXXXX");
1003 361 markom 
        j += len;
1004 
      }
1005 
    }
1006 
    if (nl)
1007 997 markom 
      PRINTF ("\n");
1008 361 markom 
  }
1009 
}
1010 
 
1011 426 markom 
/* Closes files, etc. */
1012 
 
1013 1486 nogj 
void done_memory_table (void)
1014 426 markom 
{
1015 
  struct dev_memarea *ptmp;
1016 
 
1017 
  /* Check list of registered devices. */
1018 
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
1019 
    if (ptmp->log)
1020 
      fclose (ptmp->log);
1021 
  }
1022 
}
1023 427 markom 
 
1024 
/* Displays current memory configuration */
1025 
 
1026 1486 nogj 
void memory_table_status (void)
1027 427 markom 
{
1028 
  struct dev_memarea *ptmp;
1029 
 
1030 
  /* Check list of registered devices. */
1031 
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
1032 1486 nogj 
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32"\n",
1033 427 markom 
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
1034 1486 nogj 
      ptmp->size);
1035 997 markom 
    PRINTF ("\t");
1036 1486 nogj 
    if (ptmp->ops.delayr >= 0)
1037 
      PRINTF ("read delay = %i cycles, ", ptmp->ops.delayr);
1038 427 markom 
    else
1039 997 markom 
      PRINTF ("reads not possible, ");
1040 427 markom 
 
1041 1486 nogj 
    if (ptmp->ops.delayw >= 0)
1042 
      PRINTF ("write delay = %i cycles", ptmp->ops.delayw);
1043 427 markom 
    else
1044 997 markom 
      PRINTF ("writes not possible");
1045 427 markom 
 
1046 
    if (ptmp->log)
1047 997 markom 
      PRINTF (", (logged)\n");
1048 427 markom 
    else
1049 997 markom 
      PRINTF ("\n");
1050 427 markom 
  }
1051 
}
1052 433 markom 
 
1053 
/* Outputs time in pretty form to dest string */
1054 
 
1055 897 markom 
char *generate_time_pretty (char *dest, long time_ps)
1056 433 markom 
{
1057 
  int exp3 = 0;
1058 
  if (time_ps) {
1059 
    while ((time_ps % 1000) == 0) {
1060 
      time_ps /= 1000;
1061 
      exp3++;
1062 
    }
1063 
  }
1064 1308 phoenix 
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
1065 897 markom 
  return dest;
1066 433 markom 
}

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