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/* abstract.c -- Abstract entities header file

   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

#include <stdio.h>

#define DEFAULT_MEMORY_START  0

#define DEFAULT_MEMORY_LEN  0x800000

#define STACK_SIZE  20

#define LABELNAME_LEN 50

#define INSNAME_LEN 15

#define OPERANDNAME_LEN 50

#define MAX_OPERANDS    (5)

#define OP_MEM_ACCESS 0x80000000

/* Cache tag types.  */

#define CT_NONE            0

#define CT_VIRTUAL         1

#define CT_PHYSICAL        2

/* Instruction queue */

struct iqueue_entry {

  int insn_index;

  uint32_t insn;

  oraddr_t insn_addr;

};

/* Memory regions assigned to devices */

struct dev_memarea {

  struct dev_memarea *next;

  /*unsigned long start;

  unsigned long end;*/         /* if start + size > end, this block is disabled; to enable it recalculate end addr. */

  oraddr_t addr_mask;

  oraddr_t addr_compare;

  uint32_t size;

  uint32_t size_mask;        /* Address mask, calculated out of size */

  unsigned int granularity;  /* how many bytes read/write accepts: 1/2/4 */

  int delayr;                /* Read delay */

  int delayw;                /* Write delay */

  int chip_select;           /* Needed by memory controller; specifies chip

                              * select number for this memory area. */

  int valid;                 /* This bit reflect the memory controler valid bit */

  FILE *log;                 /* log file if this device is to be logged, NULL otherwise */

  uint32_t (*readfunc)(oraddr_t);

  void (*writefunc)(oraddr_t, uint32_t);

  /* private data */

  unsigned long misc;

};

extern struct iqueue_entry iqueue[20];

extern struct iqueue_entry icomplet[20];

extern oraddr_t pc;

extern int    mem_cycles;   /* Number of memory cycles in during this instruction execution */

extern int    cycles;       /* Total number of cycles executed so far */

extern void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl);

extern uint32_t eval_mem32(oraddr_t memaddr,int*);

extern uint16_t eval_mem16(oraddr_t memaddr,int*);

extern uint8_t eval_mem8(oraddr_t memaddr,int*);

void set_mem32(oraddr_t memaddr, uint32_t value,int*);

extern void set_mem16(oraddr_t memaddr, uint16_t value,int*);

extern void set_mem8(oraddr_t memaddr, uint8_t value,int*);

uint32_t evalsim_mem32(oraddr_t);

uint16_t evalsim_mem16(oraddr_t);

uint8_t evalsim_mem8(oraddr_t);

uint32_t evalsim_mem32_atomic(oraddr_t, int);

uint16_t evalsim_mem16_atomic(oraddr_t, int);

uint8_t evalsim_mem8_atomic(oraddr_t, int);

void setsim_mem32(oraddr_t, uint32_t);

void setsim_mem16(oraddr_t, uint16_t);

void setsim_mem8(oraddr_t, uint8_t);

void setsim_mem32_atomic(oraddr_t, uint32_t, int);

void setsim_mem16_atomic(oraddr_t, uint16_t, int);

void setsim_mem8_atomic(oraddr_t, uint8_t, int);

void init_memory_table ();

/* Changes read/write memory in read/write only */

void lock_memory_table ();

/* Closes files, etc. */

void done_memory_table ();

/* Displays current memory configuration */

void memory_table_status ();

/* Register read and write function for a memory area.

   addr is inside the area, if addr & addr_mask == addr_compare

   (used also by peripheral devices like 16450 UART etc.) */

void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,

                         uint32_t size, unsigned granularity, unsigned mc_dev,

                         uint32_t (readfunc)(oraddr_t),

                         void (writefunc)(oraddr_t, uint32_t));

/* Register read and write function for a memory area.

   Memory areas should be aligned. Memory area is rounded up to

   fit the nearest 2^n aligment.

   (used also by peripheral devices like 16450 UART etc.)

   If mc_dev is 1, this means that this device will be checked first for match

   and will be accessed in case in overlaping memory spaces.

   Only one device can have this set to 1 (used for memory controller) */

void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,

                         unsigned mc_dev, uint32_t (readfunc)(oraddr_t),

                         void (writefunc)(oraddr_t, uint32_t));

/* Finds the memory area for the address and adjust the read and write delays for it. */

void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw);

/* Check if access is to registered area of memory. */

struct dev_memarea *verify_memoryarea(oraddr_t addr);

/* Outputs time in pretty form to dest string. */

char *generate_time_pretty (char *dest, long time_ps);

/* Returns 32-bit values from mem array. */

uint32_t eval_insn(oraddr_t, int *);

void simmem_write_word(oraddr_t addr, uint32_t value);

uint32_t simmem_read_word(oraddr_t addr);

uint32_t eval_direct32(oraddr_t addr, int *breakpoint, int through_mmu, int through_dc);

void set_direct32(uint32_t addr, uint32_t value, int *breakpoint, int through_mmu, int through_dc);

/* Temporary variable to increase speed.  */

extern struct dev_memarea *cur_area;

/* Virtual address of current access. */

extern oraddr_t cur_vadd;

/* These are set by mmu if cache inhibit bit is set for current acces.  */

extern int data_ci, insn_ci;

/* Added by MM */

#ifndef LONGEST

#define LONGEST long long

#define ULONGEST unsigned long long

#endif /* ! LONGEST */

/* Instructions left to execute */

extern int cont_run;

/* History of execution */

#define HISTEXEC_LEN 200

extern int histexec[HISTEXEC_LEN];