OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cuc/] [verilog.c] - Blame information for rev 1778

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1244 hpanther 
/* verilog.c -- OpenRISC Custom Unit Compiler, verilog generator
2 
 *    Copyright (C) 2002 Marko Mlinar, markom@opencores.org
3 
 *
4 
 *    This file is part of OpenRISC 1000 Architectural Simulator.
5 
 *
6 
 *    This program is free software; you can redistribute it and/or modify
7 
 *    it under the terms of the GNU General Public License as published by
8 
 *    the Free Software Foundation; either version 2 of the License, or
9 
 *    (at your option) any later version.
10 
 *
11 
 *    This program is distributed in the hope that it will be useful,
12 
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
 *    GNU General Public License for more details.
15 
 *
16 
 *    You should have received a copy of the GNU General Public License
17 
 *    along with this program; if not, write to the Free Software
18 
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19 
 
20 
#include <stdio.h>
21 
#include <stdlib.h>
22 
#include <stdarg.h>
23 
#include <assert.h>
24 1308 phoenix 
 
25 1350 nogj 
#include "config.h"
26 
 
27 
#ifdef HAVE_INTTYPES_H
28 
#include <inttypes.h>
29 
#endif
30 
 
31 
#include "port.h"
32 
#include "arch.h"
33 1308 phoenix 
#include "abstract.h"
34 1244 hpanther 
#include "cuc.h"
35 
#include "insn.h"
36 
#include "profiler.h"
37 
#include "sim-config.h"
38 1555 nogj 
#include "misc.h"
39 1244 hpanther 
 
40 
/* Shortcut */
41 
#define GEN(x...) fprintf (fo, x)
42 
 
43 
/* Find index of load/store/call */
44 
int find_lsc_index (cuc_func *f, int ref)
45 
{
46 
  int c = 0;
47 
  int i;
48 
  int load;
49 
 
50 
  if (f->INSN(ref).index == II_CALL) {
51 
    for (i = 0; i < f->nmsched; i++) {
52 
      if (f->msched[i] == ref) break;
53 
      if (f->mtype[i] & MT_CALL) c++;
54 
    }
55 
  } else {
56 
    load = II_IS_LOAD (f->INSN(ref).index);
57 
    for (i = 0; i < f->nmsched; i++) {
58 
      if (f->msched[i] == ref) break;
59 1557 nogj 
      if ((load && (f->mtype[i] & MT_LOAD))
60 
       || (!load && (f->mtype[i] & MT_STORE))) c++;
61 1244 hpanther 
    }
62 
  }
63 
  return c;
64 
}
65 
 
66 
/* Print out dependencies as verilog expression */
67 
void print_deps (FILE *fo, cuc_func *f, int b, dep_list *t, int registered)
68 
{
69 
  if (t) {
70 
    int first = 0;
71 
    while (t) {
72 
      if (f->INSN(t->ref).type & IT_MEMORY) {
73 
        GEN ("%s%c_end[%i]", first ? " && " : "",
74 
                  II_IS_LOAD (f->INSN(t->ref).index) ? 'l' : 's', find_lsc_index (f, t->ref));
75 
      } else if (f->INSN(t->ref).index == II_CALL) {
76 
        GEN ("%sf_end[%i]", first ? " && " : "", find_lsc_index (f, t->ref));
77 
      } else {
78 1308 phoenix 
        PRINTF ("print_deps: err %lx\n", t->ref);
79 1244 hpanther 
        assert (0);
80 
      }
81 
      first = 1;
82 
      t = t->next;
83 
    }
84 
  } else {
85 
    if (registered) GEN ("bb_start_r[%i]", b);
86 
    else GEN ("bb_start[%i]", b);
87 
  }
88 
}
89 
 
90 
char *print_op_v (cuc_func *f, char *s, int ref, int j)
91 
{
92 
  unsigned long op = f->INSN(ref).op[j];
93 
  unsigned long opt = f->INSN(ref).opt[j];
94 
  switch (opt & ~OPT_DEST) {
95 
    case OPT_NONE: assert (0); break;
96 
    case OPT_CONST: if (f->INSN(ref).type & IT_COND && (f->INSN(ref).index == II_CMOV
97 
                     || f->INSN(ref).index == II_ADD)) {
98 
                      assert (op == 0 || op == 1);
99 1308 phoenix 
                      sprintf (s, "1'b%lx", op);
100 
                    } else sprintf (s, "32'h%lx", op);
101 1244 hpanther 
                    break;
102 
    case OPT_REGISTER:
103 
                    if (opt & OPT_DEST) sprintf (s, "t%x_%x", REF_BB(ref), REF_I(ref));
104 1308 phoenix 
                    else sprintf (s, "r%li_%c", op, opt & OPT_DEST ? 'o' : 'i');
105 1244 hpanther 
                    break;
106 
#if 0
107 
    case OPT_FREG:  assert (opt & OPT_DEST);
108 
                    sprintf (s, "fr%i_o", op);
109 
                    break;
110 
#endif
111 1308 phoenix 
    case OPT_REF:   sprintf (s, "t%lx_%lx", REF_BB(op), REF_I(op)); break;
112 1244 hpanther 
  }
113 
  return s;
114 
}
115 
 
116 
/* Prints out specified instruction */
117 
void print_insn_v (FILE *fo, cuc_func *f, int b, int i)
118 
{
119 
  cuc_insn *ii = &f->bb[b].insn[i];
120 
  char *s = known[ii->index].rtl;
121 
  char tmp[200] = "";
122 
 
123 
  assert (s);
124 
  while (*s) {
125 
    if (*s <= MAX_OPERANDS) {
126 
      char t[30];
127 
      sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));
128 1557 nogj 
    } else if (*s == '\b') sprintf (tmp, "%s%i", tmp, b);
129 1244 hpanther 
    else sprintf (tmp, "%s%c", tmp, *s);
130 
    s++;
131 
  }
132 
  GEN ("%-40s /* %s */\n", tmp, ii->disasm);
133 
  if (ii->type & IT_MEMORY) {
134 1308 phoenix 
    int nls = find_lsc_index (f, REF (b, i));
135 1244 hpanther 
    if (II_IS_LOAD (ii->index)) {
136 
      int nm;
137 
      for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
138 
      assert (nm < f->nmsched);
139 
 
140 
      GEN ("  if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
141 
      switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
142 
        case 1: GEN ("l_dat_i & 32'hff;\n");
143 
                break;
144 
        case 2: GEN ("l_dat_i & 32'hffff;\n");
145 
                break;
146 
        case 4 | MT_SIGNED:
147 
        case 4: GEN ("l_dat_i;\n");
148 
                break;
149 
        case 1 | MT_SIGNED:
150 
                GEN ("{24{l_dat_i[7]}, l_dat_i[7:0]};\n");
151 
                break;
152 
        case 2 | MT_SIGNED:
153 
                GEN ("{16{l_dat_i[15]}, l_dat_i[15:0]};\n");
154 
                break;
155 
        default: assert (0);
156 
      }
157 
    }
158 
  } else if (ii->index == II_LRBB) {
159 
    GEN ("  if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
160 
    assert (f->bb[b].prev[0] >= 0);
161 
    if (f->bb[b].prev[0] == BBID_START)
162 
      GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp start_i;\n", b, b, i);
163 
    else
164 
      GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
165 
  } else if (ii->index == II_REG) {
166 
    assert (ii->opt[1] == OPT_REF);
167 
    GEN ("  if (");
168 
    if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);
169 
    else GEN ("bb_stb[%i]", b);
170 1308 phoenix 
    GEN (") t%x_%x <= #Tp t%lx_%lx;\n",  b, i,
171 1244 hpanther 
                    REF_BB (ii->op[1]), REF_I (ii->op[1]));
172 
  }
173 
}
174 
 
175 
/* Outputs binary number */
176 1557 nogj 
/*
177 1244 hpanther 
static char *bin_str (unsigned long x, int len)
178 
{
179 
  static char bx[33];
180 
  char *s = bx;
181 
  while (len > 0) *s++ = '0' + ((x >> --len) & 1);
182 
  *s = '\0';
183 
  return bx;
184 
}
185 1557 nogj 
*/
186 1244 hpanther 
 
187 
/* Returns index of branch instruction inside a block b */
188 
static int branch_index (cuc_bb *bb)
189 
{
190 
  int i;
191 
  for (i = bb->ninsn - 1; i >= 0; i--)
192 
    if (bb->insn[i].type & IT_BRANCH) return i;
193 
  return -1;
194 
}
195 
 
196 
static void print_turn_off_dep (FILE *fo, cuc_func *f, dep_list *dep)
197 
{
198 
  while (dep) {
199 
    assert (f->INSN(dep->ref).type & IT_MEMORY || f->INSN(dep->ref).index == II_CALL);
200 
    GEN ("      %c_stb[%i] <= #Tp 1'b0;\n", f->INSN(dep->ref).index == II_CALL ? 'f'
201 
            : II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_lsc_index (f, dep->ref));
202 
    dep = dep->next;
203 
  }
204 
}
205 
 
206 
static int func_index (cuc_func *f, int ref)
207 
{
208 
  int i;
209 
  unsigned long addr;
210 
  assert (f->INSN(ref).index == II_CALL && f->INSN(ref).opt[0] & OPT_CONST);
211 
  addr = f->INSN(ref).op[0];
212 
  for (i = 0; i < f->nfdeps; i++)
213 
    if (f->fdeps[i]->start_addr == addr) return i;
214 
 
215 
  assert (0);
216 
  return -1;
217 
}
218 
 
219 
/* Generates verilog file out of insn dataflow */
220 
void output_verilog (cuc_func *f, char *filename, char *funcname)
221 
{
222 
  FILE *fo;
223 
  int b, i, j;
224 
  int ci = 0, co = 0;
225 
  int nloads = 0, nstores = 0, ncalls = 0;
226 
  char tmp[256];
227 
  sprintf (tmp, "%s.v", filename);
228 
 
229 
  log ("Generating verilog file \"%s\"\n", tmp);
230 
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
231 
  if ((fo = fopen (tmp, "wt+")) == NULL) {
232 
    fprintf (stderr, "Cannot open '%s'\n", tmp);
233 
    exit (1);
234 
  }
235 
 
236 
  /* output header */
237 
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
238 
  GEN ("   (C) 2002 Opencores\n");
239 
  GEN ("   function   \"%s\"\n", funcname);
240 1308 phoenix 
  GEN ("   at         %08lx - %08lx\n", f->start_addr, f->end_addr);
241 1244 hpanther 
  GEN ("   num BBs    %i */\n\n", f->num_bb);
242 
 
243 
  GEN ("`include \"timescale.v\"\n\n");
244 
  GEN ("module %s (clk, rst,\n", filename);
245 
  GEN ("              l_adr_o, l_dat_i, l_req_o,\n");
246 
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i,\n");
247 
  GEN ("              s_adr_o, s_dat_o, s_req_o,\n");
248 
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i,\n");
249 
 
250 
  GEN ("/* inputs */  ");
251 
  for (i = 0; i < MAX_REGS; i++)
252 
    if (f->used_regs[i]) {
253 
      GEN ("r%i_i, ", i);
254 
      ci++;
255 
    }
256 
  if (!ci) GEN ("/* NONE */");
257 
 
258 
  GEN ("\n/* outputs */ ");
259 
  for (i = 0; i < MAX_REGS; i++)
260 
    if (f->lur[i] >= 0 && !f->saved_regs[i]) {
261 
      GEN ("r%i_o, ", i);
262 
      co++;
263 
    }
264 
 
265 
  if (!co) GEN ("/* NONE */");
266 
  if (f->nfdeps) {
267 
    GEN ("\n/* f. calls */, fstart_o, %sfend_i, fr11_i, ",
268 
                    log2_int (f->nfdeps) > 0 ? "fid_o, " : "");
269 
    for (i = 0; i < 6; i++) GEN ("fr%i_o, ", i + 3);
270 
  }
271 
  GEN ("\n              start_i, end_o, busy_o);\n\n");
272 
 
273 
  GEN ("parameter Tp = 1;\n\n");
274 
 
275 
  GEN ("input         clk, rst;\n");
276 
  GEN ("input         start_i;\t/* Module starts when set to 1 */ \n");
277 
  GEN ("output        end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
278 
  GEN ("output        busy_o;\t/* Set when module should not be interrupted */\n");
279 
  GEN ("\n/* Bus signals */\n");
280 
  GEN ("output        l_req_o, s_req_o;\n");
281 
  GEN ("input         l_rdy_i, s_rdy_i;\n");
282 
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
283 
  GEN ("output [31:0] l_adr_o, s_adr_o;\n");
284 
  GEN ("output        l_linbrst_o, s_linbrst_o;\n");
285 
  GEN ("input  [31:0] l_dat_i;\n");
286 
  GEN ("output [31:0] s_dat_o;\n\n");
287 
 
288 
  GEN ("reg           l_req_o, s_req_o;\n");
289 
  GEN ("reg    [31:0] l_adr_o, s_adr_o;\n");
290 
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
291 
  GEN ("reg    [31:0] s_dat_o;\n");
292 
  GEN ("reg           l_linbrst_o, s_linbrst_o;\n");
293 
 
294 
  if (ci || co) GEN ("\n/* module ports */\n");
295 
  if (ci) {
296 
    int first = 1;
297 
    GEN ("input  [31:0]");
298 
    for (i = 0; i < MAX_REGS; i++)
299 
      if (f->used_regs[i]) {
300 
        GEN ("%sr%i_i", first ? " " : ", ", i);
301 
        first = 0;
302 
      }
303 
    GEN (";\n");
304 
  }
305 
 
306 
  if (co) {
307 
    int first = 1;
308 
    GEN ("output [31:0]");
309 
    for (i = 0; i < MAX_REGS; i++)
310 
      if (f->lur[i] >= 0 && !f->saved_regs[i]) {
311 
        GEN ("%sr%i_o", first ? " " : ", ", i);
312 
        first = 0;
313 
      }
314 
    GEN (";\n");
315 
  }
316 
 
317 
  if (f->nfdeps) {
318 
    GEN ("\n/* Function calls */\n");
319 
    GEN ("output [31:0] fr3_o");
320 
    for (i = 1; i < 6; i++) GEN (", fr%i_o", i + 3);
321 
    GEN (";\n");
322 
    GEN ("input  [31:0] fr11_i;\n");
323 
    if (log2_int(f->nfdeps) > 0) GEN ("output [%i:0] fid_o;\n", log2_int(f->nfdeps));
324 
    GEN ("output        fstart_o;\n");
325 
    GEN ("input         fend_i;\n");
326 
  }
327 
 
328 
  /* Count loads & stores */
329 
  for (i = 0; i < f->nmsched; i++)
330 
    if (f->mtype[i] & MT_STORE) nstores++;
331 
    else if (f->mtype[i] & MT_LOAD) nloads++;
332 
    else if (f->mtype[i] & MT_CALL) ncalls++;
333 
 
334 
  /* Output internal registers for loads */
335 
  if (nloads) {
336 
    int first = 1;
337 
    int num = 0;
338 
    GEN ("\n/* internal registers for loads */\n");
339 
    for (i = 0; i < f->nmsched; i++)
340 
      if (f->mtype[i] & MT_LOAD) {
341 
        GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ",
342 
                REF_BB(f->msched[i]), REF_I(f->msched[i]));
343 
 
344 
        if (num >= 8) {
345 
          GEN (";\n");
346 
          first = 1;
347 
          num = 0;
348 
        } else {
349 
          first = 0;
350 
          num++;
351 
        }
352 
      }
353 
    if (!first) GEN (";\n");
354 
  }
355 
 
356 
  /* Internal register for function return value */
357 
  if (f->nfdeps) {
358 
    GEN ("\n/* Internal register for function return value */\n");
359 
    GEN ("reg     [31:0] fr11_r;\n");
360 
  }
361 
 
362 
  GEN ("\n/* 'zero or one' hot state machines */\n");
363 
  if (nloads) GEN ("reg     [%i:0] l_stb; /* loads */\n", nloads - 1);
364 
  if (nstores) GEN ("reg     [%i:0] s_stb; /* stores */\n", nstores - 1);
365 
  GEN ("reg     [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
366 
 
367 
  {
368 
    int first = 2;
369 
    int num = 0;
370 
    for (b = 0; b < f->num_bb; b++)
371 
      for (i = 0; i < f->bb[b].ninsn; i++)
372 
        if (f->bb[b].insn[i].type & IT_COND
373 
         && f->bb[b].insn[i].index != II_REG
374 
         && f->bb[b].insn[i].index != II_LRBB) {
375 
          if (first == 2) GEN ("\n/* basic block condition wires */\n");
376 
          GEN ("%st%x_%x", first ? "wire          " : ", ", b, i);
377 
          if (num >= 8) {
378 
            GEN (";\n");
379 
            first = 1;
380 
            num = 0;
381 
          } else {
382 
            first = 0;
383 
            num++;
384 
          }
385 
        }
386 
    if (!first) GEN (";\n");
387 
 
388 
    GEN ("\n/* forward declaration of normal wires */\n");
389 
    num = 0;
390 
    first = 1;
391 
    for (b = 0; b < f->num_bb; b++)
392 
      for (i = 0; i < f->bb[b].ninsn; i++)
393 
        if (!(f->bb[b].insn[i].type & (IT_COND | IT_BRANCH))
394 
         && f->bb[b].insn[i].index != II_REG
395 
         && f->bb[b].insn[i].index != II_LRBB) {
396 
          /* Exclude loads */
397 
          if (f->bb[b].insn[i].type & IT_MEMORY && II_IS_LOAD (f->bb[b].insn[i].index)) continue;
398 
          GEN ("%st%x_%x", first ? "wire   [31:0] " : ", ", b, i);
399 
          if (num >= 8) {
400 
            GEN (";\n");
401 
            first = 1;
402 
            num = 0;
403 
          } else {
404 
            first = 0;
405 
            num++;
406 
          }
407 
        }
408 
    if (!first) GEN (";\n");
409 
 
410 
    GEN ("\n/* forward declaration registers */\n");
411 
    num = 0;
412 
    first = 1;
413 
    for (b = 0; b < f->num_bb; b++)
414 
      for (i = 0; i < f->bb[b].ninsn; i++)
415 
        if (f->bb[b].insn[i].index == II_REG
416 
         && f->bb[b].insn[i].index != II_LRBB) {
417 
          GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ", b, i);
418 
          if (num >= 8) {
419 
            GEN (";\n");
420 
            first = 1;
421 
            num = 0;
422 
          } else {
423 
            first = 0;
424 
            num++;
425 
          }
426 
        }
427 
    if (!first) GEN (";\n");
428 
 
429 
    num = 0;
430 
    first = 1;
431 
    for (b = 0; b < f->num_bb; b++)
432 
      for (i = 0; i < f->bb[b].ninsn; i++)
433 
        if (f->bb[b].insn[i].index != II_REG
434 
         && f->bb[b].insn[i].index == II_LRBB) {
435 
          GEN ("%st%x_%x", first ? "reg           " : ", ", b, i);
436 
          if (num >= 8) {
437 
            GEN (";\n");
438 
            first = 1;
439 
            num = 0;
440 
          } else {
441 
            first = 0;
442 
            num++;
443 
          }
444 
        }
445 
    if (!first) GEN (";\n");
446 
  }
447 
 
448 
  if (nloads || nstores) GEN ("\n/* dependencies */\n");
449 
  if (nloads) GEN ("wire    [%i:0] l_end = l_stb & {%i{l_rdy_i}};\n",
450 
                  nloads - 1, nloads);
451 
  if (nstores) GEN ("wire    [%i:0] s_end = s_stb & {%i{s_rdy_i}};\n",
452 
                  nstores - 1, nstores);
453 
  if (ncalls) GEN ("wire    [%i:0] f_end = f_stb & {%i{fend_i}};\n",
454 
                  ncalls - 1, ncalls);
455 
 
456 
  GEN ("\n/* last dependency */\n");
457 
  GEN ("wire   end_o = ");
458 
  for (b = 0; b < f->num_bb; b++) {
459 
    for (i = 0; i < 2; i++) if (f->bb[b].next[i] == BBID_END) {
460 
      GEN ("bb_stb[%i]", b);
461 
      if (f->bb[b].mdep) {
462 
        GEN (" && ");
463 
        print_deps (fo, f, b, f->bb[b].mdep, 0);
464 
      }
465 
      /* Is branch to BBID_END conditional? */
466 
      if (f->bb[b].next[1 - i] >= 0) {
467 
        int bidx = branch_index (&f->bb[b]);
468 
        char t[30];
469 
        print_op_v (f, t, REF (b, bidx), 1);
470 
        GEN (" && %s%s", i ? "" : "!", t);
471 
      }
472 
    }
473 
  }
474 
  GEN (";\n");
475 
  GEN ("wire   busy_o = |bb_stb;\n");
476 
 
477 
 
478 
  GEN ("\n/* Basic block triggers */\n");
479 
  GEN ("wire   [%2i:0] bb_start = {\n", f->num_bb - 1);
480 
  for (b = f->num_bb - 1; b >= 0; b--) {
481 
    GEN ("    /* bb_start[%2i] */ ", b);
482 
    for (i = 0; i < 2; i++) if (f->bb[b].prev[i] >= 0 && f->bb[b].prev[i] != BBID_START) {
483 
      cuc_bb *prev = &f->bb[f->bb[b].prev[i]];
484 
      int t;
485 
      if (i) GEN ("\n                    || ");
486 
      if (prev->mdep) {
487 
        print_deps (fo, f, f->bb[b].prev[i], prev->mdep, 0);
488 
        GEN (" && ");
489 
      }
490 
      GEN ("bb_stb[%i]", f->bb[b].prev[i]);
491 
      if (prev->next[0] >= 0 && prev->next[0] != BBID_END
492 
       && prev->next[1] >= 0 && prev->next[1] != BBID_END) {
493 
        int bi = REF (f->bb[b].prev[i], branch_index (&f->bb[f->bb[b].prev[i]]));
494 
        int ci;
495 
        assert (bi >= 0);
496 
        ci = f->INSN(bi).op[1];
497 
        t = prev->next[0] == b;
498 
        GEN (" && ");
499 
        if (f->INSN(bi).opt[1] & OPT_REF) {
500 
          GEN ("%st%x_%x", t ? "" : "!", REF_BB(ci), REF_I(ci));
501 
        } else {
502 
          cucdebug (5, "%x!%x!%x\n", bi, ci, f->INSN(bi).opt[1]);
503 
          assert (f->INSN(bi).opt[1] & OPT_CONST);
504 
          GEN ("%s%i", t ? "" : "!", ci);
505 
        }
506 
      }
507 
    } else break;
508 
    if (!i) GEN ("start_i");
509 
    if (b == 0) GEN ("};\n");
510 
    else GEN (",\n");
511 
  }
512 
 
513 
  GEN ("\n/* Register the bb_start */\n");
514 
  GEN ("reg   [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
515 
  GEN ("always @(posedge rst or posedge clk)\n");
516 
  GEN ("begin\n");
517 
  GEN ("  if (rst) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
518 
  GEN ("  else if (end_o) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
519 
  GEN ("  else bb_start_r <= #Tp bb_start;\n");
520 
  GEN ("end\n");
521 
 
522 
  GEN ("\n/* Logic */\n");
523 
  /* output body */
524 
  for (b = 0; b < f->num_bb; b++) {
525 
    GEN ("\t\t/* BB%i */\n", b);
526 
    for (i = 0; i < f->bb[b].ninsn; i++)
527 
      print_insn_v (fo, f, b, i);
528 
    GEN ("\n");
529 
  }
530 
 
531 
  if (co) {
532 
    GEN ("\n/* Outputs */\n");
533 
    for (i = 0; i < MAX_REGS; i++)
534 
      if (f->lur[i] >= 0 && !f->saved_regs[i])
535 
        GEN ("assign r%i_o = t%x_%x;\n", i, REF_BB(f->lur[i]),
536 
                        REF_I(f->lur[i]));
537 
  }
538 
 
539 
  if (nstores) {
540 
    int cur_store;
541 
    GEN ("\n/* Memory stores */\n");
542 
    GEN ("always @(s_stb");
543 
    for (i = 0; i < f->nmsched; i++)
544 
      if (f->mtype[i] & MT_STORE) {
545 
        char t[30];
546 
        unsigned long opt = f->INSN(f->msched[i]).opt[0];
547 
        if ((opt & ~OPT_DEST) != OPT_CONST) {
548 
          GEN (" or %s", print_op_v (f, t, f->msched[i], 0));
549 
        }
550 
      }
551 
 
552 
    cur_store = 0;
553 
    GEN (")\nbegin\n");
554 
    for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
555 
      char t[30];
556 
      GEN ("  %sif (s_stb[%i]) s_dat_o = %s;\n", cur_store == 0 ? "" : "else ", cur_store,
557 
                      print_op_v (f, t, f->msched[i], 0));
558 
      cur_store++;
559 
      //PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
560 
    }
561 
    GEN ("  else s_dat_o = 32'hx;\n");
562 
    GEN ("end\n");
563 
  }
564 
 
565 
  /* Generate load and store state machine */
566 
#if 0
567 
  GEN ("\n/* Load&store state machine */\n");
568 
  GEN ("always @(posedge clk or posedge rst)\n");
569 
  GEN ("  if (rst) begin\n");
570 
  if (nloads) GEN ("    l_stb <= #Tp %i'h0;\n", nloads);
571 
  if (nstores) GEN ("    s_stb <= #Tp %i'h0;\n", nstores);
572 
  GEN ("  end else begin\n");
573 
  for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE) {
574 
    int cur = 0;
575 
    dep_list *dep = f->INSN(f->msched[i]).dep;
576 
    assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
577 
    GEN ("    if (");
578 
    print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
579 
    GEN (") begin\n");
580 
    print_turn_off_dep (fo, f, dep);
581 
    GEN ("      %c_stb[%i] <= #Tp 1'b1;\n", f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
582 
    GEN ("    end\n");
583 
  }
584 
  GEN ("    if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
585 
  GEN ("  end\n");
586 
#endif
587 
 
588 
  /* Generate state generator machine */
589 
  for (j = 0; j < 2; j++) {
590 
    char c;
591 
    char *s;
592 
 
593 
    switch (j) {
594 
      case 0: c = 'l'; s = "Load"; break;
595 
      case 1: c = 's'; s = "Store"; break;
596 
      case 2: c = 'c'; s = "Calls"; break;
597 
    }
598 1557 nogj 
    if ((j == 0 && nloads)
599 
     || (j == 1 && nstores)
600 
     || (j == 2 && ncalls)) {
601 1244 hpanther 
      int cur = 0;
602 
      char t[30];
603 
 
604 
      GEN ("\n/* %s state generator machine */\n", s);
605 
      GEN ("always @(");
606 
      for (i = 0; i < f->nmsched; i++) {
607 
        print_op_v (f, t, f->msched[i], 1);
608 
        GEN ("%s or ", t);
609 
      }
610 
      GEN ("bb_start_r");
611 
      if (nloads) GEN (" or l_end");
612 
      if (nstores) GEN (" or s_end");
613 
      GEN (")\n");
614 
      GEN ("begin\n  ");
615 
      cucdebug (1, "%s\n", s);
616 
      for (i = 0; i < f->nmsched; i++)
617 1557 nogj 
        if ((j == 0 && f->mtype[i] & MT_LOAD)
618 
         || (j == 1 && f->mtype[i] & MT_STORE)
619 
         || (j == 2 && f->mtype[i] & MT_CALL)) {
620 1244 hpanther 
        cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
621 
        assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
622 
        GEN ("if (");
623 
        print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
624 
        GEN (") begin\n");
625 
        GEN ("    %c_req_o = 1'b1;\n", c);
626 
        GEN ("    %c_sel_o[3:0] = 4'b", c);
627 
        switch (f->mtype[i] & MT_WIDTH) {
628 
          case 1: GEN ("0001 << (%s & 32'h3);\n",
629 
                                  print_op_v (f, t, f->msched[i], 1)); break;
630 
          case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
631 
                                  print_op_v (f, t, f->msched[i], 1)); break;
632 
          case 4: GEN ("1111;\n"); break;
633 
          default: assert (0);
634 
        }
635 
        GEN ("    %c_linbrst_o = 1'b%i;\n", c,
636 
                      (f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
637 1308 phoenix 
        GEN ("    %c_adr_o = t%lx_%lx & ~32'h3;\n", c,
638 1244 hpanther 
                      REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
639 
        GEN ("  end else ");
640 
      }
641 
      GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
642 
      GEN ("    %c_req_o = 1'b0;\n", c);
643 
      GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
644 
      GEN ("    %c_linbrst_o = 1'b0;\n", c);
645 
      GEN ("    %c_adr_o = 32'hx;\n", c);
646 
      GEN ("  end else begin\n");
647 
      GEN ("    %c_req_o = 1'b0;\n", c);
648 
      GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
649 
      GEN ("    %c_linbrst_o = 1'b0;\n", c);
650 
      GEN ("    %c_adr_o = 32'hx;\n", c);
651 
      GEN ("  end\n");
652 
      GEN ("end\n");
653 
    }
654 
  }
655 
 
656 
  if (ncalls) {
657 
    int cur_call = 0;
658 
    GEN ("\n/* Function calls state machine */\n");
659 
    GEN ("always @(posedge clk or posedge rst)\n");
660 
    GEN ("begin\n");
661 
    GEN ("  if (rst) begin\n");
662 
    GEN ("    f_stb <= #Tp %i'h0;\n", nstores);
663 
    for (i = 0; i < 6; i++) GEN ("    fr%i_o <= #Tp 32'h0;\n", i + 3);
664 
    if (log2_int(ncalls)) GEN ("    fid_o <= #Tp %i'h0;\n", log2_int (f->nfdeps));
665 
    GEN ("    fstart_o <= #Tp 1'b0;\n");
666 
    //GEN ("    f11_r <= #Tp 32'h0;\n");
667 
    GEN ("  end else begin\n");
668 
    cucdebug (1, "calls \n");
669 
    for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_CALL) {
670 
      dep_list *dep = f->INSN(f->msched[i]).dep;
671 
      cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
672 
      assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
673 
      GEN ("    if (");
674 
      print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
675 
      GEN (") begin\n");
676 
      print_turn_off_dep (fo, f, dep);
677 
      GEN ("      f_stb[%i] <= #Tp 1'b1;\n", cur_call++);
678 
      GEN ("      fstart_o <= #Tp 1'b1;\n");
679 
      if (log2_int (f->nfdeps))
680 
        GEN ("      fid_o <= #Tp %i'h%x;\n", log2_int (f->nfdeps), func_index (f, f->msched[i]));
681 
 
682 
      for (j = 0; j < 6; j++)
683 
        GEN ("      fr%i_o <= #Tp t%x_%x;\n", j + 3,
684 
                       REF_BB (f->msched[i]), REF_I (f->msched[i]) - 6 + i);
685 
      GEN ("    end\n");
686 
    }
687 
    GEN ("    if (f_end[%i]) begin\n", ncalls - 1);
688 
    GEN ("      f_stb <= #Tp %i'h0;\n", ncalls);
689 
    GEN ("      f_start_o <= #Tp 1'b0;\n");
690 
    GEN ("    end\n");
691 
    GEN ("  end\n");
692 
    GEN ("end\n");
693 
  }
694 
 
695 
  GEN ("\n/* Basic blocks state machine */\n");
696 
  GEN ("always @(posedge clk or posedge rst)\n");
697 
  GEN ("begin\n");
698 
  GEN ("  if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
699 
  GEN ("  else if (end_o) begin\n");
700 
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
701 
  for (i = 0; i < f->num_bb; i++) {
702 
    GEN ("  end else if (bb_start[%i]) begin\n", i);
703 
    GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
704 
  }
705 
  GEN ("  end else if (end_o) begin\n");
706 
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
707 
  GEN ("  end\n");
708 
  GEN ("end\n");
709 
 
710 
  /* output footer */
711 
  GEN ("\nendmodule\n");
712 
 
713 
  fclose (fo);
714 
}
715 
 
716 
void generate_main (int nfuncs, cuc_func **f, char *filename)
717 
{
718 
  FILE *fo;
719 
  int i, j, nrf, first;
720 
  char tmp[256];
721 
  int ncallees[MAX_FUNCS];
722 
  int nl[MAX_FUNCS], ns[MAX_FUNCS];
723 
  int maxncallees = 0;
724 
  sprintf (tmp, "%s_top.v", filename);
725 
 
726 
  for (i = 0, nrf = 0; i < nfuncs; i++) {
727 
    nl[i] = ns[i] = 0;
728 
    ncallees[i] = 0;
729 
    if (f[i]) {
730 
      f[i]->tmp = nrf++;
731 
      for (j = 0; j < f[i]->nmsched; j++)
732 
        if (f[i]->mtype[j] & MT_LOAD) nl[i]++;
733 
        else if (f[i]->mtype[j] & MT_STORE) ns[i]++;
734 
      for (j = 0; j < f[i]->nfdeps; j++)
735 
        ncallees[f[i]->fdeps[j]->tmp]++;
736 
    }
737 
  }
738 
  if (!nrf) return;
739 
 
740 
  for (i = 0; i < nrf; i++)
741 
    if (maxncallees < ncallees[i]) maxncallees = ncallees[i];
742 
 
743 
  log ("Generating verilog file \"%s\"\n", tmp);
744 
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
745 
  if ((fo = fopen (tmp, "wt+")) == NULL) {
746 
    fprintf (stderr, "Cannot open '%s'\n", tmp);
747 
    exit (1);
748 
  }
749 
 
750 
  /* output header */
751 
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
752 
  GEN ("   (C) 2002 Opencores */\n\n");
753 
  GEN ("/* Includes %i functions:", nrf);
754 
  for (i = 0; i < nfuncs; i++) if (f[i])
755 
    GEN ("\n%s", prof_func[i].name);
756 
  GEN (" */\n\n");
757 
 
758 
  GEN ("`include \"timescale.v\"\n\n");
759 
  GEN ("module %s (clk, rst,\n", filename);
760 
  GEN ("              /* Load and store master Wishbone ports */\n");
761 
  GEN ("              l_adr_o, l_dat_i, l_cyc_o, l_stb_o,\n");
762 
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i, l_we_o,\n");
763 
  GEN ("              s_adr_o, s_dat_o, s_cyc_o, s_stb_o,\n");
764 
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i, s_we_o,\n\n");
765 
  GEN ("              /* cuc interface */\n");
766 
  GEN ("              cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_rdy_o);\n\n");
767 
 
768 
  GEN ("parameter Tp = 1;\n");
769 
  GEN ("\n/* module ports */\n");
770 
  GEN ("input         clk, rst, cuc_stb_i, cuc_we_i;\n");
771 
  GEN ("input         l_rdy_i, s_rdy_i;\n");
772 
  GEN ("output        l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
773 
  GEN ("reg           l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
774 
  GEN ("output        s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
775 
  GEN ("reg           s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
776 
  GEN ("output        cuc_rdy_o; /* Not registered ! */\n");
777 
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
778 
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
779 
  GEN ("output [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
780 
  GEN ("reg    [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
781 
  GEN ("input  [15:0] cuc_adr_i;\n");
782 
  GEN ("input  [31:0] l_dat_i, cuc_dat_i;\n\n");
783 
 
784 
  GEN ("wire   [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n", nrf - 1);
785 
  GEN ("wire   [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n", nrf - 1);
786 
  GEN ("wire   [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
787 
  GEN ("wire   [%2i:0] i_l_req, i_s_req;\n", nrf - 1);
788 
  GEN ("reg    [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
789 
 
790 
  GEN ("assign i_selected = {\n");
791 
  for (i = 0; i < nrf; i++)
792 
    GEN ("    cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
793 
 
794 
  GEN ("assign i_first_reg = {\n");
795 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
796 
    for (j = 0; j <= MAX_REGS; j++) if (f[i]->used_regs[j]) break;
797 
    GEN ("    cuc_adr_i[5:0] == %i%s\n", j, f[i]->tmp < nrf - 1 ? "," : "};");
798 
  }
799 
 
800 
  GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
801 
  GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
802 
 
803 
  GEN ("assign i_start = i_go_bsy & {%i{cuc_rdy_o}};\n", nrf);
804 
  GEN ("assign i_start_bidok = {\n");
805 
  for (i = 0; i < nrf; i++)
806 
    GEN ("    i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
807 
  GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
808 
  GEN ("assign main_end = {%i{i_end}} & i_selected;\n");
809 
 
810 
  GEN ("\nalways @(posedge clk or posedge rst)\n");
811 
  GEN ("begin\n");
812 
  GEN ("  if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
813 
  GEN ("  else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
814 
  GEN ("end\n");
815 
 
816 
 
817 
  /* Function specific data */
818 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
819 
    int ci = 0, co = 0;
820 
    int fn = f[i]->tmp;
821 
    GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
822 
    for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j]) {
823 
      GEN ("%s i%i_r%ii", first ? "/* inputs */\nreg    [31:0]" : ",", fn, j);
824 
      first = 0;
825 
      ci++;
826 
    }
827 
    if (ci) GEN (";\n");
828 
 
829 
    for (j = 0, first = 1; j < MAX_REGS; j++)
830 
      if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
831 
        GEN ("%s i%i_r%io", first ? "/* outputs */\nwire   [31:0]" : ",", fn, j);
832 
        first = 0;
833 
        co++;
834 
      }
835 
    if (co) GEN (";\n");
836 
    GEN ("wire [31:0] i%i_l_adr, i%i_s_adr;\n", fn, fn);
837 
 
838 
    GEN ("always @(posedge clk or posedge rst)\n");
839 
    GEN ("  if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
840 
    GEN ("  else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
841 
 
842 
    if (ci) {
843 
      GEN ("\n/* write register access */\n");
844 
      GEN ("always @(posedge clk or posedge rst)\n");
845 
      GEN ("begin\n");
846 
      GEN ("  if (rst) begin\n");
847 
      for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
848 
        GEN ("    i%i_r%ii <= #Tp 32'h0;\n", fn, j);
849 
      GEN ("  end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
850 
      GEN ("    case (cuc_adr_i[5:0])\n");
851 
      for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
852 
        GEN ("      %-2i: i%i_r%ii <= #Tp cuc_dat_i;\n", j, fn, j);
853 
      GEN ("    endcase\n");
854 
      GEN ("end\n");
855 
    }
856 
 
857 
    GEN ("\n");
858 
  }
859 
 
860 
  /* Generate machine for reading all function registers. Register read can be
861 
     delayed till function completion */
862 
  {
863 
    int co;
864 
    GEN ("/* read register access - data */\n");
865 
    GEN ("always @(posedge clk or posedge rst)\n");
866 
    GEN ("  if (rst) cuc_dat_o <= #Tp 32'h0;\n");
867 
    GEN ("  else if (cuc_stb_i && cuc_we_i) begin\n");
868 
    GEN ("    ");
869 
 
870 
    for (i = 0; i < nfuncs; i++) if (f[i]) {
871 
      co = 0;
872 
      for (j = 0; j < MAX_REGS; j++)
873 
        if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
874 
 
875 
      GEN ("if (cuc_adr_i[15:6] == %i)", f[i]->tmp);
876 
      if (co) {
877 
        first = 1;
878 
        GEN ("\n      case (cuc_adr_i[5:0])\n");
879 
        for (j = 0; j < MAX_REGS; j++)
880 
          if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
881 
            GEN ("        %-2i: cuc_dat_o <= #Tp i%i_r%io;\n", j, f[i]->tmp, j);
882 
        GEN ("      endcase\n");
883 
      } else {
884 
        GEN ("      cuc_dat_o <= #Tp 32'hx;\n");
885 
      }
886 
      GEN ("    else ");
887 
    }
888 
    GEN ("cuc_dat_o <= #Tp 32'hx;\n");
889 
    GEN ("  end else cuc_dat_o <= #Tp 32'hx;\n");
890 
 
891 
    GEN ("\n/* read register access - acknowledge */\n");
892 
    GEN ("assign cuc_rdy_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
893 
  }
894 
 
895 
  /* Store/load Wishbone bridge */
896 
  for (j = 0; j < 2; j++) {
897 
    char t = j ? 's' : 'l';
898 
    GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
899 
    GEN ("reg [%i:0] %cm_sel;\n", log2_int (nrf), t);
900 
    GEN ("reg [%i:0] %cm_bid;\n", log2_int (nrf), t);
901 
    GEN ("reg       %ccyc_ip;\n\n", t);
902 
    GEN ("always @(posedge clk)\n");
903 
    GEN ("begin\n");
904 
    GEN ("  %c_we_o <= #Tp 1'b%i;\n", t, j);
905 
    GEN ("  %c_cyc_o <= #Tp |i_%c_req;\n", t, t);
906 
    GEN ("  %c_stb_o <= #Tp |i_%c_req;\n", t, t);
907 
    GEN ("end\n");
908 
 
909 
    GEN ("\n/* highest bid */\n");
910 
    GEN ("always @(");
911 
    for (i = 0; i < nrf; i++) GEN ("%si_%c_req", i > 0 ? " or " : "", t);
912 
    GEN (")\n");
913 
    for (i = 0; i < nrf; i++) GEN ("  %sif (i_%c_req) %cm_bid = %i'h%x;\n",
914 
                    i ? "else " : "", t, t, log2_int (nrf) + 1, i);
915 
 
916 
    GEN ("\n/* selected transfer */\n");
917 
    GEN ("always @(posedge clk or posedge rst)\n");
918 
    GEN ("  if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2_int (nrf) + 1);
919 
    GEN ("  else if (%c_rdy_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2_int (nrf) + 1);
920 
    GEN ("  else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
921 
 
922 
    GEN ("\n/* Cycle */\n");
923 
    GEN ("\nalways @(posedge clk or posedge rst)\n");
924 
    GEN ("  if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
925 
    GEN ("  else if (%c_rdy_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
926 
    GEN ("  else %ccyc_ip <= #Tp %c_cyc_o;\n", t, t);
927 
  }
928 
 
929 
  GEN ("\n/* Acknowledge */\n");
930 
  for (i = 0; i < nrf; i++) {
931 
    GEN ("wire i%i_s_rdy = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & s_rdy_i;\n", i, i, i);
932 
    GEN ("wire i%i_l_rdy = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & l_rdy_i;\n", i, i, i);
933 
  }
934 
 
935 
  GEN ("\n/* data, address selects and burst enables */\n");
936 
  for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_s_dat;\n", i);
937 
  for (i = 0; i < nrf; i++) GEN ("wire i%i_s_linbrst, i%i_l_linbrst;\n", i, i);
938 
  for (i = 0; i < nrf; i++) GEN ("wire [3:0]  i%i_s_sel, i%i_l_sel;\n", i, i);
939 
  for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_l_dat = l_dat_i;\n", i);
940 
  GEN ("\nalways @(posedge clk)\n");
941 
  GEN ("begin\n");
942 
  GEN ("  s_dat_o <= #Tp ");
943 
  for (i = 0; i < nrf - 1; i++)
944 
    GEN ("\n    sm_bid == %i ? i%i_s_dat : ", i, i);
945 
  GEN ("i%i_s_dat;\n", nrf - 1);
946 
  GEN ("  s_adr_o <= #Tp ");
947 
  for (i = 0; i < nrf - 1; i++)
948 
    GEN ("\n    sm_bid == %i ? i%i_s_adr : ", i, i);
949 
  GEN ("i%i_s_adr;\n", nrf - 1);
950 
  GEN ("  s_sel_o <= #Tp ");
951 
  for (i = 0; i < nrf - 1; i++)
952 
    GEN ("\n    sm_bid == %i ? i%i_s_sel : ", i, i);
953 
  GEN ("i%i_s_sel;\n", nrf - 1);
954 
  GEN ("  s_linbrst_o <= #Tp ");
955 
  for (i = 0; i < nrf - 1; i++)
956 
    GEN ("\n    sm_bid == %i ? i%i_s_linbrst : ", i, i);
957 
  GEN ("i%i_s_linbrst;\n", nrf - 1);
958 
  GEN ("end\n\n");
959 
 
960 
  GEN ("always @(posedge clk)\n");
961 
  GEN ("begin\n");
962 
  GEN ("  l_adr_o <= #Tp ");
963 
  for (i = 0; i < nrf - 1; i++)
964 
    GEN ("\n    lm_bid == %i ? i%i_l_adr : ", i, i);
965 
  GEN ("i%i_l_adr;\n", nrf - 1);
966 
  GEN ("  l_sel_o <= #Tp ");
967 
  for (i = 0; i < nrf - 1; i++)
968 
    GEN ("\n    lm_bid == %i ? i%i_l_sel : ", i, i);
969 
  GEN ("i%i_l_sel;\n", nrf - 1);
970 
  GEN ("  l_linbrst_o <= #Tp ");
971 
  for (i = 0; i < nrf - 1; i++)
972 
    GEN ("\n    lm_bid == %i ? i%i_l_linbrst : ", i, i);
973 
  GEN ("i%i_l_linbrst;\n", nrf - 1);
974 
  GEN ("end\n\n");
975 
 
976 
  /* start/end signals */
977 
  GEN ("\n\n/* start/end signals */\n");
978 
  for (i = 0; i < nrf; i++) {
979 
    if (log2_int (maxncallees + 1))
980 
      GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
981 1557 nogj 
        log2_int (maxncallees + 1), i, i, i, i);
982 1244 hpanther 
    else GEN ("wire i%i_current = 0;\n", i);
983 
  }
984 
  GEN ("\n");
985 
 
986 
  for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
987 
    if (log2_int (ncallees[i])) {
988 
      GEN ("reg [%i:0] i%i_start_bid;\n", log2_int (ncallees[i]), j);
989 
      GEN ("always @(start%i", f[i]->tmp);
990 
      for (j = 0, first = 1; j < f[i]->nfdeps; j++)
991 
        if (f[i]->fdeps[j]) GEN (", ");
992 
      GEN (")\n");
993 
      GEN ("begin !!!\n"); //TODO
994 
      GEN ("  \n");
995 
      GEN ("end\n");
996 
    }
997 
    GEN ("wire i%i_start = main_start[%i];\n", j, j);
998 
    j++;
999 
  }
1000 
  GEN ("\n");
1001 
 
1002 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
1003 
    int nf = f[i]->tmp;
1004 
    GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename, prof_func[i].name, nf);
1005 
    GEN ("  .l_adr_o(i%i_l_adr), .l_dat_i(i%i_l_dat), .l_req_o(i_l_req[%i]),\n",
1006 
                    nf, nf, nf);
1007 
    GEN ("  .l_sel_o(i%i_l_sel), .l_linbrst_o(i%i_l_linbrst), .l_rdy_i(i%i_l_rdy),\n",
1008 
                    nf, nf, nf);
1009 
    GEN ("  .s_adr_o(i%i_s_adr), .s_dat_o(i%i_s_dat), .s_req_o(i_s_req[%i]),\n",
1010 
                    nf, nf, nf);
1011 
    GEN ("  .s_sel_o(i%i_s_sel), .s_linbrst_o(i%i_s_linbrst), .s_rdy_i(i%i_s_rdy),\n",
1012 
                    nf, nf, nf);
1013 
    GEN ("  ");
1014 
    for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
1015 
      GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
1016 
 
1017 
    if (first) GEN ("\n  ");
1018 
    for (j = 0, first = 1; j < MAX_REGS; j++)
1019 
      if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
1020 
        GEN (".r%i_o(i%i_r%io), ", j, nf, j), first = 0;
1021 
    if (first) GEN ("\n  ");
1022 
    if (f[i]->nfdeps) {
1023 
      GEN (".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n", i, i, i),
1024 
      GEN ("  .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n");
1025 
      GEN ("  .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n  ");
1026 
    }
1027 
    GEN (".start_i(i_start[%i]), .end_o(i_end[%i]), .busy_o(i_busy[%i]));\n", nf, nf, nf);
1028 
  }
1029 
 
1030 
  /* output footer */
1031 
  GEN ("\nendmodule\n");
1032 
 
1033 
  fclose (fo);
1034 
}
1035 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.