1 |
31 |
lampret |
/* 16450.h -- Definition of types and structures for 8250/16450 serial UART
|
2 |
|
|
Copyright (C) 2000 Damjan Lampret, lampret@opencores.org
|
3 |
|
|
|
4 |
|
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
5 |
|
|
|
6 |
|
|
This program is free software; you can redistribute it and/or modify
|
7 |
|
|
it under the terms of the GNU General Public License as published by
|
8 |
|
|
the Free Software Foundation; either version 2 of the License, or
|
9 |
|
|
(at your option) any later version.
|
10 |
|
|
|
11 |
|
|
This program is distributed in the hope that it will be useful,
|
12 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
14 |
|
|
GNU General Public License for more details.
|
15 |
|
|
|
16 |
|
|
You should have received a copy of the GNU General Public License
|
17 |
|
|
along with this program; if not, write to the Free Software
|
18 |
|
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
19 |
|
|
|
20 |
|
|
/* Prototypes */
|
21 |
|
|
void uart_reset();
|
22 |
|
|
void uart_clock();
|
23 |
|
|
|
24 |
341 |
markom |
/* Definitions */
|
25 |
355 |
markom |
#define UART_ADDR_SPACE (8) /* UART memory address space size in bytes */
|
26 |
341 |
markom |
#define UART_MAX_FIFO_LEN (16) /* rx FIFO for uart 16550 */
|
27 |
355 |
markom |
#define MAX_SKEW (1) /* max. clock skew in subclocks */
|
28 |
409 |
markom |
#define UART_VAPI_BUF_LEN 128 /* Size of VAPI command buffer - VAPI should not send more
|
29 |
|
|
that this amout of char before requesting something back */
|
30 |
|
|
#define UART_CLOCK_DIVIDER 16 /* Uart clock divider */
|
31 |
341 |
markom |
|
32 |
31 |
lampret |
/* Registers */
|
33 |
|
|
|
34 |
|
|
struct dev_16450 {
|
35 |
355 |
markom |
struct {
|
36 |
411 |
markom |
unsigned txbuf[UART_MAX_FIFO_LEN];
|
37 |
|
|
unsigned rxbuf[UART_MAX_FIFO_LEN];
|
38 |
355 |
markom |
unsigned char dll;
|
39 |
|
|
unsigned char dlh;
|
40 |
|
|
unsigned char ier;
|
41 |
|
|
unsigned char iir;
|
42 |
409 |
markom |
unsigned char fcr;
|
43 |
355 |
markom |
unsigned char lcr;
|
44 |
|
|
unsigned char mcr;
|
45 |
|
|
unsigned char lsr;
|
46 |
|
|
unsigned char msr;
|
47 |
|
|
unsigned char scr;
|
48 |
|
|
} regs; /* Visible registers */
|
49 |
|
|
struct {
|
50 |
|
|
unsigned long txser; /* Character just sending */
|
51 |
|
|
unsigned long rxser; /* Character just receiving */
|
52 |
|
|
unsigned char loopback;
|
53 |
|
|
} iregs; /* Internal registers */
|
54 |
|
|
struct {
|
55 |
|
|
int txbuf_head;
|
56 |
|
|
int txbuf_tail;
|
57 |
|
|
int rxbuf_head;
|
58 |
|
|
int rxbuf_tail;
|
59 |
|
|
unsigned int txser_full;
|
60 |
|
|
unsigned int rxser_full;
|
61 |
|
|
unsigned int txbuf_full;
|
62 |
|
|
unsigned int rxbuf_full;
|
63 |
409 |
markom |
unsigned thre_int;
|
64 |
|
|
unsigned break_set;
|
65 |
355 |
markom |
unsigned long txser_clks;
|
66 |
|
|
unsigned long rxser_clks;
|
67 |
409 |
markom |
unsigned timeout_count;
|
68 |
355 |
markom |
} istat; /* Internal status */
|
69 |
341 |
markom |
|
70 |
355 |
markom |
/* Clocks per char */
|
71 |
|
|
unsigned long char_clks;
|
72 |
341 |
markom |
|
73 |
355 |
markom |
/* VAPI internal registers */
|
74 |
|
|
struct {
|
75 |
|
|
unsigned long char_clks;
|
76 |
|
|
int dll, dlh;
|
77 |
|
|
int lcr;
|
78 |
|
|
int skew;
|
79 |
385 |
markom |
int next_break;
|
80 |
|
|
int next_break_cnt;
|
81 |
|
|
int cur_break;
|
82 |
|
|
int cur_break_cnt;
|
83 |
409 |
markom |
int break_sent;
|
84 |
355 |
markom |
} vapi;
|
85 |
|
|
|
86 |
|
|
/* Required by VAPI - circular buffer */
|
87 |
409 |
markom |
unsigned long vapi_buf[UART_VAPI_BUF_LEN]; /* Buffer to store incoming characters to,
|
88 |
355 |
markom |
since we cannot handle them so fast - we
|
89 |
|
|
are serial */
|
90 |
341 |
markom |
int vapi_buf_head_ptr; /* Where we write to */
|
91 |
|
|
int vapi_buf_tail_ptr; /* Where we read from */
|
92 |
|
|
|
93 |
|
|
/* Length of FIFO, 16 for 16550, 1 for 16450 */
|
94 |
|
|
int fifo_len;
|
95 |
355 |
markom |
|
96 |
|
|
/* Required by standard file streams */
|
97 |
|
|
FILE * rxfs;
|
98 |
|
|
FILE * txfs;
|
99 |
31 |
lampret |
};
|
100 |
|
|
|
101 |
|
|
/*
|
102 |
|
|
* Addresses of visible registers
|
103 |
|
|
*
|
104 |
|
|
*/
|
105 |
355 |
markom |
#define UART_RXBUF 0 /* R: Rx buffer, DLAB=0 */
|
106 |
|
|
#define UART_TXBUF 0 /* W: Tx buffer, DLAB=0 */
|
107 |
|
|
#define UART_DLL 0 /* R/W: Divisor Latch Low, DLAB=1 */
|
108 |
|
|
#define UART_DLH 1 /* R/W: Divisor Latch High, DLAB=1 */
|
109 |
|
|
#define UART_IER 1 /* R/W: Interrupt Enable Register */
|
110 |
|
|
#define UART_IIR 2 /* R: Interrupt ID Register */
|
111 |
409 |
markom |
#define UART_FCR 2 /* W: FIFO Control Register */
|
112 |
355 |
markom |
#define UART_LCR 3 /* R/W: Line Control Register */
|
113 |
|
|
#define UART_MCR 4 /* W: Modem Control Register */
|
114 |
|
|
#define UART_LSR 5 /* R: Line Status Register */
|
115 |
|
|
#define UART_MSR 6 /* R: Modem Status Register */
|
116 |
|
|
#define UART_SCR 7 /* R/W: Scratch Register */
|
117 |
31 |
lampret |
|
118 |
|
|
/*
|
119 |
|
|
* R/W masks for valid bits in 8250/16450 (mask out 16550 and later bits)
|
120 |
|
|
*
|
121 |
|
|
*/
|
122 |
355 |
markom |
#define UART_VALID_LCR 0xff
|
123 |
409 |
markom |
#define UART_VALID_LSR 0xff
|
124 |
|
|
#define UART_VALID_IIR 0x0f
|
125 |
|
|
#define UART_VALID_FCR 0xc0
|
126 |
355 |
markom |
#define UART_VALID_IER 0x0f
|
127 |
|
|
#define UART_VALID_MCR 0x1f
|
128 |
|
|
#define UART_VALID_MSR 0xff
|
129 |
31 |
lampret |
|
130 |
|
|
/*
|
131 |
|
|
* Bit definitions for the Line Control Register
|
132 |
|
|
*
|
133 |
|
|
*/
|
134 |
355 |
markom |
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
135 |
|
|
#define UART_LCR_SBC 0x40 /* Set break control */
|
136 |
|
|
#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
|
137 |
|
|
#define UART_LCR_EPAR 0x10 /* Even parity select */
|
138 |
|
|
#define UART_LCR_PARITY 0x08 /* Parity Enable */
|
139 |
|
|
#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
|
140 |
|
|
#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
|
141 |
|
|
#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
|
142 |
|
|
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
|
143 |
|
|
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
|
144 |
344 |
markom |
#define UART_LCR_RESET 0x03
|
145 |
31 |
lampret |
/*
|
146 |
|
|
* Bit definitions for the Line Status Register
|
147 |
|
|
*/
|
148 |
409 |
markom |
#define UART_LSR_RXERR 0x80 /* Error in rx fifo */
|
149 |
355 |
markom |
#define UART_LSR_TXSERE 0x40 /* Transmitter serial register empty */
|
150 |
|
|
#define UART_LSR_TXBUFE 0x20 /* Transmitter buffer register empty */
|
151 |
|
|
#define UART_LSR_BREAK 0x10 /* Break interrupt indicator */
|
152 |
|
|
#define UART_LSR_FRAME 0x08 /* Frame error indicator */
|
153 |
|
|
#define UART_LSR_PARITY 0x04 /* Parity error indicator */
|
154 |
|
|
#define UART_LSR_OVRRUN 0x02 /* Overrun error indicator */
|
155 |
|
|
#define UART_LSR_RDRDY 0x01 /* Receiver data ready */
|
156 |
31 |
lampret |
|
157 |
|
|
/*
|
158 |
|
|
* Bit definitions for the Interrupt Identification Register
|
159 |
|
|
*/
|
160 |
355 |
markom |
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
|
161 |
|
|
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
|
162 |
31 |
lampret |
|
163 |
355 |
markom |
#define UART_IIR_MSI 0x00 /* Modem status interrupt (Low priority) */
|
164 |
|
|
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
|
165 |
|
|
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
|
166 |
|
|
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt (High p.) */
|
167 |
409 |
markom |
#define UART_IIR_CTI 0x0c /* Character timeout */
|
168 |
31 |
lampret |
|
169 |
|
|
/*
|
170 |
409 |
markom |
* Bit Definitions for the FIFO Control Register
|
171 |
|
|
*/
|
172 |
|
|
#define UART_FCR_FIE 0x01 /* FIFO enable */
|
173 |
|
|
#define UART_FCR_RRXFI 0x02 /* Reset rx FIFO */
|
174 |
411 |
markom |
#define UART_FCR_RTXFI 0x04 /* Reset tx FIFO */
|
175 |
409 |
markom |
#define UART_FIFO_TRIGGER(x) /* Trigger values for indexes 0..3 */\
|
176 |
423 |
markom |
((x) == 0 ? 1\
|
177 |
|
|
:(x) == 1 ? 4\
|
178 |
|
|
:(x) == 2 ? 8\
|
179 |
|
|
:(x) == 3 ? 14 : 0)
|
180 |
409 |
markom |
|
181 |
|
|
/*
|
182 |
31 |
lampret |
* Bit definitions for the Interrupt Enable Register
|
183 |
|
|
*/
|
184 |
355 |
markom |
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
|
185 |
|
|
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
|
186 |
|
|
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
|
187 |
|
|
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
|
188 |
31 |
lampret |
|
189 |
|
|
/*
|
190 |
|
|
* Bit definitions for the Modem Control Register
|
191 |
|
|
*/
|
192 |
355 |
markom |
#define UART_MCR_LOOP 0x10 /* Enable loopback mode */
|
193 |
|
|
#define UART_MCR_AUX2 0x08 /* Auxilary 2 */
|
194 |
|
|
#define UART_MCR_AUX1 0x04 /* Auxilary 1 */
|
195 |
|
|
#define UART_MCR_RTS 0x02 /* Force RTS */
|
196 |
|
|
#define UART_MCR_DTR 0x01 /* Force DTR */
|
197 |
31 |
lampret |
|
198 |
|
|
/*
|
199 |
|
|
* Bit definitions for the Modem Status Register
|
200 |
|
|
*/
|
201 |
355 |
markom |
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
|
202 |
385 |
markom |
#define UART_MSR_RI 0x40 /* Ring Indicator */
|
203 |
355 |
markom |
#define UART_MSR_DSR 0x20 /* Data Set Ready */
|
204 |
|
|
#define UART_MSR_CTS 0x10 /* Clear to Send */
|
205 |
|
|
#define UART_MSR_DDCD 0x08 /* Delta DCD */
|
206 |
|
|
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
|
207 |
|
|
#define UART_MSR_DDSR 0x02 /* Delta DSR */
|
208 |
|
|
#define UART_MSR_DCTS 0x01 /* Delta CTS */
|
209 |
31 |
lampret |
|
210 |
385 |
markom |
/*
|
211 |
|
|
* Various definitions
|
212 |
|
|
*/
|
213 |
423 |
markom |
#define UART_BREAK_COUNT (1) /* # of chars to count when performing break */
|
214 |
409 |
markom |
#define UART_CHAR_TIMEOUT (4) /* # of chars to count when performing timeout int. */
|