OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [peripheral/] [atadevice.h] - Blame information for rev 1488

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 876 rherveille
/*
2
    atahost.h -- ATA Host code simulation
3
    Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
4
 
5
    This file is part of OpenRISC 1000 Architectural Simulator
6
 
7
    This program is free software; you can redistribute it and/or modify
8
    it under the terms of the GNU General Public License as published by
9
    the Free Software Foundation; either version 2 of the License, or
10
    (at your option) any later version
11
 
12
    This program is distributed in the hope that it will be useful,
13
    but WITHOUT ANY WARRANTY; without even the implied warranty of
14
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
    GNU General Public License for more details.
16
 
17
    You should have received a copy of the GNU General Public License
18
    along with this program; if not, write to the Free Software
19
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
*/
21
 
22
/*
23
 * Definitions for the Opencores ATA Controller Core, Device model
24
 */
25
 
26
#ifndef __OR1KSIM_ATAD_H
27
#define __OR1KSIM_ATAD_H
28
 
29
#include <stdio.h>
30
 
31
/* --- Register definitions --- */
32
/* ----- ATA Registers                                                */
33
/* These are actually the memory locations where the ATA registers    */
34
/* can be found in the host system; i.e. as seen from the CPU.        */
35
/* However, this doesn't matter for the simulator.                    */
36
#define ATA_ASR   0x78         /* Alternate Status Register      (R)  */
37
#define ATA_CR    0x5c         /* Command Register               (W)  */
38
#define ATA_CHR   0x54         /* Cylinder High Register       (R/W)  */
39
#define ATA_CLR   0x50         /* Cylinder Low Register        (R/W)  */
40
#define ATA_DR    0x40         /* Data Register                       */
41
#define ATA_DCR   0x78         /* Device Control Register        (W)  */
42
#define ATA_DHR   0x58         /* Device/Head Register         (R/W)  */
43
#define ATA_ERR   0x44         /* Error Register                 (R)  */
44
#define ATA_FR    0x44         /* Features Register              (W)  */
45
#define ATA_SCR   0x48         /* Sector Count Register        (R/W)  */
46
#define ATA_SNR   0x4c         /* Sector Number Register       (R/W)  */
47
#define ATA_SR    0x5c         /* Status Register                (R)  */
48
#define ATA_DA    0x7c         /* Device Address Register        (R)  */
49
             /* ATA/ATAPI-5 does not describe Device Status Register  */
50
 
51
/* --------------------------------------                             */
52
/* ----- ATA Device bit defenitions -----                             */
53
/* --------------------------------------                             */
54
 
55
/* ----- ATA (Alternate) Status Register                              */
56
#define ATA_SR_BSY  0x80        /* Busy                               */
57
#define ATA_SR_DRDY 0x40        /* Device Ready                       */
58
#define ATA_SR_DF   0x20        /* Device Fault                       */
59
#define ATA_SR_DSC  0x10        /* Device Seek Complete               */
60
#define ATA_SR_DRQ  0x08        /* Data Request                       */
61
#define ATA_SR_COR  0x04        /* Corrected data (obsolete)          */
62
#define ATA_SR_IDX  0x02        /*                (obsolete)          */
63
#define ATA_SR_ERR  0x01        /* Error                              */
64
 
65
/* ----- ATA Device Control Register                                  */
66
                                /* bits 7-3 are reserved              */
67
#define ATA_DCR_RST 0x04        /* Software reset   (RST=1, reset)    */
68
#define ATA_DCR_IEN 0x02        /* Interrupt Enable (IEN=0, enabled)  */
69
                                /* always write a '0' to bit0         */
70
 
71
/* ----- ATA Device Address Register                                  */
72
/* All values in this register are one's complement (i.e. inverted)   */
73
#define ATA_DAR_WTG 0x40        /* Write Gate                         */
74
#define ATA_DAR_H   0x3c        /* Head Select                        */
75
#define ATA_DAR_DS1 0x02        /* Drive select 1                     */
76
#define ATA_DAR_DS0 0x01        /* Drive select 0                     */
77
 
78
/* ----- Device/Head Register                                         */
79
#define ATA_DHR_LBA 0x40        /* LBA/CHS mode ('1'=LBA mode)        */
80
#define ATA_DHR_DEV 0x10        /* Device       ('0'=dev0, '1'=dev1)  */
81
#define ATA_DHR_H   0x0f        /* Head Select                        */
82
 
83
/* ----- Error Register                                               */
84
#define ATA_ERR_BBK  0x80       /* Bad Block                          */
85
#define ATA_ERR_UNC  0x40       /* Uncorrectable Data Error           */
86
#define ATA_ERR_IDNF 0x10       /* ID Not Found                       */
87
#define ATA_ERR_ABT  0x04       /* Aborted Command                    */
88
#define ATA_ERR_TON  0x02       /* Track0 Not Found                   */
89
#define ATA_ERR_AMN  0x01       /* Address Mark Not Found             */
90
 
91
/* --------------------------                                         */
92
/* ----- Device Defines -----                                         */
93
/* --------------------------                                         */
94
 
95
/* types for hard disk simulation                                     */
96
#define TYPE_NO_CONNECT 0
97
#define TYPE_FILE       1
98
#define TYPE_LOCAL      2
99
 
100
 
101
/* -----------------------------                                      */
102
/* ----- Statemachine defines --                                      */
103
/* -----------------------------                                      */
104
#define ATA_STATE_IDLE   0x00
105
#define ATA_STATE_SW_RST 0x01
106
#define ATA_STATE_HW_RST 0x02
107
 
108
 
109
/* ----------------------------                                       */
110
/* ----- Structs          -----                                       */
111
/* ----------------------------                                       */
112
typedef struct{
113
 
114
        /******* Housekeeping *****************************************/
115
        struct {
116
                /* device number                                      */
117
                int dev;
118
 
119
                /* current PIO mode                                   */
120
                int pio_mode;
121
 
122
                /* current DMA mode                                   */
123
                int dma_mode;
124
 
125
                /* databuffer                                         */
126 919 rherveille
                unsigned short dbuf[4096];
127 1067 rherveille
                unsigned short *dbuf_ptr;
128 919 rherveille
                unsigned short dbuf_cnt;
129 876 rherveille
 
130
                /* current statemachine state                         */
131
                int state;
132
 
133
                /* current CHS translation settings                   */
134
                unsigned int heads_per_cylinder;
135
                unsigned int sectors_per_track;
136 1067 rherveille
        } internals;
137 876 rherveille
 
138
 
139
        /******* ATA Device Registers *********************************/
140
        struct {
141
                unsigned char command;
142
                unsigned char cylinder_low;
143
                unsigned char cylinder_high;
144
                unsigned char device_control;
145
                unsigned char device_head;
146
                unsigned char error;
147
                unsigned char features;
148
                unsigned char sector_count;
149
                unsigned char sector_number;
150
                unsigned char status;
151
 
152
                short dataport_i;
153
        } regs;
154
 
155
        /******** ata device output signals **************************/
156
        struct {
157
                int iordy;
158
                int intrq;
159
                int dmarq;
160
                int pdiagi, pdiago;
161
                int daspi, daspo;
162
        } sigs;
163
 
164
        /******** simulator settings **********************************/
165
        /* simulate ata-device                                        */
166 1364 nogj
        char *file;   /* Filename (if type == FILE)                   */
167 876 rherveille
        FILE *stream; /* stream where the simulated device connects to*/
168
        int  type;    /* Simulate device using                        */
169
                      /* NO_CONNECT: no device connected (dummy)      */
170
                      /* FILE      : a file                           */
171
                      /* LOCAL     : a local stream, e.g./dev/hda1    */
172
        unsigned long size;    /* size in MB of the simulated device  */
173
        int  packet;  /* device implements PACKET command set         */
174
} ata_device;
175
 
176
typedef struct{
177
  ata_device device0, device1;
178
} ata_devices;
179
 
180
 
181
/* all devices                                                        */
182 1364 nogj
void  ata_devices_init(ata_devices *devices);
183 876 rherveille
void  ata_devices_hw_reset(ata_devices *devices, int reset_signal);
184
short ata_devices_read(ata_devices *devices, char adr);
185
void  ata_devices_write(ata_devices *devices, char adr, short value);
186
 
187
/* single device                                                      */
188 1364 nogj
void ata_device_init(ata_device *device, int dev);
189 876 rherveille
void ata_device_hw_reset(ata_device *device, int reset_signal, int daspo, int pdiagi, int daspi);
190
void ata_device_do_control_register(ata_device *device);
191
void ata_device_do_command_register(ata_device *device);
192
void ata_device_write(ata_device *device, char adr, short value);
193
 
194
/* housekeeping routines                                              */
195
FILE  *open_file(unsigned long *size, const char *filename);
196
FILE  *open_local(void);
197
 
198
 
199
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.