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/*
    atahost.c -- ATA Host code simulation
    Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
 
    This file is part of OpenRISC 1000 Architectural Simulator
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
/* get a prototype for 'register_memoryarea()', and 'adjust_rw_delay()' */
#include "abstract.h"
#include "sim-config.h"
#include "sched.h"
 
/* all user defineable settings are in 'atahost_define.h'             */
#include "atahost_define.h"
#include "atahost.h"
#include "messages.h"
 
static ata_host atas[MAX_ATAS];
 
/* reset and initialize ATA host core(s) */
void ata_reset(void)
{
   static int first_time=0;
 
   unsigned i;
   ata_host *ata;
 
   // for all ATA cores
   for (i=0; i < config.natas; i++)
   {
     ata = &(atas[i]);
 
     // reset the core registers
     ata->regs.ctrl  = 0x0001;
     ata->regs.stat  = (DEV_ID << 28) | (REV << 24);
     ata->regs.pctr  = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
     ata->regs.pftr0 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
     ata->regs.pftr1 = (PIO_MODE0_TEOC << ATA_TEOC) | (PIO_MODE0_T4 << ATA_T4) | (PIO_MODE0_T2 << ATA_T2) | (PIO_MODE0_T1 << ATA_T1);
     ata->regs.dtr0  = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
     ata->regs.dtr1  = (DMA_MODE0_TEOC << ATA_TEOC) | (DMA_MODE0_TD << ATA_TD) | (DMA_MODE0_TM << ATA_TM);
     ata->regs.txb   = 0;
 
     // copy the config settings
     ata->ata_number = i;
     ata->irq        = config.atas[i].irq;
     ata->baseaddr   = config.atas[i].baseaddr;
 
     ata->devices.device0.size   = config.atas[i].dev_size0;
     ata->devices.device0.type   = config.atas[i].dev_type0;
     ata->devices.device0.packet = config.atas[i].dev_packet0;
     ata->devices.device1.size   = config.atas[i].dev_size1;
     ata->devices.device1.type   = config.atas[i].dev_type1;
     ata->devices.device1.packet = config.atas[i].dev_packet1;
 
     // inform simulator about new read/write delay timings
     adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
 
     /* initialize simulator & ata_devices                                */
     if (!first_time)
     {
       /* Connect ata_devices.                                            */
       ata_devices_init(&ata->devices, config.atas[i].dev_file0, config.atas[i].dev_file1);
 
       register_memoryarea(ata->baseaddr, ATA_ADDR_SPACE, 4, ata_read32, ata_write32);
     }
 
     /* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */
     ata_devices_hw_reset(&ata->devices, 1);
   }
 
   first_time++;
}
/* ========================================================================= */
 
 
/* Convert a memory address to a device struct and relative address.
 * Return nonzero on success */
int ata_find_device( unsigned long addr, ata_host **ata, unsigned long *reladdr )
{
  unsigned i;
  *ata = NULL;
 
  for ( i = 0; i < config.natas && *ata == NULL; ++ i ) {
    if ( (addr >= atas[i].baseaddr) && (addr < atas[i].baseaddr + ATA_ADDR_SPACE) )
      *ata = &(atas[i]);
  }
 
  /* verify we found a device */
  if ( *ata == NULL )
    return 0;
 
  /* Verify legal address */
  if ( (addr - (*ata)->baseaddr) % 4 != 0 )
    return 0;
 
  *reladdr = addr - (*ata) -> baseaddr;
  return 1;
}
/* ========================================================================= */
 
 
/*
  Read a register
*/
unsigned long ata_read32( unsigned long addr )
{
    ata_host *ata;
 
    if ( !ata_find_device( addr, &ata, &addr ) )    {
        fprintf(stderr, "ata_read32( 0x%08lX ): Not in registered range(s)\n", addr );
        return 0;
    }
 
    /* determine if ata_host or ata_device addressed */
    if (is_ata_hostadr(addr))
    {
        // Accesses to internal register take 2cycles
        adjust_rw_delay( ata->baseaddr, 2, 2 );
 
        switch( addr ) {
            case ATA_CTRL :
                return ata -> regs.ctrl;
 
            case ATA_STAT :
                return ata -> regs.stat;
 
            case ATA_PCTR :
                return ata -> regs.pctr;
 
#if (DEV_ID > 1)
            case ATA_PFTR0:
                return ata -> regs.pftr0;
 
            case ATA_PFTR1:
                return ata -> regs.pftr1;
#endif
 
#if (DEV_ID > 2)
            case ATA_DTR0 :
                return ata -> regs.dtr0;
 
            case ATA_DTR1 :
                return ata -> regs.dtr1;
 
            case ATA_RXB  :
                return ata -> regs.rxb;
#endif
 
            default:
                return 0;
        }
    }
    else
    {
        // make sure simulator uses correct read/write delay timings
#if (DEV_ID > 1)
        if ( (addr & 0x7f) == ATA_DR)
        {
          if (ata->devices.dev)
              adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
          else
              adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
        }
        else
#endif
        adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
 
        return ata_devices_read(&ata->devices, addr & 0x7f);
    }
}
/* ========================================================================= */
 
 
/*
  Write a register
*/
void ata_write32( unsigned long addr, unsigned long value )
{
    ata_host *ata;
 
    if ( !ata_find_device( addr, &ata, &addr ) )
    {
        fprintf(stderr, "ata_write32( 0x%08lX ): Not in registered range(s)\n", addr );
        return;
    }
 
    /* determine if ata_host or ata_device addressed */
    if (is_ata_hostadr(addr))
    {
       // Accesses to internal register take 2cycles
       adjust_rw_delay( ata->baseaddr, 2, 2 );
 
        switch( addr ) {
            case ATA_CTRL :
                ata -> regs.ctrl =  value;
 
                /* check if reset bit set, if so reset ata-devices    */
                if (value & ATA_RST)
                  ata_devices_hw_reset(&ata->devices, 1);
                else
                  ata_devices_hw_reset(&ata->devices, 0);
                break;
 
            case ATA_STAT :
                ata -> regs.stat = (ata -> regs.stat & ~ATA_IDEIS) | (ata -> regs.stat & ATA_IDEIS & value);
                break;
 
            case ATA_PCTR :
                ata -> regs.pctr = value;
                break;
 
            case ATA_PFTR0:
                ata -> regs.pftr0 = value;
                break;
 
            case ATA_PFTR1:
                ata -> regs.pftr1 = value;
                break;
 
            case ATA_DTR0 :
                ata -> regs.dtr0  = value;
                break;
 
            case ATA_DTR1 :
                ata -> regs.dtr1  = value;
                break;
 
            case ATA_TXB  :
                ata -> regs.txb   = value;
                break;
 
            default:
                /* ERROR-macro currently only supports simple strings. */
                /*
                  fprintf(stderr, "ERROR  : Unknown register for OCIDEC(%1d).\n", DEV_ID );
 
                  Tried to show some useful info here.
                  But when using 'DM'-simulator-command, the screen gets filled with these messages.
                  Thereby eradicating the usefulness of the message
                */
                break;
        }
    }
    else
    {
        // make sure simulator uses correct read/write delay timings
#if (DEV_ID > 1)
        if ( (addr & 0x7f) == ATA_DR)
        {
          if (ata->devices.dev)
              adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );
          else
              adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );
        }
        else
#endif
        adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );
 
        ata_devices_write(&ata->devices, addr & 0x7f, value);
    }
}
/* ========================================================================= */
 
 
/* Dump status */
void ata_status( void )
{
  unsigned i;
  ata_host *ata;
 
  for ( i = 0; i < config.natas; i++ ) {
      ata = &(atas[i]);
 
      if ( ata->baseaddr == 0 )
         continue;
 
       printf( "\nOCIDEC-%1d %u at: 0x%08X\n", DEV_ID, i, ata->baseaddr );
       printf( "ATA CTRL     : 0x%08lX\n", ata->regs.ctrl  );
       printf( "ATA STAT     : 0x%08lx\n", ata->regs.stat  );
       printf( "ATA PCTR     : 0x%08lx\n", ata->regs.pctr  );
 
#if (DEV_ID > 1)
       printf( "ATA FCTR0    : 0x%08lx\n", ata->regs.pftr0 );
       printf( "ATA FCTR1    : 0x%08lx\n", ata->regs.pftr1 );
#endif
 
#if (DEV_ID > 2)
       printf( "ATA DTR0     : 0x%08lx\n", ata->regs.dtr0  );
       printf( "ATA DTR1     : 0x%08lx\n", ata->regs.dtr1  );
       printf( "ATA TXD      : 0x%08lx\n", ata->regs.txb   );
       printf( "ATA RXD      : 0x%08lx\n", ata->regs.rxb   );
#endif
  }
}
/* ========================================================================= */

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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [peripheral/] [atahost.c] - Blame information for rev 919

Line No.	Rev	Author	Line
1	876	rherveille	`/*`
2			`atahost.c -- ATA Host code simulation`
3			`Copyright (C) 2002 Richard Herveille, rherveille@opencores.org`
4
5			`This file is part of OpenRISC 1000 Architectural Simulator`
6
7			`This program is free software; you can redistribute it and/or modify`
8			`it under the terms of the GNU General Public License as published by`
9			`the Free Software Foundation; either version 2 of the License, or`
10			`(at your option) any later version`
11
12			`This program is distributed in the hope that it will be useful,`
13			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
14			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
15			`GNU General Public License for more details.`
16
17			`You should have received a copy of the GNU General Public License`
18			`along with this program; if not, write to the Free Software`
19			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.`
20			`*/`
21
22	919	rherveille	`/* get a prototype for 'register_memoryarea()', and 'adjust_rw_delay()' */`
23	876	rherveille	`#include "abstract.h"`
24			`#include "sim-config.h"`
25			`#include "sched.h"`
26
27	919	rherveille	`/* all user defineable settings are in 'atahost_define.h' */`
28			`#include "atahost_define.h"`
29	876	rherveille	`#include "atahost.h"`
30			`#include "messages.h"`
31
32			`static ata_host atas[MAX_ATAS];`
33
34			`/* reset and initialize ATA host core(s) */`
35			`void ata_reset(void)`
36			`{`
37			`static int first_time=0;`
38
39			`unsigned i;`
40			`ata_host *ata;`
41
42			`// for all ATA cores`
43			`for (i=0; i < config.natas; i++)`
44			`{`
45			`ata = &(atas[i]);`
46
47			`// reset the core registers`
48			`ata->regs.ctrl = 0x0001;`
49	919	rherveille	`ata->regs.stat = (DEV_ID << 28) \| (REV << 24);`
50	876	rherveille	`ata->regs.pctr = (PIO_MODE0_TEOC << ATA_TEOC) \| (PIO_MODE0_T4 << ATA_T4) \| (PIO_MODE0_T2 << ATA_T2) \| (PIO_MODE0_T1 << ATA_T1);`
51			`ata->regs.pftr0 = (PIO_MODE0_TEOC << ATA_TEOC) \| (PIO_MODE0_T4 << ATA_T4) \| (PIO_MODE0_T2 << ATA_T2) \| (PIO_MODE0_T1 << ATA_T1);`
52			`ata->regs.pftr1 = (PIO_MODE0_TEOC << ATA_TEOC) \| (PIO_MODE0_T4 << ATA_T4) \| (PIO_MODE0_T2 << ATA_T2) \| (PIO_MODE0_T1 << ATA_T1);`
53			`ata->regs.dtr0 = (DMA_MODE0_TEOC << ATA_TEOC) \| (DMA_MODE0_TD << ATA_TD) \| (DMA_MODE0_TM << ATA_TM);`
54			`ata->regs.dtr1 = (DMA_MODE0_TEOC << ATA_TEOC) \| (DMA_MODE0_TD << ATA_TD) \| (DMA_MODE0_TM << ATA_TM);`
55			`ata->regs.txb = 0;`
56	919	rherveille
57	876	rherveille	`// copy the config settings`
58			`ata->ata_number = i;`
59			`ata->irq = config.atas[i].irq;`
60			`ata->baseaddr = config.atas[i].baseaddr;`
61
62			`ata->devices.device0.size = config.atas[i].dev_size0;`
63			`ata->devices.device0.type = config.atas[i].dev_type0;`
64			`ata->devices.device0.packet = config.atas[i].dev_packet0;`
65			`ata->devices.device1.size = config.atas[i].dev_size1;`
66			`ata->devices.device1.type = config.atas[i].dev_type1;`
67			`ata->devices.device1.packet = config.atas[i].dev_packet1;`
68
69	919	rherveille	`// inform simulator about new read/write delay timings`
70			`adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );`
71
72	876	rherveille	`/* initialize simulator & ata_devices */`
73			`if (!first_time)`
74			`{`
75			`/* Connect ata_devices. */`
76			`ata_devices_init(&ata->devices, config.atas[i].dev_file0, config.atas[i].dev_file1);`
77
78			`register_memoryarea(ata->baseaddr, ATA_ADDR_SPACE, 4, ata_read32, ata_write32);`
79			`}`
80
81			`/* the reset bit in the control register 'ctrl' is set, reset connect ata-devices */`
82			`ata_devices_hw_reset(&ata->devices, 1);`
83			`}`
84
85			`first_time++;`
86			`}`
87			`/* ========================================================================= */`
88
89
90			`/* Convert a memory address to a device struct and relative address.`
91			`* Return nonzero on success */`
92			`int ata_find_device( unsigned long addr, ata_host *ata, unsigned long reladdr )`
93			`{`
94			`unsigned i;`
95			`*ata = NULL;`
96
97			`for ( i = 0; i < config.natas && *ata == NULL; ++ i ) {`
98			`if ( (addr >= atas[i].baseaddr) && (addr < atas[i].baseaddr + ATA_ADDR_SPACE) )`
99			`*ata = &(atas[i]);`
100			`}`
101
102			`/* verify we found a device */`
103			`if ( *ata == NULL )`
104			`return 0;`
105
106			`/* Verify legal address */`
107			`if ( (addr - (*ata)->baseaddr) % 4 != 0 )`
108			`return 0;`
109
110			`reladdr = addr - (ata) -> baseaddr;`
111			`return 1;`
112			`}`
113			`/* ========================================================================= */`
114
115
116			`/*`
117			`Read a register`
118			`*/`
119			`unsigned long ata_read32( unsigned long addr )`
120			`{`
121			`ata_host *ata;`
122
123			`if ( !ata_find_device( addr, &ata, &addr ) ) {`
124			`fprintf(stderr, "ata_read32( 0x%08lX ): Not in registered range(s)\n", addr );`
125			`return 0;`
126			`}`
127
128			`/* determine if ata_host or ata_device addressed */`
129			`if (is_ata_hostadr(addr))`
130	919	rherveille	`{`
131			`// Accesses to internal register take 2cycles`
132			`adjust_rw_delay( ata->baseaddr, 2, 2 );`
133
134	876	rherveille	`switch( addr ) {`
135			`case ATA_CTRL :`
136			`return ata -> regs.ctrl;`
137
138			`case ATA_STAT :`
139			`return ata -> regs.stat;`
140
141			`case ATA_PCTR :`
142			`return ata -> regs.pctr;`
143
144			`#if (DEV_ID > 1)`
145			`case ATA_PFTR0:`
146			`return ata -> regs.pftr0;`
147
148			`case ATA_PFTR1:`
149			`return ata -> regs.pftr1;`
150			`#endif`
151
152			`#if (DEV_ID > 2)`
153			`case ATA_DTR0 :`
154			`return ata -> regs.dtr0;`
155
156			`case ATA_DTR1 :`
157			`return ata -> regs.dtr1;`
158
159			`case ATA_RXB :`
160			`return ata -> regs.rxb;`
161			`#endif`
162
163			`default:`
164			`return 0;`
165	919	rherveille	`}`
166	876	rherveille	`}`
167			`else`
168	919	rherveille	`{`
169			`// make sure simulator uses correct read/write delay timings`
170			`#if (DEV_ID > 1)`
171			`if ( (addr & 0x7f) == ATA_DR)`
172			`{`
173			`if (ata->devices.dev)`
174			`adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );`
175			`else`
176			`adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );`
177			`}`
178			`else`
179			`#endif`
180			`adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );`
181
182			`return ata_devices_read(&ata->devices, addr & 0x7f);`
183			`}`
184	876	rherveille	`}`
185			`/* ========================================================================= */`
186
187
188			`/*`
189			`Write a register`
190			`*/`
191			`void ata_write32( unsigned long addr, unsigned long value )`
192			`{`
193			`ata_host *ata;`
194
195			`if ( !ata_find_device( addr, &ata, &addr ) )`
196			`{`
197			`fprintf(stderr, "ata_write32( 0x%08lX ): Not in registered range(s)\n", addr );`
198			`return;`
199			`}`
200
201			`/* determine if ata_host or ata_device addressed */`
202			`if (is_ata_hostadr(addr))`
203	919	rherveille	`{`
204			`// Accesses to internal register take 2cycles`
205			`adjust_rw_delay( ata->baseaddr, 2, 2 );`
206
207	876	rherveille	`switch( addr ) {`
208			`case ATA_CTRL :`
209			`ata -> regs.ctrl = value;`
210
211			`/* check if reset bit set, if so reset ata-devices */`
212			`if (value & ATA_RST)`
213			`ata_devices_hw_reset(&ata->devices, 1);`
214			`else`
215			`ata_devices_hw_reset(&ata->devices, 0);`
216			`break;`
217
218			`case ATA_STAT :`
219			`ata -> regs.stat = (ata -> regs.stat & ~ATA_IDEIS) \| (ata -> regs.stat & ATA_IDEIS & value);`
220			`break;`
221
222			`case ATA_PCTR :`
223			`ata -> regs.pctr = value;`
224			`break;`
225
226			`case ATA_PFTR0:`
227			`ata -> regs.pftr0 = value;`
228			`break;`
229
230			`case ATA_PFTR1:`
231			`ata -> regs.pftr1 = value;`
232			`break;`
233
234			`case ATA_DTR0 :`
235			`ata -> regs.dtr0 = value;`
236			`break;`
237
238			`case ATA_DTR1 :`
239			`ata -> regs.dtr1 = value;`
240			`break;`
241
242			`case ATA_TXB :`
243			`ata -> regs.txb = value;`
244			`break;`
245
246			`default:`
247			`/* ERROR-macro currently only supports simple strings. */`
248			`/*`
249			`fprintf(stderr, "ERROR : Unknown register for OCIDEC(%1d).\n", DEV_ID );`
250
251			`Tried to show some useful info here.`
252			`But when using 'DM'-simulator-command, the screen gets filled with these messages.`
253			`Thereby eradicating the usefulness of the message`
254			`*/`
255			`break;`
256			`}`
257	919	rherveille	`}`
258	876	rherveille	`else`
259	919	rherveille	`{`
260			`// make sure simulator uses correct read/write delay timings`
261			`#if (DEV_ID > 1)`
262			`if ( (addr & 0x7f) == ATA_DR)`
263			`{`
264			`if (ata->devices.dev)`
265			`adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr1), ata_pio_delay(ata->regs.ftcr1) );`
266			`else`
267			`adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.ftcr0), ata_pio_delay(ata->regs.ftcr0) );`
268			`}`
269			`else`
270			`#endif`
271			`adjust_rw_delay( ata->baseaddr, ata_pio_delay(ata->regs.pctr), ata_pio_delay(ata->regs.pctr) );`
272
273	876	rherveille	`ata_devices_write(&ata->devices, addr & 0x7f, value);`
274	919	rherveille	`}`
275	876	rherveille	`}`
276			`/* ========================================================================= */`
277
278
279			`/* Dump status */`
280			`void ata_status( void )`
281			`{`
282			`unsigned i;`
283			`ata_host *ata;`
284
285			`for ( i = 0; i < config.natas; i++ ) {`
286			`ata = &(atas[i]);`
287
288			`if ( ata->baseaddr == 0 )`
289			`continue;`
290
291			`printf( "\nOCIDEC-%1d %u at: 0x%08X\n", DEV_ID, i, ata->baseaddr );`
292			`printf( "ATA CTRL : 0x%08lX\n", ata->regs.ctrl );`
293			`printf( "ATA STAT : 0x%08lx\n", ata->regs.stat );`
294			`printf( "ATA PCTR : 0x%08lx\n", ata->regs.pctr );`
295
296			`#if (DEV_ID > 1)`
297			`printf( "ATA FCTR0 : 0x%08lx\n", ata->regs.pftr0 );`
298			`printf( "ATA FCTR1 : 0x%08lx\n", ata->regs.pftr1 );`
299			`#endif`
300
301			`#if (DEV_ID > 2)`
302			`printf( "ATA DTR0 : 0x%08lx\n", ata->regs.dtr0 );`
303			`printf( "ATA DTR1 : 0x%08lx\n", ata->regs.dtr1 );`
304			`printf( "ATA TXD : 0x%08lx\n", ata->regs.txb );`
305			`printf( "ATA RXD : 0x%08lx\n", ata->regs.rxb );`
306			`#endif`
307			`}`
308			`}`
309			`/* ========================================================================= */`