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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 1372

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1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 1308 phoenix 
#include <netinet/in.h>
33 696 ivang 
 
34 867 markom 
#include "config.h"
35 1350 nogj 
 
36 
#ifdef HAVE_INTTYPES_H
37 
#include <inttypes.h>
38 
#endif
39 
 
40 
#include "port.h"
41 
#include "arch.h"
42 
#include "config.h"
43 696 ivang 
#include "abstract.h"
44 
#include "ethernet_i.h"
45 
#include "dma.h"
46 
#include "sim-config.h"
47 
#include "fields.h"
48 
#include "crc32.h"
49 889 ivang 
#include "vapi.h"
50 1308 phoenix 
#include "pic.h"
51 1372 nogj 
#include "sched.h"
52 1308 phoenix 
#include "debug.h"
53 696 ivang 
 
54 1372 nogj 
DEFAULT_DEBUG_CHANNEL(eth);
55 696 ivang 
 
56 702 ivang 
/* simulator interface */
57 1366 nogj 
static void eth_vapi_read( unsigned long id, unsigned long data, void *dat);
58 696 ivang 
/* register interface */
59 1359 nogj 
static void eth_write32( oraddr_t addr, uint32_t value, void *dat );
60 
static uint32_t eth_read32( oraddr_t addr, void *dat );
61 696 ivang 
/* clock */
62 1372 nogj 
static void eth_controller_tx_clock( void * );
63 
static void eth_controller_rx_clock( void * );
64 696 ivang 
/* utility functions */
65 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
66 
static void eth_skip_rx_file( struct eth_device *, off_t );
67 
static void eth_rewind_rx_file( struct eth_device *, off_t );
68 
static void eth_rx_next_packet( struct eth_device * );
69 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
70 696 ivang 
/* ========================================================================= */
71 702 ivang 
/*  TX LOGIC                                                                 */
72 696 ivang 
/*---------------------------------------------------------------------------*/
73 
 
74 
/*
75 
 * TX clock
76 
 * Responsible for starting and finishing TX
77 
 */
78 1372 nogj 
void eth_controller_tx_clock( void *dat )
79 696 ivang 
{
80 1372 nogj 
    struct eth_device *eth = dat;
81 702 ivang 
    int breakpoint = 0;
82 
    int bAdvance   = 1;
83 867 markom 
#if HAVE_ETH_PHY
84 702 ivang 
    struct sockaddr_ll sll;
85 849 markom 
#endif /* HAVE_ETH_PHY */
86 702 ivang 
    long nwritten;
87 
    unsigned long read_word;
88 696 ivang 
 
89 
    switch (eth->tx.state) {
90 1372 nogj 
    case ETH_TXSTATE_IDLE:
91 
        debug (3, "TX - entering state WAIT4BD (%ld)\n", eth->tx.bd_index);
92 
        eth->tx.state = ETH_TXSTATE_WAIT4BD;
93 702 ivang 
        break;
94 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
95 702 ivang 
        /* Read buffer descriptor */
96 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
97 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
98 
 
99 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
100 
            /*****************/
101 
            /* initialize TX */
102 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
103 
            eth->tx.bytes_sent = 0;
104 
 
105 
            /*   Initialize error status bits */
106 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
107 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
108 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
109 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
110 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
111 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
112 
 
113 
            /* Find out minimum length */
114 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
115 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
116 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
117 
            else
118 
                eth->tx.minimum_length = eth->tx.packet_length;
119 
 
120 
            /* Find out maximum length */
121 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
122 
                eth->tx.maximum_length = eth->tx.packet_length;
123 
            else
124 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
125 
 
126 
            /* Do we need CRC on this packet? */
127 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
128 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
129 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
130 
                eth->tx.add_crc = 1;
131 
            else
132 
                eth->tx.add_crc = 0;
133 
 
134 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
135 
                eth->tx.crc_dly = 1;
136 
            else
137 
                eth->tx.crc_dly = 0;
138 
            /* XXX - For now we skip CRC calculation */
139 
 
140 1350 nogj 
            debug( 3, "Ethernet: Starting TX of %lu bytes (min. %u, max. %u)\n",
141 
                   eth->tx.packet_length, eth->tx.minimum_length,
142 
                   eth->tx.maximum_length );
143 702 ivang 
 
144 
            if (eth->rtx_type == ETH_RTX_FILE) {
145 
                /* write packet length to file */
146 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
147 
            }
148 
 
149 
            /************************************************/
150 
            /* start transmit with reading packet into FIFO */
151 
                debug (3, "TX - entering state READFIFO\n");
152 
            eth->tx.state = ETH_TXSTATE_READFIFO;
153 
        }
154 
 
155 
        /* stay in this state if (TXEN && !READY) */
156 
        break;
157 696 ivang 
    case ETH_TXSTATE_READFIFO:
158 744 simons 
#if 1
159 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
160 1241 phoenix 
            read_word = eval_direct32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
161 702 ivang 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
162 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
163 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
164 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
165 
            eth->tx.bytes_sent += 4;
166 
        }
167 744 simons 
#else
168 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
169 1241 phoenix 
            eth->tx_buff[eth->tx.bytes_sent] = eval_direct8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint, 0, 0);
170 744 simons 
            eth->tx.bytes_sent += 1;
171 
        }
172 
#endif
173 702 ivang 
        else {
174 
            debug (3, "TX - entering state TRANSMIT\n");
175 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
176 
        }
177 
        break;
178 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
179 702 ivang 
        /* send packet */
180 
        switch (eth->rtx_type) {
181 
        case ETH_RTX_FILE:
182 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
183 
            break;
184 867 markom 
#if HAVE_ETH_PHY
185 702 ivang 
        case ETH_RTX_SOCK:
186 
            memset(&sll, 0, sizeof(sll));
187 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
188 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
189 849 markom 
#endif /* HAVE_ETH_PHY */
190 702 ivang 
        }
191 
 
192 
        /* set BD status */
193 
        if (nwritten == eth->tx.packet_length) {
194 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
195 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
196 1350 nogj 
            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
197 702 ivang 
 
198 1372 nogj 
            debug (3, "TX - entering state WAIT4BD\n");
199 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
200 1350 nogj 
            debug (3, "send (%ld)bytes OK\n", nwritten);
201 702 ivang 
        }
202 
        else {
203 
            /* XXX - implement retry mechanism here! */
204 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
205 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
206 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
207 1350 nogj 
            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
208 702 ivang 
 
209 1372 nogj 
            debug (3, "TX - entering state WAIT4BD\n");
210 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
211 702 ivang 
            debug (3, "send FAILED!\n");
212 
        }
213 
 
214 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
215 
 
216 889 ivang 
        /* generate OK interrupt */
217 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
218 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
219 
        {
220 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, IRQ ) )
221 
                report_interrupt( eth->mac_int );
222 
        }
223 
 
224 702 ivang 
        /* advance to next BD */
225 
        if (bAdvance) {
226 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
227 
                            eth->tx.bd_index >= ETH_BD_COUNT )
228 
                eth->tx.bd_index = 0;
229 
            else
230 
                eth->tx.bd_index += 2;
231 
        }
232 
 
233 
        break;
234 696 ivang 
    }
235 1372 nogj 
 
236 
    /* Reschedule */
237 
    SCHED_ADD( eth_controller_tx_clock, dat, runtime.sim.cycles + 1 );
238 696 ivang 
}
239 
/* ========================================================================= */
240 
 
241 
 
242 
/* ========================================================================= */
243 702 ivang 
/*  RX LOGIC                                                                 */
244 696 ivang 
/*---------------------------------------------------------------------------*/
245 
 
246 
/*
247 
 * RX clock
248 
 * Responsible for starting and finishing RX
249 
 */
250 1372 nogj 
void eth_controller_rx_clock( void *dat )
251 696 ivang 
{
252 1372 nogj 
    struct eth_device *eth = dat;
253 702 ivang 
    int breakpoint = 0;
254 
    long nread;
255 
    unsigned long send_word;
256 
 
257 
 
258 696 ivang 
    switch (eth->rx.state) {
259 
    case ETH_RXSTATE_IDLE:
260 1372 nogj 
        debug (3, "RX - entering state WAIT4BD (%ld)\n", eth->rx.bd_index);
261 
        eth->rx.state = ETH_RXSTATE_WAIT4BD;
262 702 ivang 
        break;
263 
 
264 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
265 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
266 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
267 
 
268 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
269 
            /*****************/
270 
            /* Initialize RX */
271 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
272 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
273 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
274 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
275 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
276 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
277 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
278 
 
279 
            debug( 3,  "Ethernet: Starting RX\n" );
280 
 
281 
            /* Setup file to read from */
282 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
283 
                eth->rx.fd = eth->txfd;
284 
                eth->rx.offset = &(eth->loopback_offset);
285 
            } else {
286 
                eth->rx.fd = eth->rxfd;
287 
                eth->rx.offset = 0;
288 
            }
289 889 ivang 
            debug (3, "RX - entering state RECV\n");
290 702 ivang 
            eth->rx.state = ETH_RXSTATE_RECV;
291 
        }
292 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
293 
          debug (3, "RX - entering state IDLE\n");
294 
          eth->rx.state = ETH_RXSTATE_IDLE;
295 
        }
296 
        else {
297 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
298 705 ivang 
            if (nread > 0) {
299 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
300 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
301 
                  report_interrupt(eth->mac_int);
302 702 ivang 
            }
303 
        }
304 
        break;
305 
 
306 696 ivang 
    case ETH_RXSTATE_RECV:
307 702 ivang 
        switch (eth->rtx_type) {
308 
        case ETH_RTX_FILE:
309 
            /* Read packet length */
310 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
311 
                     < sizeof(eth->rx.packet_length) ) {
312 
                /* TODO: just do what real ethernet would do (some kind of error state) */
313 1350 nogj 
                debug (4, "eth_start_rx(): File does not have a packet ready for RX (len = %ld)\n", eth->rx.packet_length );
314 884 markom 
                runtime.sim.cont_run = 0;
315 702 ivang 
                break;
316 
            }
317 
 
318 
            /* Packet must be big enough to hold a header */
319 1244 hpanther 
            if ( eth->rx.packet_length < ETHER_HDR_LEN ){
320 702 ivang 
                debug( 3,  "eth_start_rx(): Packet too small\n" );
321 
                eth_rx_next_packet( eth );
322 
 
323 1372 nogj 
                debug (3, "RX - entering state WAIT4BD\n");
324 
                eth->rx.state = ETH_RXSTATE_WAIT4BD;
325 702 ivang 
                break;
326 
            }
327 
 
328 
            eth->rx.bytes_read = 0;
329 
            eth->rx.bytes_left = eth->rx.packet_length;
330 
 
331 
            /* for now Read entire packet into memory */
332 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
333 844 ivang 
            if ( nread < eth->rx.bytes_left ) {
334 1350 nogj 
                debug (3, "Read %ld from %ld. Error!\n", nread, eth->rx.bytes_left);
335 844 ivang 
                eth->rx.error = 1;
336 
                break;
337 
            }
338 
 
339 
            eth->rx.packet_length = nread;
340 
            eth->rx.bytes_left = nread;
341 
            eth->rx.bytes_read = 0;
342 
 
343 
            debug (3, "RX - entering state WRITEFIFO\n");
344 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
345 
 
346 702 ivang 
            break;
347 
 
348 
        case ETH_RTX_SOCK:
349 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
350 744 simons 
 
351 
            if (nread == 0)
352 
                break;
353 
            else if (nread < 0) {
354 
                if ( errno != EAGAIN ) {
355 889 ivang 
                    debug (3, "recv() FAILED!\n");
356 
                    break;
357 
                }
358 
                else break;
359 
            }
360 744 simons 
            /* If not promiscouos mode, check the destination address */
361 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
362 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
363 
                /* Nothing for now */
364 
                }
365 
 
366 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
367 
                    eth->mac_address[4] != eth->rx_buff[1] ||
368 
                    eth->mac_address[3] != eth->rx_buff[2] ||
369 
                    eth->mac_address[2] != eth->rx_buff[3] ||
370 
                    eth->mac_address[1] != eth->rx_buff[4] ||
371 
                    eth->mac_address[0] != eth->rx_buff[5])
372 889 ivang 
                    break;
373 744 simons 
            }
374 
 
375 841 simons 
            eth->rx.packet_length = nread;
376 
            eth->rx.bytes_left = nread;
377 
            eth->rx.bytes_read = 0;
378 
 
379 
            debug (3, "RX - entering state WRITEFIFO\n");
380 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
381 
 
382 702 ivang 
            break;
383 889 ivang 
        case ETH_RTX_VAPI:
384 1366 nogj 
            break;
385 702 ivang 
        }
386 841 simons 
        break;
387 
 
388 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
389 744 simons 
#if 1
390 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
391 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
392 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
393 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
394 1241 phoenix 
        set_direct32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint, 0, 0);
395 702 ivang 
        /* update counters */
396 1350 nogj 
        debug (3, "Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,
397 
               eth->rx.bytes_left, send_word);
398 702 ivang 
        eth->rx.bytes_left -= 4;
399 
        eth->rx.bytes_read += 4;
400 744 simons 
#else
401 1241 phoenix 
        set_direct8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint, 0, 0);
402 744 simons 
        eth->rx.bytes_left -= 1;
403 
        eth->rx.bytes_read += 1;
404 
#endif
405 
 
406 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
407 
            /* Write result to bd */
408 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
409 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
410 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
411 1350 nogj 
            debug (4, "ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
412 702 ivang 
 
413 1068 simons 
            if ( eth->rx.packet_length < (GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) - 4) )
414 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
415 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
416 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
417 
 
418 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
419 
 
420 
            /* advance to next BD */
421 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
422 1018 simons 
                eth->rx.bd_index = eth->regs.tx_bd_num << 1;
423 702 ivang 
            else
424 705 ivang 
                eth->rx.bd_index += 2;
425 702 ivang 
 
426 889 ivang 
            if ( ( TEST_FLAG( eth->regs.int_mask, ETH_INT_MASK, RXB_M ) ) &&
427 
                 ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, IRQ )              ) ) {
428 702 ivang 
                report_interrupt( eth->mac_int );
429 
            }
430 
 
431 
            /* ready to receive next packet */
432 
                debug (3, "RX - entering state IDLE\n");
433 
            eth->rx.state = ETH_RXSTATE_IDLE;
434 
        }
435 
        break;
436 696 ivang 
    }
437 1372 nogj 
 
438 
    /* Reschedule */
439 
    SCHED_ADD( eth_controller_rx_clock, dat, runtime.sim.cycles + 1 );
440 696 ivang 
}
441 702 ivang 
 
442 696 ivang 
/* ========================================================================= */
443 702 ivang 
/* Move to next RX BD */
444 
void eth_rx_next_packet( struct eth_device *eth )
445 
{
446 
    /* Skip any possible leftovers */
447 
    if ( eth->rx.bytes_left )
448 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
449 
}
450 
/* "Skip" bytes in RX file */
451 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
452 
{
453 
    eth->rx.offset += count;
454 
}
455 696 ivang 
 
456 702 ivang 
/* Move RX file position back */
457 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
458 
{
459 
    eth->rx.offset -= count;
460 
}
461 
/*
462 
 * Utility function to read from the ethernet RX file
463 
 * This function moves the file pointer to the current place in the packet before reading
464 
 */
465 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
466 
{
467 
    ssize_t result;
468 
 
469 
    if ( eth->rx.fd <= 0 ) {
470 
        debug( 3,  "Ethernet: No RX file\n" );
471 
        return 0;
472 
    }
473 
 
474 
    if ( eth->rx.offset )
475 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
476 
            debug( 3,  "Ethernet: Error seeking RX file\n" );
477 
            return 0;
478 
        }
479 696 ivang 
 
480 702 ivang 
    result = read( eth->rx.fd, buf, count );
481 836 ivang 
    debug (4, "Ethernet: read result = %d \n", result);
482 702 ivang 
    if ( eth->rx.offset && result >= 0 )
483 
        *(eth->rx.offset) += result;
484 
 
485 
    return result;
486 
}
487 
 
488 
/* ========================================================================= */
489 
 
490 696 ivang 
/*
491 702 ivang 
  Reset. Initializes all registers to default and places devices in
492 
         memory address space.
493 696 ivang 
*/
494 1372 nogj 
void eth_reset(void *dat)
495 696 ivang 
{
496 1372 nogj 
    struct eth_device *eth = dat;
497 1308 phoenix 
#if HAVE_ETH_PHY
498 702 ivang 
    int j;
499 
    struct sockaddr_ll sll;
500 849 markom 
#endif /* HAVE_ETH_PHY */
501 702 ivang 
 
502 
    if ( eth->baseaddr != 0 ) {
503 
        switch (eth->rtx_type) {
504 
        case ETH_RTX_FILE:
505 
            /* (Re-)open TX/RX files */
506 
            if ( eth->rxfd > 0 )
507 
                close( eth->rxfd );
508 
            if ( eth->txfd > 0 )
509 
                close( eth->txfd );
510 
            eth->rxfd = eth->txfd = -1;
511 
 
512 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
513 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
514 
            if ( (eth->txfd = open( eth->txfile,
515 1244 hpanther 
                                    O_RDWR | O_CREAT | O_APPEND
516 
 
517 
#if defined(O_SYNC)     /* BSD / Mac OS X manual doesn't know about O_SYNC */
518 
                                                                        | O_SYNC
519 
#endif
520 
                                                                        ,
521 702 ivang 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
522 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
523 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
524 
 
525 
            break;
526 867 markom 
#if HAVE_ETH_PHY
527 702 ivang 
        case ETH_RTX_SOCK:
528 
            /* (Re-)open TX/RX sockets */
529 
            if (eth->rtx_sock != 0)
530 
                break;
531 
 
532 
            debug (3, "RTX oppening socket...\n");
533 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
534 
            if (eth->rtx_sock == -1) {
535 
                fprintf( stderr, "Cannot open rtx_sock.\n");
536 
                return;
537 
            }
538 
 
539 
            /* get interface index number */
540 
            debug (3, "RTX getting interface...\n");
541 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
542 1372 nogj 
            strncpy(eth->ifr.ifr_name, eth->sockif, IFNAMSIZ);
543 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
544 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
545 
                return;
546 
            }
547 
            debug (3, "RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
548 
 
549 
            /* Bind to interface... */
550 
            debug (3, "Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
551 
            memset(&sll, 0xff, sizeof(sll));
552 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
553 
            sll.sll_protocol = htons(ETH_P_ALL);
554 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
555 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
556 
                fprintf( stderr, "Error bind().\n");
557 
                return;
558 
            }
559 
 
560 
            /* first, flush all received packets. */
561 
            debug (3, "Flush");
562 
            do {
563 
                fd_set fds;
564 
                struct timeval t;
565 
 
566 
                debug( 3, ".");
567 
                FD_ZERO(&fds);
568 
                FD_SET(eth->rtx_sock, &fds);
569 
                memset(&t, 0, sizeof(t));
570 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
571 
                if (j > 0)
572 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
573 
            } while (j);
574 
            debug (3, "\n");
575 
 
576 
            break;
577 1372 nogj 
#else /* HAVE_ETH_PHY */
578 
        case ETH_RTX_SOCK:
579 
            fprintf (stderr, "Ethernet phy not enabled in this configuration.  Configure with --enable-ethphy.\n");
580 
            exit (1);
581 
            break;
582 849 markom 
#endif /* HAVE_ETH_PHY */
583 702 ivang 
        }
584 
 
585 
        /* Set registers to default values */
586 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
587 
        eth->regs.moder = 0x0000A000;
588 
        eth->regs.ipgt = 0x00000012;
589 
        eth->regs.ipgr1 = 0x0000000C;
590 
        eth->regs.ipgr2 = 0x00000012;
591 
        eth->regs.packetlen = 0x003C0600;
592 
        eth->regs.collconf = 0x000F003F;
593 
        eth->regs.miimoder = 0x00000064;
594 1018 simons 
        eth->regs.tx_bd_num = 0x00000040;
595 702 ivang 
 
596 
        /* Initialize TX/RX status */
597 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
598 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
599 1018 simons 
        eth->rx.bd_index = eth->regs.tx_bd_num << 1;
600 889 ivang 
 
601 
        /* Initialize VAPI */
602 1372 nogj 
        if (eth->base_vapi_id) {
603 
            vapi_install_multi_handler( eth->base_vapi_id, ETH_NUM_VAPI_IDS, eth_vapi_read, dat );
604 889 ivang 
        }
605 702 ivang 
    }
606 
}
607 
/* ========================================================================= */
608 
 
609 
 
610 696 ivang 
/*
611 
  Print register values on stdout
612 
*/
613 1372 nogj 
void eth_status( void *dat )
614 696 ivang 
{
615 1372 nogj 
    struct eth_device *eth = dat;
616 696 ivang 
 
617 1372 nogj 
    PRINTF( "\nEthernet MAC at 0x%"PRIxADDR":\n", eth->baseaddr );
618 
    PRINTF( "MODER        : 0x%08lX\n", eth->regs.moder );
619 
    PRINTF( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
620 
    PRINTF( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
621 
    PRINTF( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
622 
    PRINTF( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
623 
    PRINTF( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
624 
    PRINTF( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
625 
    PRINTF( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
626 
    PRINTF( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
627 
    PRINTF( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
628 
    PRINTF( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
629 
    PRINTF( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
630 
    PRINTF( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
631 
    PRINTF( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
632 
    PRINTF( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
633 
    PRINTF( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
634 
    PRINTF( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
635 
           eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
636 
           eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
637 
    PRINTF( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
638 
    PRINTF( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
639 696 ivang 
}
640 
/* ========================================================================= */
641 
 
642 
 
643 
/*
644 
  Read a register
645 
*/
646 1359 nogj 
uint32_t eth_read32( oraddr_t addr, void *dat )
647 696 ivang 
{
648 1372 nogj 
    struct eth_device *eth = dat;
649 
    addr -= eth->baseaddr;
650 696 ivang 
 
651 
    switch( addr ) {
652 
    case ETH_MODER: return eth->regs.moder;
653 
    case ETH_INT_SOURCE: return eth->regs.int_source;
654 
    case ETH_INT_MASK: return eth->regs.int_mask;
655 
    case ETH_IPGT: return eth->regs.ipgt;
656 
    case ETH_IPGR1: return eth->regs.ipgr1;
657 
    case ETH_IPGR2: return eth->regs.ipgr2;
658 
    case ETH_PACKETLEN: return eth->regs.packetlen;
659 
    case ETH_COLLCONF: return eth->regs.collconf;
660 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
661 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
662 
    case ETH_MIIMODER: return eth->regs.miimoder;
663 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
664 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
665 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
666 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
667 
    case ETH_MIISTATUS: return eth->regs.miistatus;
668 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
669 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
670 
                               (((unsigned long)eth->mac_address[1]) << 8) |
671 
                                 (unsigned long)eth->mac_address[0];
672 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
673 702 ivang 
                                 (unsigned long)eth->mac_address[4];
674 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
675 
    case ETH_HASH1: return eth->regs.hash1;
676 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
677 696 ivang 
    }
678 
 
679 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
680 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
681 696 ivang 
 
682 1350 nogj 
    PRINTF( "eth_read32( 0x%"PRIxADDR" ): Illegal address\n",
683 
            addr + eth->baseaddr );
684 884 markom 
    runtime.sim.cont_run = 0;
685 696 ivang 
    return 0;
686 
}
687 
/* ========================================================================= */
688 
 
689 
 
690 
/*
691 
  Write a register
692 
*/
693 1359 nogj 
void eth_write32( oraddr_t addr, uint32_t value, void *dat )
694 696 ivang 
{
695 1372 nogj 
    struct eth_device *eth = dat;
696 
 
697 
    addr -= eth->baseaddr;
698 
 
699 696 ivang 
    switch( addr ) {
700 1372 nogj 
    case ETH_MODER:
701 
 
702 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) &&
703 
             TEST_FLAG( value, ETH_MODER, RXEN) )
704 
            SCHED_ADD( eth_controller_rx_clock, dat, runtime.sim.cycles + 1 );
705 
        else if ( !TEST_FLAG( value, ETH_MODER, RXEN) )
706 
            SCHED_FIND_REMOVE( eth_controller_rx_clock, dat);
707 
 
708 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN) &&
709 
             TEST_FLAG( value, ETH_MODER, TXEN) )
710 
            SCHED_ADD( eth_controller_tx_clock, dat, runtime.sim.cycles + 1 );
711 
        else if ( !TEST_FLAG( value, ETH_MODER, TXEN) )
712 
            SCHED_FIND_REMOVE( eth_controller_tx_clock, dat);
713 
 
714 
        eth->regs.moder = value;
715 
 
716 
        if (TEST_FLAG(value, ETH_MODER, RST))
717 
            eth_reset( dat );
718 
        return;
719 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
720 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
721 
    case ETH_IPGT: eth->regs.ipgt = value; return;
722 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
723 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
724 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
725 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
726 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
727 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
728 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
729 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
730 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
731 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
732 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
733 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
734 
    case ETH_MAC_ADDR0:
735 702 ivang 
        eth->mac_address[0] = value & 0xFF;
736 
        eth->mac_address[1] = (value >> 8) & 0xFF;
737 
        eth->mac_address[2] = (value >> 16) & 0xFF;
738 
        eth->mac_address[3] = (value >> 24) & 0xFF;
739 
        return;
740 696 ivang 
    case ETH_MAC_ADDR1:
741 702 ivang 
        eth->mac_address[4] = value & 0xFF;
742 
        eth->mac_address[5] = (value >> 8) & 0xFF;
743 
        return;
744 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
745 
    case ETH_HASH1: eth->regs.hash1 = value; return;
746 702 ivang 
 
747 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
748 696 ivang 
    }
749 
 
750 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
751 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
752 
        return;
753 696 ivang 
    }
754 
 
755 1350 nogj 
    PRINTF( "eth_write32( 0x%"PRIxADDR" ): Illegal address\n",
756 
            addr + eth->baseaddr );
757 884 markom 
    runtime.sim.cont_run = 0;
758 696 ivang 
    return;
759 
}
760 
/* ========================================================================= */
761 
 
762 
 
763 889 ivang 
/*
764 
 *   VAPI connection to outside
765 
 */
766 1366 nogj 
static void eth_vapi_read (unsigned long id, unsigned long data, void *dat)
767 889 ivang 
{
768 
    unsigned long which;
769 1372 nogj 
    struct eth_device *eth = dat;
770 889 ivang 
 
771 1372 nogj 
    which = id - eth->base_vapi_id;
772 
 
773 1350 nogj 
    debug( 5, "ETH: id %08lx, data %08lx\n", id, data );
774 889 ivang 
 
775 
    if ( !eth ) {
776 1350 nogj 
        debug( 1, "ETH: VAPI ID %08lx is not ours!\n", id );
777 889 ivang 
        return;
778 
    }
779 
 
780 
    switch( which ) {
781 
    case ETH_VAPI_DATA:
782 
        break;
783 
    case ETH_VAPI_CTRL:
784 
        break;
785 
    }
786 
}
787 
/* ========================================================================= */
788 
 
789 
 
790 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
791 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
792 
{
793 1018 simons 
    eth->regs.tx_bd_num = value & 0xFF;
794 
    eth->rx.bd_index = eth->regs.tx_bd_num << 1;
795 702 ivang 
}
796 1372 nogj 
 
797 702 ivang 
/* ========================================================================= */
798 
 
799 1372 nogj 
/*-----------------------------------------------[ Ethernet configuration ]---*/
800 
void eth_baseaddr(union param_val val, void *dat)
801 696 ivang 
{
802 1372 nogj 
  struct eth_device *eth = dat;
803 
  eth->baseaddr = val.addr_val;
804 696 ivang 
}
805 889 ivang 
 
806 1372 nogj 
void eth_dma(union param_val val, void *dat)
807 889 ivang 
{
808 1372 nogj 
  struct eth_device *eth = dat;
809 
  eth->dma = val.addr_val;
810 889 ivang 
}
811 1358 nogj 
 
812 1372 nogj 
void eth_rtx_type(union param_val val, void *dat)
813 
{
814 
  struct eth_device *eth = dat;
815 
  eth->rtx_type = val.int_val;
816 1358 nogj 
}
817 
 
818 1372 nogj 
void eth_rx_channel(union param_val val, void *dat)
819 
{
820 
  struct eth_device *eth = dat;
821 
  eth->rx_channel = val.int_val;
822 1358 nogj 
}
823 
 
824 1372 nogj 
void eth_tx_channel(union param_val val, void *dat)
825 
{
826 
  struct eth_device *eth = dat;
827 
  eth->tx_channel = val.int_val;
828 1358 nogj 
}
829 
 
830 1372 nogj 
void eth_rxfile(union param_val val, void *dat)
831 
{
832 
  struct eth_device *eth = dat;
833 
  if(!(eth->rxfile = strdup(val.str_val))) {
834 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
835 
    exit(-1);
836 
  }
837 1358 nogj 
}
838 
 
839 
void eth_txfile(union param_val val, void *dat)
840 
{
841 1372 nogj 
  struct eth_device *eth = dat;
842 
  if(!(eth->txfile = strdup(val.str_val))) {
843 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
844 
    exit(-1);
845 
  }
846 1358 nogj 
}
847 
 
848 
void eth_sockif(union param_val val, void *dat)
849 
{
850 1372 nogj 
  struct eth_device *eth = dat;
851 
  if(!(eth->sockif = strdup(val.str_val))) {
852 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
853 
    exit(-1);
854 
  }
855 1358 nogj 
}
856 
 
857 
void eth_irq(union param_val val, void *dat)
858 
{
859 1372 nogj 
  struct eth_device *eth = dat;
860 
  eth->mac_int = val.int_val;
861 1358 nogj 
}
862 
 
863 
void eth_vapi_id(union param_val val, void *dat)
864 
{
865 1372 nogj 
  struct eth_device *eth = dat;
866 
  eth->base_vapi_id = val.int_val;
867 1358 nogj 
}
868 
 
869 1372 nogj 
void *eth_sec_start(void)
870 
{
871 
  struct eth_device *new = malloc(sizeof(struct eth_device));
872 
 
873 
  if(!new) {
874 
    fprintf(stderr, "Peripheral Eth: Run out of memory\n");
875 
    exit(-1);
876 
  }
877 
 
878 
  return new;
879 
}
880 
 
881 
void eth_sec_end(void *dat)
882 
{
883 
  struct eth_device *eth = dat;
884 
 
885 
  register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, 0, eth_read32, eth_write32, dat );
886 
  reg_sim_stat( eth_status, dat );
887 
  reg_sim_reset( eth_reset, dat );
888 
}
889 
 
890 1358 nogj 
void reg_ethernet_sec(void)
891 
{
892 1372 nogj 
  struct config_section *sec = reg_config_sec("ethernet", eth_sec_start, eth_sec_end);
893 1358 nogj 
 
894 
  reg_config_param(sec, "irq", paramt_int, eth_irq);
895 
  reg_config_param(sec, "baseaddr", paramt_int, eth_baseaddr);
896 
  reg_config_param(sec, "dma", paramt_int, eth_dma);
897 
  reg_config_param(sec, "rtx_type", paramt_int, eth_rtx_type);
898 
  reg_config_param(sec, "rx_channel", paramt_int, eth_rx_channel);
899 
  reg_config_param(sec, "tx_channel", paramt_int, eth_tx_channel);
900 
  reg_config_param(sec, "rxfile", paramt_str, eth_rxfile);
901 
  reg_config_param(sec, "txfile", paramt_str, eth_txfile);
902 
  reg_config_param(sec, "sockif", paramt_str, eth_sockif);
903 
  reg_config_param(sec, "vapi_id", paramt_int, eth_vapi_id);
904 
}

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