OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 1606

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 1308 phoenix 
#include <netinet/in.h>
33 696 ivang 
 
34 867 markom 
#include "config.h"
35 1350 nogj 
 
36 
#ifdef HAVE_INTTYPES_H
37 
#include <inttypes.h>
38 
#endif
39 
 
40 
#include "port.h"
41 
#include "arch.h"
42 
#include "config.h"
43 696 ivang 
#include "abstract.h"
44 
#include "ethernet_i.h"
45 
#include "dma.h"
46 
#include "sim-config.h"
47 
#include "fields.h"
48 
#include "crc32.h"
49 889 ivang 
#include "vapi.h"
50 1308 phoenix 
#include "pic.h"
51 1372 nogj 
#include "sched.h"
52 1308 phoenix 
#include "debug.h"
53 696 ivang 
 
54 1463 nogj 
DEFAULT_DEBUG_CHANNEL(eth);
55 
 
56 702 ivang 
/* simulator interface */
57 1366 nogj 
static void eth_vapi_read( unsigned long id, unsigned long data, void *dat);
58 696 ivang 
/* register interface */
59 1359 nogj 
static void eth_write32( oraddr_t addr, uint32_t value, void *dat );
60 
static uint32_t eth_read32( oraddr_t addr, void *dat );
61 696 ivang 
/* clock */
62 1372 nogj 
static void eth_controller_tx_clock( void * );
63 
static void eth_controller_rx_clock( void * );
64 696 ivang 
/* utility functions */
65 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
66 
static void eth_skip_rx_file( struct eth_device *, off_t );
67 
static void eth_rx_next_packet( struct eth_device * );
68 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
69 696 ivang 
/* ========================================================================= */
70 702 ivang 
/*  TX LOGIC                                                                 */
71 696 ivang 
/*---------------------------------------------------------------------------*/
72 
 
73 
/*
74 
 * TX clock
75 
 * Responsible for starting and finishing TX
76 
 */
77 1372 nogj 
void eth_controller_tx_clock( void *dat )
78 696 ivang 
{
79 1372 nogj 
    struct eth_device *eth = dat;
80 702 ivang 
    int bAdvance   = 1;
81 867 markom 
#if HAVE_ETH_PHY
82 702 ivang 
    struct sockaddr_ll sll;
83 849 markom 
#endif /* HAVE_ETH_PHY */
84 1463 nogj 
    long nwritten = 0;
85 702 ivang 
    unsigned long read_word;
86 696 ivang 
 
87 
    switch (eth->tx.state) {
88 1372 nogj 
    case ETH_TXSTATE_IDLE:
89 1463 nogj 
        TRACE ("TX - entering state WAIT4BD (%ld)\n", eth->tx.bd_index);
90 1372 nogj 
        eth->tx.state = ETH_TXSTATE_WAIT4BD;
91 702 ivang 
        break;
92 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
93 702 ivang 
        /* Read buffer descriptor */
94 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
95 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
96 
 
97 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
98 
            /*****************/
99 
            /* initialize TX */
100 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
101 
            eth->tx.bytes_sent = 0;
102 
 
103 
            /*   Initialize error status bits */
104 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
105 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
106 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
107 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
108 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
109 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
110 
 
111 
            /* Find out minimum length */
112 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
113 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
114 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
115 
            else
116 
                eth->tx.minimum_length = eth->tx.packet_length;
117 
 
118 
            /* Find out maximum length */
119 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
120 
                eth->tx.maximum_length = eth->tx.packet_length;
121 
            else
122 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
123 
 
124 
            /* Do we need CRC on this packet? */
125 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
126 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
127 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
128 
                eth->tx.add_crc = 1;
129 
            else
130 
                eth->tx.add_crc = 0;
131 
 
132 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
133 
                eth->tx.crc_dly = 1;
134 
            else
135 
                eth->tx.crc_dly = 0;
136 
            /* XXX - For now we skip CRC calculation */
137 
 
138 1463 nogj 
            TRACE( "Ethernet: Starting TX of %lu bytes (min. %u, max. %u)\n",
139 1350 nogj 
                   eth->tx.packet_length, eth->tx.minimum_length,
140 
                   eth->tx.maximum_length );
141 702 ivang 
 
142 
            if (eth->rtx_type == ETH_RTX_FILE) {
143 
                /* write packet length to file */
144 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
145 
            }
146 
 
147 
            /************************************************/
148 
            /* start transmit with reading packet into FIFO */
149 1463 nogj 
                TRACE ("TX - entering state READFIFO\n");
150 702 ivang 
            eth->tx.state = ETH_TXSTATE_READFIFO;
151 
        }
152 
 
153 
        /* stay in this state if (TXEN && !READY) */
154 
        break;
155 696 ivang 
    case ETH_TXSTATE_READFIFO:
156 744 simons 
#if 1
157 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
158 1487 nogj 
            read_word = eval_direct32(eth->tx.bytes_sent + eth->tx.bd_addr, 0, 0);
159 702 ivang 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
160 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
161 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
162 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
163 
            eth->tx.bytes_sent += 4;
164 
        }
165 744 simons 
#else
166 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
167 1487 nogj 
            eth->tx_buff[eth->tx.bytes_sent] = eval_direct8(eth->tx.bytes_sent + eth->tx.bd_addr, 0, 0);
168 744 simons 
            eth->tx.bytes_sent += 1;
169 
        }
170 
#endif
171 702 ivang 
        else {
172 1463 nogj 
            TRACE ("TX - entering state TRANSMIT\n");
173 702 ivang 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
174 
        }
175 
        break;
176 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
177 702 ivang 
        /* send packet */
178 
        switch (eth->rtx_type) {
179 
        case ETH_RTX_FILE:
180 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
181 
            break;
182 867 markom 
#if HAVE_ETH_PHY
183 702 ivang 
        case ETH_RTX_SOCK:
184 
            memset(&sll, 0, sizeof(sll));
185 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
186 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
187 849 markom 
#endif /* HAVE_ETH_PHY */
188 702 ivang 
        }
189 
 
190 
        /* set BD status */
191 
        if (nwritten == eth->tx.packet_length) {
192 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
193 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
194 1463 nogj 
            TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
195 702 ivang 
 
196 1463 nogj 
            TRACE ("TX - entering state WAIT4BD\n");
197 1372 nogj 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
198 1463 nogj 
            TRACE ("send (%ld)bytes OK\n", nwritten);
199 702 ivang 
        }
200 
        else {
201 
            /* XXX - implement retry mechanism here! */
202 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
203 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
204 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
205 1463 nogj 
            TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
206 702 ivang 
 
207 1463 nogj 
            TRACE ("TX - entering state WAIT4BD\n");
208 1372 nogj 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
209 1463 nogj 
            TRACE ("send FAILED!\n");
210 702 ivang 
        }
211 
 
212 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
213 
 
214 889 ivang 
        /* generate OK interrupt */
215 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
216 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
217 
        {
218 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, IRQ ) )
219 
                report_interrupt( eth->mac_int );
220 
        }
221 
 
222 702 ivang 
        /* advance to next BD */
223 
        if (bAdvance) {
224 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
225 
                            eth->tx.bd_index >= ETH_BD_COUNT )
226 
                eth->tx.bd_index = 0;
227 
            else
228 
                eth->tx.bd_index += 2;
229 
        }
230 
 
231 
        break;
232 696 ivang 
    }
233 1372 nogj 
 
234 
    /* Reschedule */
235 1390 nogj 
    SCHED_ADD( eth_controller_tx_clock, dat, 1 );
236 696 ivang 
}
237 
/* ========================================================================= */
238 
 
239 
 
240 
/* ========================================================================= */
241 702 ivang 
/*  RX LOGIC                                                                 */
242 696 ivang 
/*---------------------------------------------------------------------------*/
243 
 
244 
/*
245 
 * RX clock
246 
 * Responsible for starting and finishing RX
247 
 */
248 1372 nogj 
void eth_controller_rx_clock( void *dat )
249 696 ivang 
{
250 1372 nogj 
    struct eth_device *eth = dat;
251 702 ivang 
    long nread;
252 
    unsigned long send_word;
253 
 
254 
 
255 696 ivang 
    switch (eth->rx.state) {
256 
    case ETH_RXSTATE_IDLE:
257 1463 nogj 
        TRACE ("RX - entering state WAIT4BD (%ld)\n", eth->rx.bd_index);
258 1372 nogj 
        eth->rx.state = ETH_RXSTATE_WAIT4BD;
259 702 ivang 
        break;
260 
 
261 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
262 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
263 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
264 
 
265 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
266 
            /*****************/
267 
            /* Initialize RX */
268 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
269 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
270 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
271 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
272 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
273 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
274 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
275 
 
276 1463 nogj 
            TRACE( "Ethernet: Starting RX\n" );
277 702 ivang 
 
278 
            /* Setup file to read from */
279 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
280 
                eth->rx.fd = eth->txfd;
281 
                eth->rx.offset = &(eth->loopback_offset);
282 
            } else {
283 
                eth->rx.fd = eth->rxfd;
284 
                eth->rx.offset = 0;
285 
            }
286 1463 nogj 
            TRACE ("RX - entering state RECV\n");
287 702 ivang 
            eth->rx.state = ETH_RXSTATE_RECV;
288 
        }
289 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
290 1463 nogj 
          TRACE ("RX - entering state IDLE\n");
291 705 ivang 
          eth->rx.state = ETH_RXSTATE_IDLE;
292 
        }
293 
        else {
294 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
295 705 ivang 
            if (nread > 0) {
296 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
297 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
298 
                  report_interrupt(eth->mac_int);
299 702 ivang 
            }
300 
        }
301 
        break;
302 
 
303 696 ivang 
    case ETH_RXSTATE_RECV:
304 702 ivang 
        switch (eth->rtx_type) {
305 
        case ETH_RTX_FILE:
306 
            /* Read packet length */
307 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
308 
                     < sizeof(eth->rx.packet_length) ) {
309 
                /* TODO: just do what real ethernet would do (some kind of error state) */
310 1463 nogj 
                TRACE ("eth_start_rx(): File does not have a packet ready for RX (len = %ld)\n", eth->rx.packet_length );
311 
                sim_done();
312 702 ivang 
                break;
313 
            }
314 
 
315 
            /* Packet must be big enough to hold a header */
316 1244 hpanther 
            if ( eth->rx.packet_length < ETHER_HDR_LEN ){
317 1463 nogj 
                TRACE( "eth_start_rx(): Packet too small\n" );
318 702 ivang 
                eth_rx_next_packet( eth );
319 
 
320 1463 nogj 
                TRACE ("RX - entering state WAIT4BD\n");
321 1372 nogj 
                eth->rx.state = ETH_RXSTATE_WAIT4BD;
322 702 ivang 
                break;
323 
            }
324 
 
325 
            eth->rx.bytes_read = 0;
326 
            eth->rx.bytes_left = eth->rx.packet_length;
327 
 
328 
            /* for now Read entire packet into memory */
329 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
330 844 ivang 
            if ( nread < eth->rx.bytes_left ) {
331 1463 nogj 
                TRACE ("Read %ld from %ld. Error!\n", nread, eth->rx.bytes_left);
332 844 ivang 
                eth->rx.error = 1;
333 
                break;
334 
            }
335 
 
336 
            eth->rx.packet_length = nread;
337 
            eth->rx.bytes_left = nread;
338 
            eth->rx.bytes_read = 0;
339 
 
340 1463 nogj 
            TRACE ("RX - entering state WRITEFIFO\n");
341 844 ivang 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
342 
 
343 702 ivang 
            break;
344 
 
345 
        case ETH_RTX_SOCK:
346 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
347 744 simons 
 
348 1463 nogj 
            if (nread == 0) {
349 
                TRACE("No data read\n");
350 744 simons 
                break;
351 1463 nogj 
            } else if (nread < 0) {
352 744 simons 
                if ( errno != EAGAIN ) {
353 1463 nogj 
                    TRACE ("recv() FAILED!\n");
354 889 ivang 
                    break;
355 
                }
356 1463 nogj 
                else
357 
                    break;
358 889 ivang 
            }
359 744 simons 
            /* If not promiscouos mode, check the destination address */
360 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
361 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
362 
                /* Nothing for now */
363 
                }
364 
 
365 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
366 
                    eth->mac_address[4] != eth->rx_buff[1] ||
367 
                    eth->mac_address[3] != eth->rx_buff[2] ||
368 
                    eth->mac_address[2] != eth->rx_buff[3] ||
369 
                    eth->mac_address[1] != eth->rx_buff[4] ||
370 
                    eth->mac_address[0] != eth->rx_buff[5])
371 889 ivang 
                    break;
372 744 simons 
            }
373 
 
374 841 simons 
            eth->rx.packet_length = nread;
375 
            eth->rx.bytes_left = nread;
376 
            eth->rx.bytes_read = 0;
377 
 
378 1463 nogj 
            TRACE ("RX - entering state WRITEFIFO\n");
379 841 simons 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
380 
 
381 702 ivang 
            break;
382 889 ivang 
        case ETH_RTX_VAPI:
383 1366 nogj 
            break;
384 702 ivang 
        }
385 841 simons 
        break;
386 
 
387 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
388 744 simons 
#if 1
389 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
390 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
391 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
392 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
393 1487 nogj 
        set_direct32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, 0, 0);
394 702 ivang 
        /* update counters */
395 1463 nogj 
        TRACE ("Write %ld, left %ld - %08lXd\n", eth->rx.bytes_read,
396 1350 nogj 
               eth->rx.bytes_left, send_word);
397 702 ivang 
        eth->rx.bytes_left -= 4;
398 
        eth->rx.bytes_read += 4;
399 744 simons 
#else
400 1487 nogj 
        set_direct8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], 0, 0);
401 744 simons 
        eth->rx.bytes_left -= 1;
402 
        eth->rx.bytes_read += 1;
403 
#endif
404 
 
405 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
406 
            /* Write result to bd */
407 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
408 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
409 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
410 1463 nogj 
            TRACE ("ETH_INT_SOURCE = %0lx\n", eth->regs.int_source);
411 702 ivang 
 
412 1068 simons 
            if ( eth->rx.packet_length < (GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) - 4) )
413 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
414 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
415 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
416 
 
417 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
418 
 
419 
            /* advance to next BD */
420 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
421 1018 simons 
                eth->rx.bd_index = eth->regs.tx_bd_num << 1;
422 702 ivang 
            else
423 705 ivang 
                eth->rx.bd_index += 2;
424 702 ivang 
 
425 889 ivang 
            if ( ( TEST_FLAG( eth->regs.int_mask, ETH_INT_MASK, RXB_M ) ) &&
426 
                 ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, IRQ )              ) ) {
427 702 ivang 
                report_interrupt( eth->mac_int );
428 
            }
429 
 
430 
            /* ready to receive next packet */
431 1463 nogj 
                TRACE ("RX - entering state IDLE\n");
432 702 ivang 
            eth->rx.state = ETH_RXSTATE_IDLE;
433 
        }
434 
        break;
435 696 ivang 
    }
436 1372 nogj 
 
437 
    /* Reschedule */
438 1390 nogj 
    SCHED_ADD( eth_controller_rx_clock, dat, 1 );
439 696 ivang 
}
440 702 ivang 
 
441 696 ivang 
/* ========================================================================= */
442 702 ivang 
/* Move to next RX BD */
443 
void eth_rx_next_packet( struct eth_device *eth )
444 
{
445 
    /* Skip any possible leftovers */
446 
    if ( eth->rx.bytes_left )
447 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
448 
}
449 
/* "Skip" bytes in RX file */
450 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
451 
{
452 
    eth->rx.offset += count;
453 
}
454 696 ivang 
 
455 702 ivang 
/*
456 
 * Utility function to read from the ethernet RX file
457 
 * This function moves the file pointer to the current place in the packet before reading
458 
 */
459 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
460 
{
461 
    ssize_t result;
462 
 
463 
    if ( eth->rx.fd <= 0 ) {
464 1463 nogj 
        TRACE( "Ethernet: No RX file\n" );
465 702 ivang 
        return 0;
466 
    }
467 
 
468 
    if ( eth->rx.offset )
469 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
470 1463 nogj 
            TRACE( "Ethernet: Error seeking RX file\n" );
471 702 ivang 
            return 0;
472 
        }
473 696 ivang 
 
474 702 ivang 
    result = read( eth->rx.fd, buf, count );
475 1463 nogj 
    TRACE ("Ethernet: read result = %d \n", result);
476 702 ivang 
    if ( eth->rx.offset && result >= 0 )
477 
        *(eth->rx.offset) += result;
478 
 
479 
    return result;
480 
}
481 
 
482 
/* ========================================================================= */
483 
 
484 696 ivang 
/*
485 702 ivang 
  Reset. Initializes all registers to default and places devices in
486 
         memory address space.
487 696 ivang 
*/
488 1372 nogj 
void eth_reset(void *dat)
489 696 ivang 
{
490 1372 nogj 
    struct eth_device *eth = dat;
491 1308 phoenix 
#if HAVE_ETH_PHY
492 702 ivang 
    int j;
493 
    struct sockaddr_ll sll;
494 849 markom 
#endif /* HAVE_ETH_PHY */
495 702 ivang 
 
496 
    if ( eth->baseaddr != 0 ) {
497 
        switch (eth->rtx_type) {
498 
        case ETH_RTX_FILE:
499 
            /* (Re-)open TX/RX files */
500 
            if ( eth->rxfd > 0 )
501 
                close( eth->rxfd );
502 
            if ( eth->txfd > 0 )
503 
                close( eth->txfd );
504 
            eth->rxfd = eth->txfd = -1;
505 
 
506 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
507 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
508 
            if ( (eth->txfd = open( eth->txfile,
509 1244 hpanther 
                                    O_RDWR | O_CREAT | O_APPEND
510 
 
511 
#if defined(O_SYNC)     /* BSD / Mac OS X manual doesn't know about O_SYNC */
512 
                                                                        | O_SYNC
513 
#endif
514 
                                                                        ,
515 702 ivang 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
516 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
517 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
518 
 
519 
            break;
520 867 markom 
#if HAVE_ETH_PHY
521 702 ivang 
        case ETH_RTX_SOCK:
522 
            /* (Re-)open TX/RX sockets */
523 
            if (eth->rtx_sock != 0)
524 
                break;
525 
 
526 1463 nogj 
            TRACE ("RTX opening socket...\n");
527 702 ivang 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
528 
            if (eth->rtx_sock == -1) {
529 
                fprintf( stderr, "Cannot open rtx_sock.\n");
530 
                return;
531 
            }
532 
 
533 
            /* get interface index number */
534 1463 nogj 
            TRACE ("RTX getting interface...\n");
535 702 ivang 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
536 1372 nogj 
            strncpy(eth->ifr.ifr_name, eth->sockif, IFNAMSIZ);
537 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
538 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
539 
                return;
540 
            }
541 1463 nogj 
            TRACE ("RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
542 702 ivang 
 
543 
            /* Bind to interface... */
544 1463 nogj 
            TRACE ("Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
545 702 ivang 
            memset(&sll, 0xff, sizeof(sll));
546 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
547 
            sll.sll_protocol = htons(ETH_P_ALL);
548 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
549 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
550 
                fprintf( stderr, "Error bind().\n");
551 
                return;
552 
            }
553 
 
554 
            /* first, flush all received packets. */
555 1463 nogj 
            TRACE ("Flush");
556 702 ivang 
            do {
557 
                fd_set fds;
558 
                struct timeval t;
559 
 
560 1463 nogj 
                TRACE( ".");
561 702 ivang 
                FD_ZERO(&fds);
562 
                FD_SET(eth->rtx_sock, &fds);
563 
                memset(&t, 0, sizeof(t));
564 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
565 
                if (j > 0)
566 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
567 
            } while (j);
568 1463 nogj 
            TRACE ("\n");
569 702 ivang 
 
570 
            break;
571 1372 nogj 
#else /* HAVE_ETH_PHY */
572 
        case ETH_RTX_SOCK:
573 
            fprintf (stderr, "Ethernet phy not enabled in this configuration.  Configure with --enable-ethphy.\n");
574 
            exit (1);
575 
            break;
576 849 markom 
#endif /* HAVE_ETH_PHY */
577 702 ivang 
        }
578 
 
579 
        /* Set registers to default values */
580 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
581 
        eth->regs.moder = 0x0000A000;
582 
        eth->regs.ipgt = 0x00000012;
583 
        eth->regs.ipgr1 = 0x0000000C;
584 
        eth->regs.ipgr2 = 0x00000012;
585 
        eth->regs.packetlen = 0x003C0600;
586 
        eth->regs.collconf = 0x000F003F;
587 
        eth->regs.miimoder = 0x00000064;
588 1018 simons 
        eth->regs.tx_bd_num = 0x00000040;
589 702 ivang 
 
590 
        /* Initialize TX/RX status */
591 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
592 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
593 1018 simons 
        eth->rx.bd_index = eth->regs.tx_bd_num << 1;
594 889 ivang 
 
595 
        /* Initialize VAPI */
596 1372 nogj 
        if (eth->base_vapi_id) {
597 
            vapi_install_multi_handler( eth->base_vapi_id, ETH_NUM_VAPI_IDS, eth_vapi_read, dat );
598 889 ivang 
        }
599 702 ivang 
    }
600 
}
601 
/* ========================================================================= */
602 
 
603 
 
604 696 ivang 
/*
605 
  Print register values on stdout
606 
*/
607 1372 nogj 
void eth_status( void *dat )
608 696 ivang 
{
609 1372 nogj 
    struct eth_device *eth = dat;
610 696 ivang 
 
611 1372 nogj 
    PRINTF( "\nEthernet MAC at 0x%"PRIxADDR":\n", eth->baseaddr );
612 
    PRINTF( "MODER        : 0x%08lX\n", eth->regs.moder );
613 
    PRINTF( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
614 
    PRINTF( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
615 
    PRINTF( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
616 
    PRINTF( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
617 
    PRINTF( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
618 
    PRINTF( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
619 
    PRINTF( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
620 
    PRINTF( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
621 
    PRINTF( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
622 
    PRINTF( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
623 
    PRINTF( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
624 
    PRINTF( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
625 
    PRINTF( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
626 
    PRINTF( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
627 
    PRINTF( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
628 
    PRINTF( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
629 
           eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
630 
           eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
631 
    PRINTF( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
632 
    PRINTF( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
633 696 ivang 
}
634 
/* ========================================================================= */
635 
 
636 
 
637 
/*
638 
  Read a register
639 
*/
640 1359 nogj 
uint32_t eth_read32( oraddr_t addr, void *dat )
641 696 ivang 
{
642 1372 nogj 
    struct eth_device *eth = dat;
643 696 ivang 
 
644 
    switch( addr ) {
645 
    case ETH_MODER: return eth->regs.moder;
646 
    case ETH_INT_SOURCE: return eth->regs.int_source;
647 
    case ETH_INT_MASK: return eth->regs.int_mask;
648 
    case ETH_IPGT: return eth->regs.ipgt;
649 
    case ETH_IPGR1: return eth->regs.ipgr1;
650 
    case ETH_IPGR2: return eth->regs.ipgr2;
651 
    case ETH_PACKETLEN: return eth->regs.packetlen;
652 
    case ETH_COLLCONF: return eth->regs.collconf;
653 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
654 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
655 
    case ETH_MIIMODER: return eth->regs.miimoder;
656 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
657 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
658 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
659 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
660 
    case ETH_MIISTATUS: return eth->regs.miistatus;
661 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
662 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
663 
                               (((unsigned long)eth->mac_address[1]) << 8) |
664 
                                 (unsigned long)eth->mac_address[0];
665 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
666 702 ivang 
                                 (unsigned long)eth->mac_address[4];
667 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
668 
    case ETH_HASH1: return eth->regs.hash1;
669 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
670 696 ivang 
    }
671 
 
672 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
673 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
674 696 ivang 
 
675 1350 nogj 
    PRINTF( "eth_read32( 0x%"PRIxADDR" ): Illegal address\n",
676 
            addr + eth->baseaddr );
677 696 ivang 
    return 0;
678 
}
679 
/* ========================================================================= */
680 
 
681 
 
682 
/*
683 
  Write a register
684 
*/
685 1359 nogj 
void eth_write32( oraddr_t addr, uint32_t value, void *dat )
686 696 ivang 
{
687 1372 nogj 
    struct eth_device *eth = dat;
688 
 
689 696 ivang 
    switch( addr ) {
690 1372 nogj 
    case ETH_MODER:
691 
 
692 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) &&
693 
             TEST_FLAG( value, ETH_MODER, RXEN) )
694 1390 nogj 
            SCHED_ADD( eth_controller_rx_clock, dat, 1 );
695 1372 nogj 
        else if ( !TEST_FLAG( value, ETH_MODER, RXEN) )
696 
            SCHED_FIND_REMOVE( eth_controller_rx_clock, dat);
697 
 
698 
        if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN) &&
699 
             TEST_FLAG( value, ETH_MODER, TXEN) )
700 1390 nogj 
            SCHED_ADD( eth_controller_tx_clock, dat, 1 );
701 1372 nogj 
        else if ( !TEST_FLAG( value, ETH_MODER, TXEN) )
702 
            SCHED_FIND_REMOVE( eth_controller_tx_clock, dat);
703 
 
704 
        eth->regs.moder = value;
705 
 
706 
        if (TEST_FLAG(value, ETH_MODER, RST))
707 
            eth_reset( dat );
708 
        return;
709 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
710 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
711 
    case ETH_IPGT: eth->regs.ipgt = value; return;
712 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
713 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
714 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
715 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
716 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
717 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
718 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
719 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
720 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
721 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
722 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
723 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
724 
    case ETH_MAC_ADDR0:
725 702 ivang 
        eth->mac_address[0] = value & 0xFF;
726 
        eth->mac_address[1] = (value >> 8) & 0xFF;
727 
        eth->mac_address[2] = (value >> 16) & 0xFF;
728 
        eth->mac_address[3] = (value >> 24) & 0xFF;
729 
        return;
730 696 ivang 
    case ETH_MAC_ADDR1:
731 702 ivang 
        eth->mac_address[4] = value & 0xFF;
732 
        eth->mac_address[5] = (value >> 8) & 0xFF;
733 
        return;
734 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
735 
    case ETH_HASH1: eth->regs.hash1 = value; return;
736 702 ivang 
 
737 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
738 696 ivang 
    }
739 
 
740 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
741 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
742 
        return;
743 696 ivang 
    }
744 
 
745 1350 nogj 
    PRINTF( "eth_write32( 0x%"PRIxADDR" ): Illegal address\n",
746 
            addr + eth->baseaddr );
747 696 ivang 
    return;
748 
}
749 
/* ========================================================================= */
750 
 
751 
 
752 889 ivang 
/*
753 
 *   VAPI connection to outside
754 
 */
755 1366 nogj 
static void eth_vapi_read (unsigned long id, unsigned long data, void *dat)
756 889 ivang 
{
757 
    unsigned long which;
758 1372 nogj 
    struct eth_device *eth = dat;
759 889 ivang 
 
760 1372 nogj 
    which = id - eth->base_vapi_id;
761 
 
762 1463 nogj 
    TRACE( "ETH: id %08lx, data %08lx\n", id, data );
763 889 ivang 
 
764 
    if ( !eth ) {
765 1463 nogj 
        TRACE( "ETH: VAPI ID %08lx is not ours!\n", id );
766 889 ivang 
        return;
767 
    }
768 
 
769 
    switch( which ) {
770 
    case ETH_VAPI_DATA:
771 
        break;
772 
    case ETH_VAPI_CTRL:
773 
        break;
774 
    }
775 
}
776 
/* ========================================================================= */
777 
 
778 
 
779 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
780 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
781 
{
782 1018 simons 
    eth->regs.tx_bd_num = value & 0xFF;
783 
    eth->rx.bd_index = eth->regs.tx_bd_num << 1;
784 702 ivang 
}
785 1372 nogj 
 
786 702 ivang 
/* ========================================================================= */
787 
 
788 1372 nogj 
/*-----------------------------------------------[ Ethernet configuration ]---*/
789 
void eth_baseaddr(union param_val val, void *dat)
790 696 ivang 
{
791 1372 nogj 
  struct eth_device *eth = dat;
792 
  eth->baseaddr = val.addr_val;
793 696 ivang 
}
794 889 ivang 
 
795 1372 nogj 
void eth_dma(union param_val val, void *dat)
796 889 ivang 
{
797 1372 nogj 
  struct eth_device *eth = dat;
798 
  eth->dma = val.addr_val;
799 889 ivang 
}
800 1358 nogj 
 
801 1372 nogj 
void eth_rtx_type(union param_val val, void *dat)
802 
{
803 
  struct eth_device *eth = dat;
804 
  eth->rtx_type = val.int_val;
805 1358 nogj 
}
806 
 
807 1372 nogj 
void eth_rx_channel(union param_val val, void *dat)
808 
{
809 
  struct eth_device *eth = dat;
810 
  eth->rx_channel = val.int_val;
811 1358 nogj 
}
812 
 
813 1372 nogj 
void eth_tx_channel(union param_val val, void *dat)
814 
{
815 
  struct eth_device *eth = dat;
816 
  eth->tx_channel = val.int_val;
817 1358 nogj 
}
818 
 
819 1372 nogj 
void eth_rxfile(union param_val val, void *dat)
820 
{
821 
  struct eth_device *eth = dat;
822 
  if(!(eth->rxfile = strdup(val.str_val))) {
823 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
824 
    exit(-1);
825 
  }
826 1358 nogj 
}
827 
 
828 
void eth_txfile(union param_val val, void *dat)
829 
{
830 1372 nogj 
  struct eth_device *eth = dat;
831 
  if(!(eth->txfile = strdup(val.str_val))) {
832 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
833 
    exit(-1);
834 
  }
835 1358 nogj 
}
836 
 
837 
void eth_sockif(union param_val val, void *dat)
838 
{
839 1372 nogj 
  struct eth_device *eth = dat;
840 
  if(!(eth->sockif = strdup(val.str_val))) {
841 
    fprintf(stderr, "Peripheral Ethernet: Run out of memory\n");
842 
    exit(-1);
843 
  }
844 1358 nogj 
}
845 
 
846 
void eth_irq(union param_val val, void *dat)
847 
{
848 1372 nogj 
  struct eth_device *eth = dat;
849 
  eth->mac_int = val.int_val;
850 1358 nogj 
}
851 
 
852 
void eth_vapi_id(union param_val val, void *dat)
853 
{
854 1372 nogj 
  struct eth_device *eth = dat;
855 
  eth->base_vapi_id = val.int_val;
856 1358 nogj 
}
857 
 
858 1461 nogj 
void eth_enabled(union param_val val, void *dat)
859 
{
860 
  struct eth_device *eth = dat;
861 
  eth->enabled = val.int_val;
862 
}
863 
 
864 1372 nogj 
void *eth_sec_start(void)
865 
{
866 
  struct eth_device *new = malloc(sizeof(struct eth_device));
867 
 
868 
  if(!new) {
869 
    fprintf(stderr, "Peripheral Eth: Run out of memory\n");
870 
    exit(-1);
871 
  }
872 
 
873 1606 phoenix 
  memset(new, 0, sizeof(struct eth_device));
874 1461 nogj 
  new->enabled = 1;
875 
 
876 1372 nogj 
  return new;
877 
}
878 
 
879 
void eth_sec_end(void *dat)
880 
{
881 
  struct eth_device *eth = dat;
882 1486 nogj 
  struct mem_ops ops;
883 1372 nogj 
 
884 1461 nogj 
  if(!eth->enabled) {
885 
    free(dat);
886 
    return;
887 
  }
888 
 
889 1486 nogj 
  memset(&ops, 0, sizeof(struct mem_ops));
890 
 
891 
  ops.readfunc32 = eth_read32;
892 
  ops.writefunc32 = eth_write32;
893 
  ops.read_dat32 = dat;
894 
  ops.write_dat32 = dat;
895 
 
896 
  /* FIXME: Correct delay? */
897 
  ops.delayr = 2;
898 
  ops.delayw = 2;
899 
  reg_mem_area( eth->baseaddr, ETH_ADDR_SPACE, 0, &ops );
900 1372 nogj 
  reg_sim_stat( eth_status, dat );
901 
  reg_sim_reset( eth_reset, dat );
902 
}
903 
 
904 1358 nogj 
void reg_ethernet_sec(void)
905 
{
906 1372 nogj 
  struct config_section *sec = reg_config_sec("ethernet", eth_sec_start, eth_sec_end);
907 1358 nogj 
 
908 
  reg_config_param(sec, "irq", paramt_int, eth_irq);
909 1461 nogj 
  reg_config_param(sec, "enabled", paramt_int, eth_enabled);
910 1598 nogj 
  reg_config_param(sec, "baseaddr", paramt_addr, eth_baseaddr);
911 1358 nogj 
  reg_config_param(sec, "dma", paramt_int, eth_dma);
912 
  reg_config_param(sec, "rtx_type", paramt_int, eth_rtx_type);
913 
  reg_config_param(sec, "rx_channel", paramt_int, eth_rx_channel);
914 
  reg_config_param(sec, "tx_channel", paramt_int, eth_tx_channel);
915 
  reg_config_param(sec, "rxfile", paramt_str, eth_rxfile);
916 
  reg_config_param(sec, "txfile", paramt_str, eth_txfile);
917 
  reg_config_param(sec, "sockif", paramt_str, eth_sockif);
918 
  reg_config_param(sec, "vapi_id", paramt_int, eth_vapi_id);
919 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.