1 |
257 |
erez |
/* ethernet.h -- Definition of types and structures for Ethernet MAC
|
2 |
|
|
Copyright (C) 2001 Erez Volk, erez@mailandnews.comopencores.org
|
3 |
|
|
|
4 |
|
|
This file is part of OpenRISC 1000 Architectural Simulator.
|
5 |
|
|
|
6 |
|
|
This program is free software; you can redistribute it and/or modify
|
7 |
|
|
it under the terms of the GNU General Public License as published by
|
8 |
|
|
the Free Software Foundation; either version 2 of the License, or
|
9 |
|
|
(at your option) any later version.
|
10 |
|
|
|
11 |
|
|
This program is distributed in the hope that it will be useful,
|
12 |
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 |
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
14 |
|
|
GNU General Public License for more details.
|
15 |
|
|
|
16 |
|
|
You should have received a copy of the GNU General Public License
|
17 |
|
|
along with this program; if not, write to the Free Software
|
18 |
|
|
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
19 |
|
|
*/
|
20 |
|
|
|
21 |
346 |
erez |
#ifndef __OR1KSIM_PERIPHERAL_ETHERNET_H
|
22 |
|
|
#define __OR1KSIM_PERIPHERAL_ETHERNET_H
|
23 |
|
|
|
24 |
257 |
erez |
/* Exported function prototypes */
|
25 |
|
|
void eth_reset( void );
|
26 |
|
|
void eth_clock( void );
|
27 |
|
|
void eth_status( void );
|
28 |
|
|
|
29 |
|
|
|
30 |
|
|
/* Address space required by one Ethernet MAC */
|
31 |
|
|
#define ETH_ADDR_SPACE 0x1000
|
32 |
|
|
|
33 |
|
|
/* Relative Register Addresses */
|
34 |
444 |
erez |
#define ETH_MODER (4 * 0x00)
|
35 |
257 |
erez |
#define ETH_INT_SOURCE (4 * 0x01)
|
36 |
|
|
#define ETH_INT_MASK (4 * 0x02)
|
37 |
444 |
erez |
#define ETH_IPGT (4 * 0x03)
|
38 |
|
|
#define ETH_IPGR1 (4 * 0x04)
|
39 |
|
|
#define ETH_IPGR2 (4 * 0x05)
|
40 |
257 |
erez |
#define ETH_PACKETLEN (4 * 0x06)
|
41 |
|
|
#define ETH_COLLCONF (4 * 0x07)
|
42 |
418 |
erez |
#define ETH_TX_BD_NUM (4 * 0x08)
|
43 |
257 |
erez |
#define ETH_CTRLMODER (4 * 0x09)
|
44 |
|
|
#define ETH_MIIMODER (4 * 0x0A)
|
45 |
|
|
#define ETH_MIICOMMAND (4 * 0x0B)
|
46 |
|
|
#define ETH_MIIADDRESS (4 * 0x0C)
|
47 |
|
|
#define ETH_MIITX_DATA (4 * 0x0D)
|
48 |
|
|
#define ETH_MIIRX_DATA (4 * 0x0E)
|
49 |
|
|
#define ETH_MIISTATUS (4 * 0x0F)
|
50 |
|
|
#define ETH_MAC_ADDR0 (4 * 0x10)
|
51 |
|
|
#define ETH_MAC_ADDR1 (4 * 0x11)
|
52 |
|
|
|
53 |
|
|
/* Where BD's are stored */
|
54 |
|
|
#define ETH_BD_BASE 0x400
|
55 |
|
|
#define ETH_BD_COUNT 0x100
|
56 |
|
|
#define ETH_BD_SPACE (4 * ETH_BD_COUNT)
|
57 |
|
|
|
58 |
|
|
/* Where to point DMA to transmit/receive */
|
59 |
|
|
#define ETH_DMA_RX_TX 0x800
|
60 |
|
|
|
61 |
|
|
/* Field definitions for MODER */
|
62 |
|
|
#define ETH_MODER_DMAEN_OFFSET 17
|
63 |
|
|
#define ETH_MODER_RECSMALL_OFFSET 16
|
64 |
|
|
#define ETH_MODER_PAD_OFFSET 15
|
65 |
|
|
#define ETH_MODER_HUGEN_OFFSET 14
|
66 |
|
|
#define ETH_MODER_CRCEN_OFFSET 13
|
67 |
|
|
#define ETH_MODER_DLYCRCEN_OFFSET 12
|
68 |
|
|
#define ETH_MODER_RST_OFFSET 11
|
69 |
|
|
#define ETH_MODER_FULLD_OFFSET 10
|
70 |
|
|
#define ETH_MODER_EXDFREN_OFFSET 9
|
71 |
|
|
#define ETH_MODER_NOBCKOF_OFFSET 8
|
72 |
|
|
#define ETH_MODER_LOOPBCK_OFFSET 7
|
73 |
695 |
ivang |
#define ETH_MODER_IFG_OFFSET 6
|
74 |
257 |
erez |
#define ETH_MODER_PRO_OFFSET 5
|
75 |
|
|
#define ETH_MODER_IAM_OFFSET 4
|
76 |
|
|
#define ETH_MODER_BRO_OFFSET 3
|
77 |
|
|
#define ETH_MODER_NOPRE_OFFSET 2
|
78 |
|
|
#define ETH_MODER_TXEN_OFFSET 1
|
79 |
|
|
#define ETH_MODER_RXEN_OFFSET 0
|
80 |
|
|
|
81 |
|
|
/* Field definitions for INT_SOURCE */
|
82 |
705 |
ivang |
#define ETH_INT_SOURCE_RXC_OFFSET 6
|
83 |
|
|
#define ETH_INT_SOURCE_TXC_OFFSET 5
|
84 |
257 |
erez |
#define ETH_INT_SOURCE_BUSY_OFFSET 4
|
85 |
705 |
ivang |
#define ETH_INT_SOURCE_RXE_OFFSET 3
|
86 |
257 |
erez |
#define ETH_INT_SOURCE_RXB_OFFSET 2
|
87 |
|
|
#define ETH_INT_SOURCE_TXE_OFFSET 1
|
88 |
|
|
#define ETH_INT_SOURCE_TXB_OFFSET 0
|
89 |
|
|
|
90 |
|
|
/* Field definitions for INT_MASK */
|
91 |
705 |
ivang |
#define ETH_INT_MASK_RXC_M_OFFSET 6
|
92 |
|
|
#define ETH_INT_MASK_TXC_M_OFFSET 5
|
93 |
257 |
erez |
#define ETH_INT_MASK_BUSY_M_OFFSET 4
|
94 |
705 |
ivang |
#define ETH_INT_MASK_RXE_M_OFFSET 3
|
95 |
257 |
erez |
#define ETH_INT_MASK_RXB_M_OFFSET 2
|
96 |
|
|
#define ETH_INT_MASK_TXE_M_OFFSET 1
|
97 |
|
|
#define ETH_INT_MASK_TXB_M_OFFSET 0
|
98 |
|
|
|
99 |
|
|
/* Field definitions for PACKETLEN */
|
100 |
|
|
#define ETH_PACKETLEN_MINFL_OFFSET 16
|
101 |
|
|
#define ETH_PACKETLEN_MINFL_WIDTH 16
|
102 |
|
|
#define ETH_PACKETLEN_MAXFL_OFFSET 0
|
103 |
|
|
#define ETH_PACKETLEN_MAXFL_WIDTH 16
|
104 |
|
|
|
105 |
695 |
ivang |
/* Field definitions for COLLCONF */
|
106 |
|
|
#define ETH_COLLCONF_MAXRET_OFFSET 16
|
107 |
|
|
#define ETH_COLLCONF_MAXRET_WIDTH 4
|
108 |
|
|
#define ETH_COLLCONF_COLLVALID_OFFSET 0
|
109 |
|
|
#define ETH_COLLCONF_COLLVALID_WIDTH 6
|
110 |
|
|
|
111 |
|
|
/* Field definitions for CTRLMODER */
|
112 |
|
|
#define ETH_CMODER_TXFLOW_OFFSET 2
|
113 |
|
|
#define ETH_CMODER_RXFLOW_OFFSET 1
|
114 |
|
|
#define ETH_CMODER_PASSALL_OFFSET 0
|
115 |
|
|
|
116 |
|
|
/* Field definitions for MIIMODER */
|
117 |
705 |
ivang |
#define ETH_MIIMODER_MRST_OFFSET 9
|
118 |
695 |
ivang |
#define ETH_MIIMODER_NOPRE_OFFSET 8
|
119 |
|
|
#define ETH_MIIMODER_CLKDIV_OFFSET 0
|
120 |
|
|
#define ETH_MIIMODER_CLKDIV_WIDTH 8
|
121 |
|
|
|
122 |
|
|
/* Field definitions for MIICOMMAND */
|
123 |
|
|
#define ETH_MIICOMM_WCDATA_OFFSET 2
|
124 |
|
|
#define ETH_MIICOMM_RSTAT_OFFSET 1
|
125 |
|
|
#define ETH_MIICOMM_SCANS_OFFSET 0
|
126 |
|
|
|
127 |
|
|
/* Field definitions for MIIADDRESS */
|
128 |
|
|
#define ETH_MIIADDR_RGAD_OFFSET 8
|
129 |
|
|
#define ETH_MIIADDR_RGAD_WIDTH 5
|
130 |
|
|
#define ETH_MIIADDR_FIAD_OFFSET 0
|
131 |
|
|
#define ETH_MIIADDR_FIAD_WIDTH 5
|
132 |
|
|
|
133 |
|
|
/* Field definitions for MIISTATUS */
|
134 |
705 |
ivang |
#define ETH_MIISTAT_NVALID_OFFSET 1
|
135 |
|
|
#define ETH_MIISTAT_BUSY_OFFSET 1
|
136 |
695 |
ivang |
#define ETH_MIISTAT_FAIL_OFFSET 0
|
137 |
|
|
|
138 |
257 |
erez |
/* Field definitions for TX buffer descriptors */
|
139 |
|
|
#define ETH_TX_BD_LENGTH_OFFSET 16
|
140 |
|
|
#define ETH_TX_BD_LENGTH_WIDTH 16
|
141 |
|
|
#define ETH_TX_BD_READY_OFFSET 15
|
142 |
|
|
#define ETH_TX_BD_INTERRUPT_OFFSET 14
|
143 |
|
|
#define ETH_TX_BD_WRAP_OFFSET 13
|
144 |
|
|
#define ETH_TX_BD_PAD_OFFSET 12
|
145 |
|
|
#define ETH_TX_BD_CRC_OFFSET 11
|
146 |
|
|
#define ETH_TX_BD_LAST_OFFSET 10
|
147 |
|
|
#define ETH_TX_BD_PAUSE_OFFSET 9
|
148 |
695 |
ivang |
#define ETH_TX_BD_UNDERRUN_OFFSET 8
|
149 |
|
|
#define ETH_TX_BD_RETRY_OFFSET 4
|
150 |
257 |
erez |
#define ETH_TX_BD_RETRY_WIDTH 4
|
151 |
695 |
ivang |
#define ETH_TX_BD_RETRANSMIT_OFFSET 3
|
152 |
|
|
#define ETH_TX_BD_COLLISION_OFFSET 2
|
153 |
|
|
#define ETH_TX_BD_DEFER_OFFSET 1
|
154 |
|
|
#define ETH_TX_BD_NO_CARRIER_OFFSET 0
|
155 |
257 |
erez |
|
156 |
695 |
ivang |
|
157 |
257 |
erez |
/* Field definitions for RX buffer descriptors */
|
158 |
|
|
#define ETH_RX_BD_LENGTH_OFFSET 16
|
159 |
|
|
#define ETH_RX_BD_LENGTH_WIDTH 16
|
160 |
702 |
ivang |
#define ETH_RX_BD_READY_OFFSET 15
|
161 |
257 |
erez |
#define ETH_RX_BD_INTERRUPT_OFFSET 14
|
162 |
|
|
#define ETH_RX_BD_WRAP_OFFSET 13
|
163 |
695 |
ivang |
#define ETH_RX_BD_MISS_OFFSET 7
|
164 |
|
|
#define ETH_RX_BD_UVERRUN_OFFSET 6
|
165 |
|
|
#define ETH_RX_BD_INVALID_OFFSET 5
|
166 |
|
|
#define ETH_RX_BD_DRIBBLE_OFFSET 4
|
167 |
|
|
#define ETH_RX_BD_TOOBIG_OFFSET 3
|
168 |
|
|
#define ETH_RX_BD_TOOSHORT_OFFSET 2
|
169 |
|
|
#define ETH_RX_BD_CRC_OFFSET 1
|
170 |
702 |
ivang |
#define ETH_RX_BD_COLLISION_OFFSET 0
|
171 |
257 |
erez |
|
172 |
346 |
erez |
#endif /* __OR1KSIM_PERIPHERAL_ETHERNET_H */
|