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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [peripheral/] [mc.c] - Blame information for rev 1373

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1 239 markom 
/* mc.c -- Simulation of Memory Controller
2 
         Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
3 
 
4 
         This file is part of OpenRISC 1000 Architectural Simulator.
5 
 
6 
         This program is free software; you can redistribute it and/or modify
7 
         it under the terms of the GNU General Public License as published by
8 
         the Free Software Foundation; either version 2 of the License, or
9 
         (at your option) any later version.
10 
 
11 
         This program is distributed in the hope that it will be useful,
12 
         but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.    See the
14 
         GNU General Public License for more details.
15 
 
16 
         You should have received a copy of the GNU General Public License
17 
         along with this program; if not, write to the Free Software
18 
         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 
*/
20 
 
21 
/* Enable memory controller, via:
22 
  section mc
23 
    enable = 1
24 
    POC = 0x13243545
25 
  end
26 
 
27 261 markom 
   Limitations:
28 
    - memory refresh is not simulated
29 742 ivang 
*/
30 239 markom 
 
31 1308 phoenix 
#include <string.h>
32 
 
33 1350 nogj 
#include "config.h"
34 
 
35 
#ifdef HAVE_INTTYPES_H
36 
#include <inttypes.h>
37 
#endif
38 
 
39 
#include "port.h"
40 
#include "arch.h"
41 239 markom 
#include "mc.h"
42 
#include "abstract.h"
43 261 markom 
#include "sim-config.h"
44 1308 phoenix 
#include "debug.h"
45 261 markom 
 
46 539 simons 
extern struct dev_memarea *dev_list;
47 
 
48 1373 nogj 
void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc) {
49 539 simons 
  struct dev_memarea *mem_dev = dev_list;
50 
 
51 
  while (mem_dev) {
52 
    if (mem_dev->chip_select == cs) {
53 1373 nogj 
      mem_dev->addr_mask = mc->ba_mask << 22;
54 970 simons 
      mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) << 22;
55 543 simons 
      mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;
56 539 simons 
 
57 
      if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
58 
        mem_dev->delayr = (tms & 0xff) + ((tms >> 8) & 0x0f);
59 
        mem_dev->delayw = ((tms >> 12)  & 0x0f) + ((tms >> 16) & 0x0f) + ((tms >> 20) & 0x3f);
60 
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
61 
        mem_dev->delayr = 3 + ((tms >> 4) & 0x03);
62 
        mem_dev->delayw = 3 + ((tms >> 4) & 0x03);
63 
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
64 
        mem_dev->delayr = 2;
65 
        mem_dev->delayw = 2;
66 
      } else if ((csc >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
67 
        mem_dev->delayr = 2;
68 
        mem_dev->delayw = 2;
69 
      }
70 543 simons 
      return;
71 539 simons 
    }
72 
    mem_dev = mem_dev->next;
73 
  }
74 261 markom 
}
75 
 
76 
/* Set a specific MC register with value. */
77 1359 nogj 
void mc_write_word(oraddr_t addr, uint32_t value, void *dat)
78 261 markom 
{
79 1373 nogj 
    struct mc *mc = dat;
80 261 markom 
        int chipsel;
81 
 
82 1350 nogj 
        debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);
83 261 markom 
 
84 1373 nogj 
  addr -= mc->baseaddr;
85 261 markom 
 
86 
        switch (addr) {
87 
          case MC_CSR:
88 1373 nogj 
            mc->csr = value;
89 261 markom 
            break;
90 
          case MC_POC:
91 
            fprintf (stderr, "warning: write to MC's POC register!");
92 
            break;
93 
          case MC_BA_MASK:
94 1373 nogj 
            mc->ba_mask = value & MC_BA_MASK_VALID;
95 543 simons 
      for (chipsel = 0; chipsel < N_CE; chipsel++)
96 1373 nogj 
        set_csc_tms (chipsel, mc->csc[chipsel], mc->tms[chipsel], mc);
97 261 markom 
            break;
98 
                default:
99 
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
100 
                    addr -= MC_CSC(0);
101 
                    if ((addr >> 2) & 1)
102 1373 nogj 
                      mc->tms[addr >> 3] = value;
103 261 markom 
                    else
104 1373 nogj 
                      mc->csc[addr >> 3] = value;
105 261 markom 
 
106 1373 nogj 
                    set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);
107 261 markom 
                    break;
108 
                  } else
109 1373 nogj 
                        debug(1, "write out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
110 261 markom 
        }
111 
}
112 
 
113 
/* Read a specific MC register. */
114 1359 nogj 
uint32_t mc_read_word(oraddr_t addr, void *dat)
115 261 markom 
{
116 1373 nogj 
    struct mc *mc = dat;
117 1350 nogj 
        uint32_t value = 0;
118 261 markom 
 
119 1350 nogj 
        debug(5, "mc_read_word(%"PRIxADDR")", addr);
120 261 markom 
 
121 1373 nogj 
  addr -= mc->baseaddr;
122 261 markom 
 
123 
        switch (addr) {
124 
          case MC_CSR:
125 1373 nogj 
            value = mc->csr;
126 261 markom 
            break;
127 
          case MC_POC:
128 1373 nogj 
            value = mc->poc;
129 261 markom 
            break;
130 
          case MC_BA_MASK:
131 1373 nogj 
            value = mc->ba_mask;
132 261 markom 
            break;
133 
                default:
134 
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
135 
                    addr -= MC_CSC(0);
136 
                    if ((addr >> 2) & 1)
137 1373 nogj 
                      value = mc->tms[addr >> 3];
138 261 markom 
                    else
139 1373 nogj 
                      value = mc->csc[addr >> 3];
140 261 markom 
                  } else
141 1373 nogj 
                        debug(1, " read out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
142 261 markom 
            break;
143 
        }
144 1350 nogj 
        debug(5, " value(%"PRIx32")\n", value);
145 261 markom 
        return value;
146 
}
147 
 
148 
/* Read POC register and init memory controler regs. */
149 1373 nogj 
void mc_reset(void *dat)
150 261 markom 
{
151 1373 nogj 
  struct mc *mc = dat;
152 543 simons 
  struct dev_memarea *mem_dev = dev_list;
153 
 
154 1373 nogj 
  PRINTF("Resetting memory controller.\n");
155 261 markom 
 
156 1373 nogj 
  memset(mc->csc, 0, sizeof(mc->csc));
157 
  memset(mc->tms, 0, sizeof(mc->tms));
158 539 simons 
 
159 1373 nogj 
  mc->csr = 0;
160 
  mc->ba_mask = 0;
161 539 simons 
 
162 1373 nogj 
  /* Set CS0 */
163 
  mc->csc[0] = (((mc->poc & 0x0c) >> 2) << MC_CSC_MEMTYPE_OFFSET) | ((mc->poc & 0x03) << MC_CSC_BW_OFFSET) | 1;
164 539 simons 
 
165 1373 nogj 
  if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
166 
    mc->tms[0] = MC_TMS_ASYNC_VALID;
167 
  } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
168 
    mc->tms[0] = MC_TMS_SDRAM_VALID;
169 
  } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
170 
    mc->tms[0] = MC_TMS_SSRAM_VALID;
171 
  } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
172 
    mc->tms[0] = MC_TMS_SYNC_VALID;
173 
  }
174 543 simons 
 
175 1373 nogj 
  while (mem_dev) {
176 
    mem_dev->valid = 0;
177 
    mem_dev = mem_dev->next;
178 261 markom 
  }
179 
 
180 1373 nogj 
  set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
181 261 markom 
}
182 742 ivang 
 
183 1373 nogj 
void mc_status(void *dat)
184 742 ivang 
{
185 1373 nogj 
    struct mc *mc = dat;
186 742 ivang 
    int i;
187 
 
188 1373 nogj 
    PRINTF( "\nMemory Controller at 0x%"PRIxADDR":\n", mc->baseaddr );
189 
    PRINTF( "POC: 0x%08lX\n", mc->poc );
190 
    PRINTF( "BAS: 0x%08lX\n", mc->ba_mask );
191 
    PRINTF( "CSR: 0x%08lX\n", mc->csr );
192 742 ivang 
 
193 
    for (i=0; i<N_CE; i++) {
194 1373 nogj 
        PRINTF( "CE %02d -  CSC: 0x%08lX  TMS: 0x%08lX\n", i, mc->csc[i],
195 
               mc->tms[i]);
196 742 ivang 
    }
197 
}
198 1358 nogj 
 
199 
/*-----------------------------------------------------[ MC configuration }---*/
200 
void mc_enabled(union param_val val, void *dat)
201 
{
202 1373 nogj 
  struct mc *mc = dat;
203 
  mc->enabled = val.int_val;
204 1358 nogj 
}
205 
 
206 
void mc_baseaddr(union param_val val, void *dat)
207 
{
208 1373 nogj 
  struct mc *mc = dat;
209 
  mc->baseaddr = val.addr_val;
210 1358 nogj 
}
211 
 
212 
void mc_POC(union param_val val, void *dat)
213 
{
214 1373 nogj 
  struct mc *mc = dat;
215 
  mc->poc = val.int_val;
216 1358 nogj 
}
217 
 
218 1373 nogj 
void *mc_sec_start(void)
219 
{
220 
  struct mc *new = malloc(sizeof(struct mc));
221 
 
222 
  if(!new) {
223 
    fprintf(stderr, "Peripheral MC: Run out of memory\n");
224 
    exit(-1);
225 
  }
226 
 
227 
  new->enabled = 0;
228 
 
229 
  return new;
230 
}
231 
 
232 
void mc_sec_end(void *dat)
233 
{
234 
  struct mc *mc = dat;
235 
 
236 
  if(mc->enabled) {
237 
    register_memoryarea(mc->baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word, mc_write_word, dat);
238 
    reg_sim_reset(mc_reset, dat);
239 
    reg_sim_stat(mc_status, dat);
240 
  }
241 
}
242 
 
243 1358 nogj 
void reg_mc_sec(void)
244 
{
245 1373 nogj 
  struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);
246 1358 nogj 
 
247 
  reg_config_param(sec, "enabled", paramt_int, mc_enabled);
248 
  reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);
249 
  reg_config_param(sec, "POC", paramt_int, mc_POC);
250 
}

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