OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [README] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 97 lampret
This directory includes some test case programs that should be used to verify correct operation
2
of the or1ksim, OR32 GCC and OR32 GNU Binutils.
3
 
4 341 markom
All programs are built and checked by:
5 369 simons
 
6 1081 simons
./configure --target=or32-uclinux
7 341 markom
make all check
8 369 simons
 
9 341 markom
You need to have all GNU OR32 tools installed and in the path.
10 97 lampret
 
11
!!! For all test cases, or1ksim should be built with ONLY_VIRTUAL_MACHINE undefined in
12
cpu/or1k/except.h !!!
13
 
14 341 markom
All tests should exit with:
15 195 simons
MTSPR(0x1234, deaddead);
16
syscall exit(0)
17
 
18 341 markom
If the test fails, it should print as much output as possible about the failure.
19 195 simons
 
20 341 markom
dhry: Dhrystone 2.1: a benchmark modified to use simulator's timing facility.
21
basic: a test for all instructions and all GPRs.
22
test1: a test for "all" instructions and their combinations.
23
pic: a test for PIC and TICK timer. All three modes of TICK timer are tested and interrupt is enabled and disabled in PIC.
24
excpt: a test of l.sys instruction. Checks all the delay slot issues ind other things.
25
cfg: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR, SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR).
26
dma: a test of DMA in normal (software) mode.
27
compress: UNIX compressed modified not to use libc calls.
28
mul: Test l.mul, l.mac and l.macrc instructions.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.